PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev.

April’03 1

PCB DESIGN
Dr. P. C. Pandey
EE Dept, IIT Bombay

Rev. Jan’16

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 2

Topics
1.General Considerations in Layout Design
2.Layout Design for Analog Circuits
3.Layout Design for Digital Circuits
4. Artwork Considerations

References
W.C. Bosshart, Printed Circuit Boards: Design and Technology, TMH,
1992
C.F. Coombs : Printed Circuits Handbook , McGraw-Hill, 2001
R.S. Khandpur : Printed Circuit Boards : Design, Fabrication, and
Assembly, McGraw-Hill, 2005.

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 3

1. GENERAL CONSIDERATIONS
IN LAYOUT DESIGN
Main issues
• Component interconnections • Effects of parasitics
• Physical accessibility of components • Power dissipation

Subtopics
1.1 Parasitic effects
1.2 Supply conductors
1.3 Component placement

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 4

1.1 Parasitic Effects

R & L of conductor tracks
C between conductor tracks

Resistance
Resistance of 35 µm thickness, 1 mm wide conductor = 5 mΩ/cm
Change in Cu resistance with temperature = 0.4% / °C
Current carrying capacity of 35 µm thickness Cu conductor (for 10 °C
temperature rise):
Width (mm) 1 4 10
Ic (A) 2 4 11

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 5

Capacitance
• Tracks opposite each other
- Run supply lines above each other
- Don’t let signal line tracks overlap for any significant distance
• Tracks next to each other
- Increase spacing between critical conductors
- Run ground between signal lines

Inductance
To be considered in
• High frequency analog circuits
• Fast switching logic circuits

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 6

1.2 Supply Conductors

Unstable supply & ground due to
• Voltage drop due to track R & L (particularly for high freq. current)
• Current spikes during logic switching ⇒ local change in Gnd & Vcc
potentials ⇒ (i) Ripples in supply voltage (Vcc–Gnd), (ii) Errors
introduced in input voltage with reference to Gnd ⇒ Digital ckts:
Possibility of false logic triggering; Analog ckts: Degradation of SNR.

Solutions
• Conductor widths : W (ground) > W (supply) > W(signal)
• Ground plane
• Track configuration for distributed C between Vcc & ground
• Analog & digital ground (&supply) connected at the most stable point
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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 7

1.3 Component Placement

• Minimize critical conductor lengths & overall conductor length
• Component grouping according to connectivity
• Same direction & orientation for similar components
• Space around heat sinks
• Packing density
• Uniform
• Accessibility for
• adjustments • component replacement • test points
• Separation of heat sensitive and heat producing components
• Mechanical fixing of heavy components

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 8

2. LAYOUT DESIGN FOR ANALOG

CIRCUITS
• Supply and ground conductors
• Signal conductors for reducing the inductive and capacitive
coupling
• Special considerations for
• Power output stage circuits
• High gain direct coupled circuits
• HF oscillator /amplifier
• Low level signal circuits

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 9

2.1 Ground & Supply Lines

• Separate GND (& Vcc) lines for analog & digital circuits
• Independent ground for reference voltage circuits
• Connect different ground conductors at most stable
reference point
• Supply lines with sufficient
width and high capacitive
coupling to GND
(use decoupling capacitors)
• Supply line should first
connect to high current drain
ckt blocks
• Supply line independent for voltage references

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 10

2.2 HF Oscillator / Amplifier

• Decoupling capacitor between Vcc & GND → Capacitive load on o/p
• Reduce capacitive coupling between output & input lines
• Vcc decoupling for large BW ckts. (even for LF operation)
• Separation between signal & GND to reduce capacitive loading

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 11

2.3 Circuits with High Power O/P Stage

Resistance due to track length & solder joints → modulation
of Vcc & GND and low freq. oscillations
• Large decoupling capacitors
• Separate Vcc & GND for power & pre- amp stages

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 12

2.4 High Gain DC Amplifier

Solder joints → thermocouple jn
Temp gradients → diff. noisy voltages

• Temp.gradients to be avoided
• Enclosure for stopping free movement of surrounding air

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 13

2.5 Low Level Signal Circuits

A) High impedance circuits - Capacitive coupling

B) Low impedance circuits - Inductive coupling

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 14

High -Z circuits
If R » 1⁄ jw(Cxy+Cy)
then coupled Vy = Va × [Cxy/(Cy+Cxy)]

• Increase separation between low level

high Z line and high level line
(decrease Cxy)
• Put a ground line between the two
(guard line)
Example: Guard for signal leakage
from FET output to input

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 15

Low – Z Circuits
• Voltage induced in ground loops due to external magnetic fields
• Current caused in the low- Z circuit loop due to strong AC currents in
nearby circuits
Vm= - (d/dt) ∫B dA

• Avoid ground loops

• Keep high current ac lines away from
low level,low Z circuit loops
• Keep circuit loop areas small

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 16

3. LAYOUT DESIGN FOR DIGITAL

CIRCUITS
Main problems
• Ground & supply line noise
• Cross-talk between neighboring signal lines
• Reflections : signal delays, double pulsing

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 17

3.1 Ground & Supply Line Noise

Noise generated due to current spikes during logic level switching,
drawn from Vcc and returned to ground

• Internal spike: charging & discharging of transistor junction

capacitances in IC ( 20 mA, 5ns in TTL)
• External spike: charging & discharging of output load capacitance

Ground potential increases, Vcc decreases: improper logic triggering.

Problem more severe for synchronous circuits.
Severity of problem (increasing): CMOS, TTL.

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 18

Solution for ground & supply noise

• Decoupling C between Vcc & ground for every 2 to 3 IC’s :
ceramic, low L cap. of 10 nf for TTL & 0.5 nF for ECL & CMOS
•Stabilizes Vcc-GND (helps against internal spikes
• Not much help for external spikes
• Low wave impedance between supply lines (20 ohms):
5 to 10 mm wide lines opposite each other as power tracks
• Ground plane : large Cu area for ground
to stabilize it against external spikes
• Closely knit grid of ground conductors
(will form ground loops, not to be used for analog circuits)
• Twist Vcc & GND line between PCBs

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 19

3.2 Cross-
Cross-talk
• Occurs due to parallel running signal lines
(ECL: 10cm,TTL: 20 cm, CMOS: 50 cm)
• Problem more severe for logic signals flowing in opposite directions

Solutions
• Reduce long parallel paths
• Increase separation
betw. signal lines
• Decrease impedance
betw. signal & ground lines
• Run a ground track
between signal lines

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 20

3.3 Reflections
Caused by mismatch between the logic output impedance
& the wave impedance of signal tracks.
• Signal delay (low wave imp.) • Double pulses (high wave imp.)

TTL (Z: 100 - 150 Ω)

0.5 mm signal line with GND plane, 1 mm without GND plane.
Signal lines between PCBs twisted with GND lines.

CMOS (Z: 150 – 300 Ω)

0.5 mm signal line without GND plane. Gnd not close to signal lines.

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 21

Summary of Layout Design Considerations

(for 1.6 mm thickness, double sided boards)

Family: TTL CMOS

Ω)
Signal–GND Zw (Ω 100 - 150 150 - 300

0.5 with Gnd 0.5, no gnd

Signal line width (mm)
1 without Gnd
Ω)
Vcc -GND Zw (Ω <5 < 20

Vcc line (mm) 5 2

GND line (mm) Very broad 5
(plane /grid)

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 22

4. ARTWORK RULES
Conductor orientation
• Orientation for shortest interconnection length.
• Conductor tracks on opposite sides in x-direction & y-
direction to minimize via holes.
• 45° or 30° / 60° orientation for turns.

Conductor Routing
• Begin and end at solder pads, join conductors for reducing
interconnection length.
• Avoid interconnections with internal angle <60°.
• Distribute spacing between conductors .
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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 23

Conductor × √
routing
examples

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 24

Solder Pads

Hole dia
• Reduce the number of different sizes.
• 0.2 - 0.5 mm clearance for lead dia.

Solder pad
• Annular ring width
≥ 0.5 mm with PTH
≈ 3 × hole dia without PTH
• Uniformity of ring around the hole.
• Conductor width d > w > d/3.

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PC Pandey: Lecture notes “PCB Design”, EE Dept, IIT Bombay, rev. April’03 25

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