A

PROJECT REPORT
ON
“4 Bit Addition using VHDL”
Submitted in partial fulfillment of the requirements of the award of degree

Of
DIPLOMA ENGINEERING
In
ELECLTRONICS AND TELECOMMUNICATION ENGINEERING
By
Mr. GANESH MAHADEV MOHITE (Roll no. 33 )

UNDER THE GUIDANCE

Prof. Ms. Raut S. A.

S.V.E.R.I.’s
COLLEGE OF ENGINEERING (POLY.).PANDHARPUR
2019-2020
 CERTIFICATE

The project report entitled “ 4 Bit Addition using VHDL” submitted by

1. Mr. Ganesh mahadev mohite

Is approved for the Diploma of Engineering in Electronics & Telecommunication Engineering

from SVERI’s College of Engineering (Polytechnic), Pandharpur, approved for the Diploma of
Engineering in Electronics &Telecommunication Engineering from SVERI’s College of
Engineering (Polytechnic), Pandharpur.

Name of guide Name of H.O.D.

(Prof.Raut S. A) (Prof .Wadekar R.M.)
Department of E&TC Department of E&TC
Engineering , Engineering,
SVERI’s COE (Poly), Pandharpur. SVERI’s COE (Poly), Pandharpur.
 ACKNOWLEDGEMENT

I take this opportunity to express my sincere thanks and deep sense of gratitude to my guide,
Ms. Raut S. A.for his constant support, motivation, valuable guidance and immense help during
the entire course of this work. Without his constant encouragement, timely advice and valuable
discussion, it would have been difficult in completing this work. I would also like to
acknowledge Electronics & Telecommunication Engineering Department who provided me the
facilities for completion of the project. We are thankful to him for sharing his experienced in
research field with me and providing constant motivation during entire project work.
I would also like to express my gratitude to all my friends who helped me a lot for
completion of my midterm project work.

Name of Student’s,

1. Ms. Ganesh mahadev mohite

 INDEX

1. INTRODUCTION

2. COMPONENTS REQUIRED

3. THEORY

4. VHDL CODE TO GENERATE SQUARE WAVE USING DAC

 INTRODUCTION

Adding two unsigned 4-bit numbers in VHDL using the VHDL addition operator (+)
– a 4-bit binary adder is written in VHDL and implemented on a CPLD.
There are many examples on the Internet that show how to create a 4-bit adder in
VHDL out of logic gates (which boils down to using logical operators in VHDL). A full
adder adds only two bits and a carry in bit. It also has a sum bit and a carry out bit. The idea
is that a number of these 1-bit adders are linked together to form an adder of the desired
length.
It may not be necessary to implement an adder in this way, as VHDL can use the
addition operator (+) to add two numbers. We will look at adding two
STD_LOGIC_VECTOR data types together.
The design is implemented on a CPLD on the home built CPLD board. Half of the
switch bank on the board (4 switches) is used to input one of the values to be added, the
other half of the switch bank is used to input the second value to be added. The result (sum)
of the addition of the two 4-bit numbers is displayed on 5 LEDs.

COMPONENTS/TOOL REQUIRED

1. Xilinx Vivado Design suite or Web pack (Download from Xilinx for free.
Registration required).
2. Mimas Artix 7 FPGA Development Board or a similar board.
3. Mimas A7 Configuration downloader software.
 THEORY

An adder is a digital circuit that performs addition of numbers. In

many computers and other kinds of processors adders are used in the arithmetic logic
units or ALU. They are also used in other parts of the processor, where they are used to
calculate addresses, table indices, increment and decrement operators and similar
operations.
Although adders can be constructed for many number representations, such
as binary-coded decimal or excess-3, the most common adders operate on binary numbers.
In cases where two's complement or ones' complement is being used to represent negative
numbers, it is trivial to modify an adder into an adder. Other signed number
representations require more logic around the basic adder.
Adders are a part of the core of an arithmetic logic unit (ALU). The control
unit decides which operations an ALU should perform (based on the op code being
executed) and sets the ALU operation. The D input to the adder above would be one such
control line from the control unit.
The adder above could easily be extended to include more functions. For example,
a 2-to-1 multiplexer could be introduced on each Bi that would switch between zero and Bi;
this could be used (in conjunction with D = 1) to yield the two's
complement of A since −A = A + 1.
 4 Bit Addition using VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binary_4_bit_adder2 is
Port ( NUM1 : in STD_LOGIC_VECTOR (4 downto 0) := "11111";
NUM2 : in STD_LOGIC_VECTOR (4 downto 0) := "11111";
SUM : out STD_LOGIC_VECTOR (4 downto 0));
end binary_4_bit_adder2;

architecture Behavioral of binary_4_bit_adder2 is

signal A : STD_LOGIC_VECTOR (4 downto 0);
signal B : STD_LOGIC_VECTOR (4 downto 0);
signal X : STD_LOGIC_VECTOR (4 downto 0);
begin

X <= A + B;

-- compensate for inverting inputs and outputs

A <= not NUM1;
B <= not NUM2;
SUM <= not X;

end Behavioral;
OUTPUT