5.

Sequential Logic

6.004x Computation Structures

Part 1 – Digital Circuits

Copyright © 2015 MIT EECS

6.004 Computation Structures L5: Sequential Logic, Slide #1

 Something We Can’t Build (Yet)
What if you were given the following design specification:
#1

When the button is pushed:

1) Turn the light on if it is off
button 2) Turn the light off if it is on light

#2 The light should change

state within a second
of the button press

What makes this device different

from those we’ve discussed before?
1. “State” – i.e., the device has memory
2. The output was changed by a input
“event” (pushing a button) rather
than an input “level”

6.004 Computation Structures L5: Sequential Logic, Slide #2

 Digital State: What We’d Like to Build

Sequence of values
Next
Trigger State
periodically Memory
Current
Device State Combinational
LOAD Logic
Input Output

Plan: Build a Sequential Circuit with stored digital STATE –

•  Memory stores CURRENT state, produced at output
•  Combinational Logic computes

•  NEXT state (from input, current state) Needed:

Loadable
•  OUTPUT bits (from input, current state) Memory

•  State changes on LOAD control input

6.004 Computation Structures L5: Sequential Logic, Slide #3
 Memory: Using Capacitors
We’ve chosen to encode information using voltages and
we know from physics that we can “store” a voltage as
charge on a capacitor:
Pros:
word line •  compact – low cost/bit
bit line (on BIG memories)
Cons:
C •  complex interface
NFET serves as
access switch VREF •  stable? (noise, …)
•  it leaks! ⇒ refresh
To write:
Drive bit line, turn on access fet, Suppose we use
force storage cap to new voltage feedback to
refresh
To read: continuously?
precharge bit line, turn on access fet,
detect (small) change in bit line voltage
6.004 Computation Structures L5: Sequential Logic, Slide #4
 Memory: Using Feedback
IDEA: use positive feedback to maintain storage indefinitely.
Our logic gates are built to restore marginal signal levels, so
noise shouldn’t be a problem!

Result: a bistable
1
0 0
1 1
0 storage element
VIN VOUT

Not affected
VTC for by noise
Feedback constraint:
inverter pair
VIN = VOUT
VOUT
Three solutions:
•  two end-points are stable
•  middle point is metastable

VIN We’ll get back to this!

6.004 Computation Structures L5: Sequential Logic, Slide #5

 Settable Memory Element
It’s easy to build a settable storage element (called a
latch) using a lenient MUX:
Here’s a feedback path,
so it’s no longer a
“state” signal
combinational circuit. appears as both
input and output

A D0 G D Q’ Q
Q’
Q
Y 0 -- 0 0
Q stable
D
B D1 0 -- 1 1
S 1 0 -- 0
Q follows D
S
G 1 1 -- 1
D: data input
G: gate input
Q: state output
6.004 Computation Structures L5: Sequential Logic, Slide #6
 New Device: D Latch
G=1: G=0:
Q follows D Q holds
Q’ 0
Circuit: Q D V1 V2
D 1

G G

Q V1 V2
D Q
Schematic TPD TPD
Symbol: G

BUT… A change in D
or G contaminates
G=1: Q Follows D, independently of Q’ Q, hence Q’ … how
can this possibly
G=0: Q Holds stable Q’, independently of D work?

6.004 Computation Structures L5: Sequential Logic, Slide #7

 A Plea for Lenience
G D Q’ Q 1. 2. 3.
1 0 X 0
D V1 V2
1 1 X 1
Q’ 0
X 0 0 0
Q G
X 1 1 1
D 1
0 X 0 0
Q V1 V2
G 0 X 1 1

TPD TPD TPD

Assume LENIENT Mux,
propagation delay of TPD
Does lenience guarantee a
Then output valid when working latch?
1.  G=1, D stable for TPD,
independently of Q’; or What if D and G
change at about
2.  Q=D stable for TPD ,
the same time…
independently of G; or
3.  G=0, Q stable for TPD ,
independently of D

6.004 Computation Structures L5: Sequential Logic, Slide #8

 …With a Little Discipline
Q’
A 0
Q
D 1
G
To reliably latch V2:
•  Apply V2 to D, holding G=1
•  After TPD, V2 appears at Q=Q’
•  After another TPD, Q’ & D
both valid for TPD; will hold
Q=V2 independently of G
•  Set G=0, while Q’ & D hold Q=D
•  After another TPD, G=0 and
Q’ are sufficient to hold
Q=V2 independently of D
6.004 Computation Structures
D Stable
D V2
G
Q V2
TPDTPD TPD
TSETUP THOLD
Dynamic Discipline for our latch:
TSETUP = 2TPD: interval prior to G
transition for which D must
be stable & valid
THOLD = TPD: interval following G
transition for which D must
be stable & valid
L5: Sequential Logic, Slide #9
 Let’s Try It Out!

New
State
D Q
Current
G State Combinational
Logic

Input Output

When G=1, latch is Transparent… Looks like a stupid

… provides a combinational path from D to Q. approach to me…

Can’t work without tricky timing constraints on G=1

pulse:
•  Must fit within contamination delay of logic
•  Must accommodate latch setup, hold times
Want to signal an INSTANT, not an INTERVAL…
6.004 Computation Structures L5: Sequential Logic, Slide #10
 Flakey Control Systems

How do we
ensure
only one
car gets
through?
Sequence
of values

Gate closed Gate open

6.004 Computation Structures L5: Sequential Logic, Slide #11

 Solution: Escapement Strategy (2 gates)

Gate 2 Gate 2

Gate 1 Gate 1

Sequence
of values

Key: at no
Gate 1: open time is there a Gate 1: closed
Gate 2: closed path through Gate 2: open
both gates
6.004 Computation Structures L5: Sequential Logic, Slide #12
 (Edge-Triggered) D Register

The gate of this

latch is open
when the clock
is low
What does
that one do? D D Q D Q Q
D master slave
0
0 Q
1
G G
1
The gate of this
S
G CLK latch is open
when the clock
is high
Observations:
•  only one latch “transparent” at any time:
•  master closed when slave is open
•  slave closed when master is open
⇒ no combinational path through register
(the feedback path in one of the master or slave latches is always active)

6.004 Computation Structures L5: Sequential Logic, Slide #13

 D-Register Waveforms

D D Q D Q Q D D Q Q
master slave
G G CLK
CLK

D
CLK

master closed master open

slave open slave closed
6.004 Computation Structures L5: Sequential Logic, Slide #14
 Um, about that hold time…

D D Q D Q Q
master slave
G G
CLK

D
CLK

The master’s contamination

delay must meet the hold time
of the slave: tCD,M ≥ tH,S

Slave latch is closing ⇒ ☆ must meet setup/hold times

but master latch is opening so ☆ may change

6.004 Computation Structures L5: Sequential Logic, Slide #15

 D-Register Timing 1
≤tPD
≥tCD

Q
D D Q Q

CLK
CLK

D
tPD: maximum propagation delay, CLK→Q ≥tSETUP ≥tHOLD
tCD: minimum contamination delay, CLK→Q
tSETUP: setup time
guarantee that D has propagated through feedback path before master
closes
tHOLD: hold time
guarantee master is closed and data is stable before allowing D to
change
6.004 Computation Structures L5: Sequential Logic, Slide #16
 Single-clock Synchronous Circuits
We’ll use registers in a highly constrained way to build
digital systems:
Does that
symbol
register?
Single-clock Synchronous Discipline
• No combinational cycles
• Single periodic clock signal
shared among all clocked
devices
• Only care about value of
register data inputs just before
rising edge of clock
• Period greater than every
combinational delay + setup time
• Change saved state after
noise-inducing logic
transitions have stopped!
6.004 Computation Structures L5: Sequential Logic, Slide #17
 Timing in a Single-clock System

QR1 Questions for register-based

D Q L D Q
reg1 reg2
designs:
•  how much time for useful work
CLK (i.e. for combinational logic
delay)?
t1
t2 •  what happens if there’s no
tPD,reg1
CLK tCD,reg1
combinational logic between
QR1 two registers?
tCD, L tPD, L
œ •  what happens if CLK signal
tSETUP,reg2
doesn’t arrive at the two
t1 = tCD,reg1 + tCD,L ≥ tHOLD,reg2 registers at exactly the
same time (a phenomenon
t2 = tPD,reg1 + tPD,L + tSETUP,reg2 ≤ tCLK known as “clock skew”)?

6.004 Computation Structures L5: Sequential Logic, Slide #18

 Model: Discrete Time

State updated every rising clock edge

Next
State
DREG
Current
Memory State Combinational
Clock Logic

Input Output

Active Clock Edges punctuate time ---

•  Discrete Clock periods
•  Sequences of states
•  Simple rules – eg truth tables – relating outputs to
inputs and the current state)
•  ABSTRACTION: Finite State Machines (next lecture!)

6.004 Computation Structures L5: Sequential Logic, Slide #19

 Sequential Circuit Timing

Next
tCD,R = 1ns
State
tPD,R = 3ns
tS,R = 2ns Current
tH,R = 2ns Combinational
State
Logic
Clock tCD,L = ?
tPD,L = 5ns
Input Output

Questions:
tCD,R (1 ns) + tCD,L(?) ≥ tH,R(2 ns)
•  Constraints on tCD for the logic? tCD,L ≥ 1 ns

•  Minimum clock period? tCLK ≥ tPD,R+tPD,L+ tS,R = 10nS

Input tPD,L
•  Setup, Hold times for Inputs?
tS,INPUT = tPD,L + tS,R = 7 nS Next State tCD,L
tH,INPUT = tH,R - tCD,L= 1 nS clk tS,R
tH,R
6.004 Computation Structures L5: Sequential Logic, Slide #20
 Summary

>tS >tH
Basic memory elements:
•  Feedback, detailed analysis D
=> basic level-sensitive
devices (eg, latch) Clk
•  2 Latches => Register Q
•  Dynamic Discipline: >tCD
constraints on input timing
<tPD
Synchronous 1-clock logic:
•  Simple rules for sequential
circuits Out
In DQ DQ
•  Yields clocked circuit with TS, Combinational
logic
TH constraints on input timing
Clk
Finite State Machines
Next Lecture Topic!

6.004 Computation Structures L5: Sequential Logic, Slide #21