Electrical Engineering

https://doi.org/10.1007/s00202-017-0673-5

ORIGINAL PAPER

Modular high-gain DC–DC converter for renewable energy microgrids

B. Sri Revathi1 · Prabhakar Mahalingam1

Received: 23 May 2017 / Accepted: 6 December 2017

© Springer-Verlag GmbH Germany, part of Springer Nature 2017

Abstract
A novel non-isolated high-step-up high-power DC–DC converter based on coupled inductor (CI) and voltage multiplier cell
(VMC) for renewable energy microgrids is presented in this paper. Hybrid combination of three-phase interleaved boost
converter with three CIs is chosen to reduce the current ripple at the input and meet the high-power requirement. Three VMCs
connected at the secondary side of the CIs serve as gain extension cells. The voltage stress experienced by the switches is only
a fraction of the output voltage as the gain extension is mainly achieved at the secondary side of CIs. Practical results obtained
from the proposed converter, which operates from a 60 V input and provides an output voltage of 1.1 kV while delivering
3 kW of output power at 92.6% efficiency, validate the proposed concept and design hypothesis.

Keywords DC–DC power converters · High step-up · High power · Interleaved boost converter · Voltage multiplier cell

1 Introduction Due to inherent current sharing mechanism, IBC is the

Electrical energy conversion from sustainable energy sources
like photovoltaic (PV) and wind energy offer significant
advantages like (i) the ease with which these sources can be
integrated with the main grid, (ii) reduced transmission losses
and cost and (iii) the support offered to existing centralized
structure to meet the increasing electrical energy demand
[1]. To extract and efficiently utilize the available power
from a PV source, the standard practice is to use a high-gain
DC–DC converter (HGDC) followed by an inverter which
subsequently supplies the loads [2,3]. The selection of an
appropriate HGDC is critical since the overall performance
of such system largely hinges on the DC–DC conversion
stage.
Conventional boost converter (CBC) suffers from prac-
tical issues like extreme duty ratio operation, large voltage
stress on the switch and diode reverse recovery problem when
employed for high-gain applications. Voltage gain of other
boost-derived converters like IBC, cascaded and quadratic
boost converters are practically limited to about four due to
constraints like higher switch stress, low efficiency, design
complexity and stability issues besides low power handling
ability [4,5].
B Prabhakar Mahalingam
prabhakar.m@vit.ac.in
1 School of Electrical Engineering, VIT, Chennai, India
prime choice to realize higher power transfer with low input
current ripple [6–9]. In an IBC, higher voltage conversion
ratio can be obtained by using a transformer (isolated con-
verters). However, non-isolated converters with appropriate
gain extension techniques are preferred mainly due to merits
like higher efficiency, reduced volume and size [10–14]. In
non-isolated DC–DC converters, some commonly used gain
extension methods are coupled inductors along with IBC,
switched capacitor cells, voltage doublers, VMC and charge-
pump technique. Though modular multilevel converters can
cater to the high-gain requirements, higher component count
reduces their efficiency [15,16].
Generally, power switches in CI-based converters experi-
ence higher voltage stress. Nevertheless, in some converters
active and passive voltage clamping is employed to suppress
the voltage spikes created due to the leakage inductance of
CI [17–20]. Some CI-based topologies like winding cross-
coupled inductors (WCCI) [21], dual-coupled inductor [22],
switched-coupled inductor [23] and multi-CI converters [24–
26] are not very popular due to manufacturing complexity
and larger switch voltage stress.
Switched capacitor (SC)-based converters alleviate the
necessity of magnetic components and make the converter
compact and light [27,28]. Unfortunately, the achievable
voltage gain is only integral times the number of SC cells
used. In [17], high step-up conversion ratio was achieved by
combining CI and SC. Voltage balancing of output capacitors

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Fig. 1 Circuit diagram of the presented converter with rearranged struc-
ture of Stage 2
present between adjacent SC cells is another tricky issue in
such converters. Voltage doublers and VMCs have simple and
modular structure [29]. Poor voltage regulation due to many
cascaded cells and higher component count dissuades the
user from practically implementing these converters, espe-
cially at few kilowatts power levels.
To meet the requirements of high step-up conversion at
high-power levels through the proposed converter, CIs are
used in the IBC instead of discrete inductors. Voltage lift
capacitor is incorporated to enhance the voltage gain of the
IBC. In the secondary side of the CI, voltage gain is extended
through the use of VMCs. Section 2 provides the circuit
composition of such a converter, while other details of the
converter are outlined subsequently.
Fig. 2 Equivalent circuit during t0 , Modes 1-1, 1-2 and Mode 2. a till [t0 ], b Mode 1-1—[t0 to t1 ], c Mode 1-2— [t0 to t1 ], d Mode 2—[t1 to t2 ]
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Electrical Engineering
2 Proposed converter
Figure 1 shows the power circuit diagram of the devel-
oped converter. The converter structure comprises two
stages. Stage 1 is formed by a three-phase IBC with primary
winding of three CIs, a voltage lift capacitor (Clift ) and a volt-
age lift diode (Dlift ). The three legs of the IBC are operated
with a uniform phase shift of 120◦ between them to reduce
the input current ripple. Clift and Dlift are used to multiply the
voltage gain of the IBC by the number of interleaved phases.
In Stage 2, each secondary winding of the CI acts as voltage
source to the VMCs formed by multiplier diodes (DM1 –DM6 )
and multiplier capacitors (CM1 –CM6 ). Three such arrange-
ments are connected in series to extend the voltage gain.
The rearranged version of Stage 2 is shown as an inset for
clarity. Stage 1 and Stage 2 are cascaded through a diode
(DIBC ) to prevent feedback of stored energy from the CIs.
Diode D0 acts as the classical boost rectifier diode, while
output capacitor C0 is used to limit the output voltage ripple.
The novel hybrid arrangement of CIs and VMCs enables the
proposed converter to yield higher voltage gain and handle
higher power simultaneously.
3 Operating principle
To elucidate the operating principle, one complete switching
cycle is fragmented into six modes. The equivalent circuit
during each mode is shown in Figs. 2a–d and 3a–d. The
operating principle of the power circuit is explained under
the valid assumptions that (i) all the semiconductor devices
Electrical Engineering

Fig. 3 Equivalent circuit for Modes 3–6. a Mode 3—[t2 to t3 ], b Mode 4—[t3 to t4 ], c Mode 5—[t4 to t5 ], d Mode 6—[t5 to t6 ]

and passive elements are ideal, (ii) the converter operates
in continuous conduction mode (CCM) and (iii) switches
Z 1 , Z 2 and Z 3 are initially turned ON for minimum time
duration to charge the primary windings of coupled inductors
L 1P , L 2P and L 3P equal to the supply voltage Vin . Figure 2a
shows the equivalent circuit during Mode 0.
Mode 1-1: (t 0 − t 1 )
To understand the working of VMCs present in Stage 2,
Mode 1 is explained in two sub-modes. In Mode1-1, Z 1 is
turned OFF while Z 2 and Z 3 are ON. Energy stored in L 1P
is discharged to its secondary winding L 1S and load through
Dlift , Clift , DIBC , L 3S , CM1 , L 2S , CM3 , L 1S , CM5 and D0 .
Meanwhile, a small portion of current ‘i x ’ flows from L 1P
through Z 2 . The charging rate of L 1S is same as the dis-
charge rate of L 1P . Voltage across CM5 is equal to the voltage
across L 1S . Diode DM5 is forward biased and charges CM6 .
Till CM6 is completely charged, DM5 conducts and DM6 is
reverse biased. At the end of Mode 1-1, CM6 is completely
charged and is ready to discharge to the load. The governing
equations during this mode are given by
 
i L 1P (t) = n i L 1S (t) + i DM5 (t) + i x (1)
1   2
i L 1S (t) = i CM5 (t) = 2 VCM4 − VCM5 × t (2)
n L 1P
 
i Dlift (t) = i DIBC (t) = i L 1P (t) = n i L 1S (t) + i DM5 (t)
= ni D0 (t), (3)
where ‘n’ is the turns ratio of the CI.
Mode 1-2: (t 0 − t 1 )
Switches Z 1 , Z 2 and Z 3 remain in the same state as Mode
1-1. As CM6 is completely charged, DM5 turns OFF and DM6
becomes forward biased. CM6 discharges the stored energy
through DM6 and D0 to the load and contributes to voltage
build-up across C0 . At the end of
 this mode, Clift is charged
1
to a voltage level equal to 1−D Vin , where ‘D’ is duty ratio
of the switches.
Mode 2: (t 1 − t 2 )
Switches Z 1 and Z 3 remain in OFF and ON state, respec-
tively. Z 2 is turned OFF to initiate the discharge of energy
stored in L 2P to the load through its secondary winding L 2S
and CM3 . Current through CM3 is given by
1  
i CM3 (t) = nVin − VCM3 × t. (4)
n 2 L 2P
 n Vin , CM4 starts
When L 2S starts linearly charging toward
nk
charging to a voltage equal to 1−D Vin through DM3 .
Transfer of stored energy from L 1P to L 1S is complete
when current through L 1P reaches a minimum value I L 1P(min) .
Meanwhile, energy stored in CM6 is also completely trans-
ferred to the load through DM2. At the
 end of Mode 2, Clift
is charged to voltage equal to 1−D Vin .
Mode 3: (t 2 − t 3 )
Switch Z 1 is turned ON to linearly charge L 1P toward
input voltage Vin . Switches Z 2 and Z 3 are maintained in
OFF and ON state, respectively. In this mode, as Z 2 alone is
OFF, stored energy in L 2P discharges to Clift . Current flowing
through primary winding L 2P is given by
 
i L 2P (t) = n i L 2S (t) + i DM3 (t) . (5)

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enables L 3P to discharge its stored energy to the load. Energy

transfer from L 3P to load occurs in two sub-modes similar
to Mode 1-1 and Mode 1-2. As Z 3 is in OFF state, D1 starts
to conduct. When current through L 2P reaches the minimum
value I L 2P(min) , CM4 begins to transfer its stored energy to the
load. The equation governing this mode is
 
i L 3P (t) = n i L 3S (t) + i DM1 (t) . (6)

Mode 5: (t4 − t5 )
Switches Z 1 and Z 3 are maintained in ON and OFF states,
respectively. Z 2 is turned ON to linearly charge L 2P toward
Vin . Energy stored in L 3P is transferred to L 3S . Current flows
from L 3P to the load through L 3S , L 2S , L 1S and the multiplier
capacitors CM1 , CM3 and CM5 . Current through CM1 is given
as

1  
i CM1 (t) = nVin − VCM1 × t. (7)
n2 L 3P

The rate at which L 3S charges is same as the discharge rate

of L 3P . The moment CM2 is completely charged, the voltage
across CM2 reverse biases DM1 . Hence, DM1 turns OFF and
DM2 comes into conduction. Stored energy in CM2 is trans-
ferred to the load through DM2 , L 2S , CM3 , L 1S , CM5 and D0 .
 theend of this mode, Clift is charged to a potential of
At
3
1−D Vin .
Mode 6: (t 5 − t 6 )
Switches Z 2 and Z 3 are maintained in ON and OFF states,
respectively. At t5 , current through L 1P reaches its maximum
current I L 1P(max) . Switch Z 1 is now turned OFF to discharge
the energy stored in L 1P to load. At t6 , current through L 3P
reaches I L 3P(min) and switch Z 3 is turned ON. This marks
the end of Mode 6 and completion of one switching cycle.
Figure 4 shows the characteristic waveforms of the proposed
converter.

4 Steady-state analysis and design details

4.1 Voltage conversion ratio

Fig. 4 Characteristic waveforms of the proposed converter
Stage 1 of the proposed converter is a three-phase IBC. As
voltage lift technique has been employed, the voltage gain of
As soon as CM4 is completely charged, DM3 turns OFF and Stage 1 is given by
DM4 comes into conduction. Mode 3 ends when CM4 starts
3
to discharge and supplies the load through DM4 and D0 . VStage 1 = VIBC = VClift = Vin . (8)
1− D
Mode 4: (t 3 − t 4 )
Switches Z 1 and Z 2 are maintained in ON and OFF state, Stage 2 of the proposed converter comprises VMCs which are
respectively. This allows L 1P to linearly charge toward Vin . embedded with the secondary winding of each CI. Therefore,
Same current flows through Z 1 and L 1P . Turning OFF Z 3 the voltage obtainable through Stage 2 is

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3k Voltage across CM2 is given by
VStage 2 = n Vin , (9)
1− D 
nk
VCM2 = VClift + Vin . (16)
where ‘n’ represents the turns ratio of CI and ‘k’ is the cou- 1− D
pling coefficient of the CI.
Using (8) and (9), the voltage gain of the proposed con- Substituting (16) in (15),
verter is derived as 
nk
VDM1 = Vin . (17)
V0 3 (1 + nk) 1− D
M= = . (10)
Vin 1− D
From VMC concept, voltage stress on other multiplier diodes
Generalizing this concept, for a converter employing ‘P’ DM2 –DM5 is equal to (17). As DM6 is present closer to the
number of interleaved phases (with ‘P’ number of CIs each output terminals, its voltage stress is minimum and same as
having ‘n’ turns ratio with ‘k’ being the coupling coeffi- the stress on D0 . Although voltage across adjacent multiplier
cient) and ‘P’ number of VMCs, the overall voltage gain cells increases steadily, the voltage stress on the multiplier
MGeneralized can be deduced as diodes is equal. Hence, diodes with identical voltage rating
are used.
V0 P (1 + nk)
MGeneralized = = . (11) 4.4 Current stress on semiconductor devices
Vin 1− D

4.2 Switch voltage stress Stage 1 of the proposed converter is asymmetrical due to
the introduction of Clift . The RMS value of currents flowing
Due to asymmetrical structure of Stage 1, the voltage stress through Z 1 , Z 2 and Z 3 is given by
on all the three switches is different and expressed as
2 1
I Z1 = Iin , I Z 2 = I Z 3 = Iin . (18)
3 V0 3 6
VZ 1 = VZ 2 = Vin = . (12)
1− D 1 + nk RMS value of current stress on D1 and Dlift will be same as
the current through Z 3 and Z 1 , respectively. Thus,
Switch Z 3 experiences a voltage stress similar to the switch
present in a CBC. Thus, 1
I D1 = I Z 3 = Iin (19)
6
1 V0 2
VZ 3 = Vin = . (13) I Dlift = I Z 1 = Iin . (20)
1− D 3 (1 + nk) 3

Though the voltage stress on all the three power switches is Since DIBC and DM1 are present just after Stage 1, the current
unequal, the converter performance is not affected. All the through them is
three switches are chosen with identical voltage rating for
1− D
ease of fabrication. I DIBC = I DM1 = Iin . (21)
3
4.3 Diode voltage stress Since the multiplier diodes DM2 –DM6 are present in the gain
extension stage, the RMS current through these diodes pro-
Diode D1 is OFF when Z 3 conducts, whereas diode Dlift is gressively decrease and is expressed as
OFF when Z 1 is ON. Both D1 and Dlift must be rated to block
the voltage obtained from one interleaved phase. Therefore, 1− D
I DM2 = I DM3 = Iin (22)
3 + nk
1 1− D
VD1 = VDlift = Vin . (14) I DM4 = I DM5 = Iin (23)
1− D 3 + 2nk
1− D
The voltage stress on DM1 is obtained when DM2 conducts. I DM6 = Iin . (24)
3 + 3nk
By applying Kirchhoff’s voltage law (KVL) around the loop
involving Clift , DIBC , DM1 and CM2 , the voltage stress is Diodes DM6 and D0 must be rated to carry the full-load
derived as current I0 . Therefore,

VDM1 = VCM2 − VClift . (15) I DM6 = I D0 = I0 . (25)

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4.5 Design of passive components Voltage across CM2 is given by (16). Each VMC cell con-
tributes to a voltage gain given by (28). Therefore, voltage
The input current ripple of a DC–DC converter used in PV across CM4 and CM6 is deduced as
applications should be minimized to efficiently harness max- 
imum power from the input PV panels. While designing the nk
VCM4 = VCM2 + Vin (29)
inductor, a judicious trade-off is made between its size and 1− D

current ripple. For the CIs used in the proposed converter, nk
the primary winding inductance is determined from VCM6 = VCM4 + Vin . (30)
1− D
Vin (VClift − 3Vin ) Output capacitor value C0 is determined from duty ratio D,
L Primary = , (26)
3 f i L VClift output current I0 , output voltage ripple V0 and the switch-
ing frequency f as
where ‘ f ’ is the switching frequency and ‘i L ’ represents
the input current ripple. D I0
The inductance value of the secondary winding is com- C0 = . (31)
f V0
puted from the turns ratio ‘n.’ The turns ratio is decided based
on the required voltage gain and is expressed as

 5 Hardware results and discussion
1 M (1 − D)
n= −1 (27)
k 3
To verify the proposed concept, converter with the specifica-
Voltage across CM1 , CM3 and CM5 is same as the voltage tions mentioned in Table 1 was fabricated and experimented.
impressed across L 3S , L 2S and L 1S , respectively. Since the Gate pulses to switches Z 1 , Z 2 and Z 3 were generated using
three CIs have same turns ratio and coupling coefficient, volt- TMS320F28027 digital signal processor (DSP). SCALE
age across these capacitors is same and given by driver board 2AP043512 was used to interface the control
and power circuit. The driver board and power module were

nk kept in close proximity to reduce EMI issues. Tektronix make
VCM1 = VCM3 = VCM5 = Vin . (28) TPS2024B digital storage oscilloscope (DSO) with four iso-
1− D

Table 1 Specifications of
Parameters Specifications/part number
proposed converter
Input voltage Vin 60 V
Output voltage V0 1.10 kV
Output power P0 3 kW
Switching frequency f 100 kHz
Duty ratio D 0.55
Turns ratio n 2.0
Coefficient of coupling k 0.875
Input ripple current 10% of input current (Iin )
Primary coupled inductors L 1P , L 2P , L 3P 18 µH, 100 kHz (L 1P -45A, L 2P -15A, L 3P -15A)
Secondary coupled inductors L 1S , L 2S , L 3S 72 µH, 10 A, 100 kHz
Power switches Z 1 , Z 2 , Z 3 (IGBTs) IXDN55N120D1 (1200 V, 100 A, 2.3 V)
Voltage lift diode Dlift VS-UFB280FA40 (400 V, 170 A)
Diodes D1 , DM1 DSEI2X101-12A (1.2 kV, 91 A)
Diode DIBC DSEI2X101-06A (600 V, 96 A)
Diodes DM6 , D0 DSS2X61-01A (100 V, 60 A)
Multiplier diodes DM2 –DM5 DSEI2X31-06C (600 V, 30 A)
Capacitors Clift , CM2 BC2799-ND (5 µF/1.2 kV)
Multiplier capacitors CM1 , CM5 495-4186-ND (4.7 µF/250 V)
Multiplier capacitor CM3 P14214-ND (4.7 µF/450 V)
Capacitors CM4 , CM6 , C0 338-1376-ND (4.7 µF/1.5 kV)
Heat sink 294-1112-ND

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Electrical Engineering
Fig. 5 Experimental results showing the voltage and current waveform
captured using the oscilloscope: test carried out at full-load condition
lated channels along with standard accessories like P5210
high-voltage probe and A622 current probes was used to
capture the key experimental waveforms.
Figure 5a shows the experimental waveforms pertaining to
gate pulses (CH1–CH3) and output voltage (CH4). The duty
ratio, frequency and the phase shift between each pulse are
in accordance with the requirement. Resultantly, the required
output voltage with very low ripple is obtained. The voltage
conversion ratio (18.3) is evident from the waveforms pre-
sented in Fig. 5b and perfectly agrees with the theoretical
value.
Figure 5c shows the voltage across the capacitors present
at various key positions in the proposed converter. Wave-
form presented in CH1 shows the potential difference across
Clift , while the remaining three channels (CH2, CH3 and
CH4) demonstrate the voltage developed across CM2 , CM4
and CM6 , respectively. Since Clift is present between two
interleaved phases, the voltage developed across Clift is
the voltage contributed by one IBC leg. The voltage built
up across CM2 , CM4 and CM6 clearly validates the imple-
mented gain extension concept. As CM6 is located at the
far end of Stage 2 and no further gain extension is envis-
aged, the potential across CM6 is same as the output
voltage.
Figure 5d shows the current through the primary wind-
ings L 1P , L 2P and L 3P along with the input current Iin .
The total input current is shared among the three inter-
leaved phases. As anticipated, the current distribution in the
interleaved phases is unequal due to asymmetry. Since the
switches are triggered with a uniform phase shift of 120◦ ,
the input current ripple is minimized. The magnitude of rip-
ple current matches very closely with the designed value; the
minor deviation (0.7 A) is attributed to the leakage present in
the CIs.
a CH1–CH3 (50 V/div): voltage across gate and emitter ter-
minals (VGE ) of the power switches Z 1 , Z 2 and Z 3 ; CH4
(500 V/div): output voltage. (Time scale 2.5 µs/div).
b CH1 (100 V/div): input voltage; CH2 and CH3 (50 V/div):
Gate pulses applied to switches Z 2 and Z 3 ; CH4
(500 V/div): output voltage. (Time scale 2.5 µs/div).
c CH1 (500 V/div): voltage across CLift ; CH2 (500 V/div):
voltage across CM2 ; CH3 (500 V/div): voltage across
CM4 ; CH4 (2 kV/div): voltage across CM6 . (Time scale
25 µs/div).
d CH1 (50 A/div), CH2 (10 A/div), CH3 (5 A/div): current
through L 1P , L 2P and L 3P , respectively; CH4 (50 A/div):
input current Iin . (Time scale 2.5 µs/div).
Figure 6a shows the voltage stress on Z 3 as related to
its gate pulse and the output voltage. The turn ON and
turn OFF instants of Z 3 are in accordance with the applied
gate pulse. Voltage stress on Z 3 is only about 12% of V0 .
In spite of large voltage conversion ratio realized in the
proposed converter, the switch voltage stress is very low
because (i) voltage gain extension occurs in Stage 2 and (ii)
VMCs present in Stage 2 act as passive recycling network
for transferring the stored energy in the leakage inductance to
the load.
Waveforms presented in Fig. 6b–d pertain to efficiency
computation at various load conditions. Under full-load
condition, the experimented converter operates at 92.63%
efficiency. This efficiency value is acceptable since the con-
verter simultaneously offers a high voltage gain of 18.3 and
delivers 3 kW output power. The voltage reduction from the
rated load to 115% of full-load condition is about 50 V which
translates to 4.54% voltage regulation at 89.78% efficiency.
At 75% load condition, the voltage regulation is 8.63% while
the efficiency is 90.10%. The presence of energy storage ele-
ments contributes to a good voltage regulation even when
operated under open-loop mode.
a CH1 (50 V/div): gate pulse of Z 3 ; CH2 (100 V/div): volt-
age stress on Z 3 ; CH3 (1 kV/div): output voltage. (Time
scale 2.5 µs/div).
b CH1 (100 V/div) and CH2 (50 A/div): voltage and current
at the input terminals, respectively; CH3 (2 kV/div) and
CH4 (2.5 A/div): voltage and current at the output; MATH
(indicated as M): output power at full load. (Time scale
5 µs/div).
c CH1 (100 V/div), CH2 (100 A/div), CH3 (2 kV/div) and
CH4 (1 A/div): same as Fig. 5b at 75% of full load. (Time
scale 5 µs/div).
d CH1 (100 V/div), CH2 (50 A/div), CH3 (2 kV/div) and
CH4 (2 A/div): same as Fig. 5b at 125% of full load.
(Time scale 2.5 µs/div).
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Fig. 6 Results from the experimented converter

The loss distribution of the converter under full-load con-

dition is calculated from (32) to (34).

Pswitch_loss = Iswitch_RMS
2
× Rswitch_O N + Pswitch_O N
+Pswitch_OFF (32)
Pdiode_loss = Vdiode_ON × Idiode_Avg
+Idiode_RMS
2
× Rdiode (33)
PCI_loss = 2
Ipy × Rpy + 2
Isy × Rsy + Pcore , (34)

where Pswitch_loss , Pdiode_loss , PCI_loss and Pcore are the power

loss occurring in the switches, diodes, coupled inductor
and magnetic/ferrite core of CI, respectively. Pswitch_ON and
Pswitch_OFF are respectively the turn ON and turn OFF power
loss occurring in the switches. Iswitch , Idiode , Ipy and Isy are
the current flowing through switch, diode, primary winding
of CI and secondary winding of CI, respectively.
From the manufacturers’ data sheet, the required param-
eters like Rswitch_ON , Rdiode and Pcore are obtained and the
respective losses are computed. Figure 7a shows the loss
distribution of the converter under full-load condition. The
conduction loss and switching loss occurring across the
power switches account for about 45% of the total losses. Fig. 7 Loss distribution and photographs of the proposed converter. a
Loss distribution of the proposed converter at full load. b Photograph
The losses occurring across the capacitors, losses occurring
of the proposed converter. c Photograph of the experimental setup
in the PCB, connecting wires, etc. are minimal and work out
to 2% of the total power.
Figure 7b shows the top-view photograph of the experi-
mented converter laid on the PCB. Modules with SOT227
package are used as power switches and diodes. The coupled
inductors operate at 100 kHz frequency and are wound using CM4 , CM6 and C0 were the tallest components with a height
litz wire to reduce conduction losses, size and volume. Con- of about 0.065 m. The overall dimensions of the converter
sequently, the three CIs are conveniently accommodated on are 0.385 m × 0.230 m × 0.065 m (length × width × height).
the PCB itself. Switches and diodes are naturally cooled using Figure 7c. shows the photograph of the experimental setup
individual peel and stick-type heat dissipators. Capacitors when the proposed converter was tested.

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Fig. 8 Performance plots of the

proposed converter. a Efficiency
and output voltage of the
proposed converter under
simulation and experimentation.
b Voltage gain capability of the
proposed converter and some
existing converters when k = 1.
c Voltage gain variation of the
developed converter for various
values of n. d Voltage gain
variation of the developed
converter for various values of k

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Table 2 Comparison of proposed converter with some existing converters

Attributes Converters presented in
[9] [17] [24] [25] Proposed

Output voltage (V0 ) 400 200 380 590 1100

Voltage gain (M) 11.11 13.33 15.83 9.83 18.33
Power handling capacity (kW) 1 0.4 0.5 0.87 3
Duty ratio (D) 0.67 0.65 0.56 0.615 0.55
Magnetic components used 2 CI 3CI 2 CI 2CI 3 CI
4 4n 4n+1 3n+1 3(1+nk)
Generalized voltage gain 1−D 1−D 1−D 1−D 1−D
expression with coupling
coefficient k = 1
Gain extension Switched Interleaved, CI, CI, diode Interleaved, Interleaved,
technique capacitors, CI and voltage capacitor three-winding lift capacitor,
quadrupler stages CI and VMC CI and VMC
Voltage stress (% of V0 ) 50 12.5 51.35 24.4 36.36
Total component count 14 20 13 16 23

6 Performance analysis and comparison with
few existing converters
The performance of the presented high-gain high-power DC–
DC converter with respect to variations in turns ratio (n),
duty ratio (D), coefficient of coupling (k) of CIs and load
conditions is presented below.
6.1 Efficiency and output voltage
Figure 8a shows the output voltage and efficiency values
at various load conditions obtained during simulation and
experimentation for the developed converter. The peak oper-
ating efficiency of the converter is about 92% under full-load
condition. When the load varies from 75 to 115% of full
load, the practical efficiency fluctuates within a narrow 3%
band. This is desirable and mainly due to the presence of
energy storage elements which ensure appropriate delivery
of demanded output power over the load range considered.
The output voltage remains almost constant over a load rang-
ing from 75 to 115% of full-load conditions. Thus, the voltage
gain capability and the design hypothesis of the converter are
validated.
Figure 8b shows the plot of ideal voltage gain (k = 1)
versus duty ratio variation for the adopted and few exist-
ing converters. Proposed converter offers the highest voltage
gain compared to other converters. Converter presented in
[9] and [25] offers the same gain as turns ratio is unity for the
converter in [25]. Figure 8c shows the voltage gain variation
of the proposed converter with variation in turns ratio n. The
desired operating point is achieved at n = 2 and k = 0.875
(experimentally determined value). Since CIs are used in the
proposed converter, its voltage gain varies as the k varies.
Figure 8d shows the voltage gain variation when k changes
from 0.875 to 1. The change in voltage gain at a particular
duty ratio is negligible and does not drastically affect the
practical output voltage.
6.2 Voltage gain and power handling capability
To appreciate the advantageous features of the presented con-
verter, its main attributes are benchmarked with converters
presented in [9,17,24] and [25]. Table 2 provides some impor-
tant attributes which are compared. All the converters that
are compared provide a voltage gain of more than 10 except
the converter in [25], whose voltage gain is 9.83. Convert-
ers presented in [9,24] and [25] use two CIs with relatively
smaller turns ratio of 1 and 1.6 in [24]. Though the volt-
age gain of converters is higher than 10 (except [25]), their
power handling capability is limited to 1 kW mainly due to the
gain extension technique adopted. In the proposed converter,
presence of IBC as its first stage with three CIs enables the
converter to handle 3 kW power at the desired voltage level.
6.3 Switch stress
In the proposed converter, the voltage stress experienced by
Z 1 and Z 2 is 36%, while Z 3 experiences a very low voltage
stress of only about 12% of the output voltage. Th reduced
switch voltage stress is attributed to Stage 2 where major-
ity of gain extension takes place. Switches used in [9] and
[24] experience a stress of about half of their output voltage,
while in [25] the switch stress is about one-fourth of the out-
put. In [17], switches are subjected to the least voltage stress
of 12.5% of its output voltage due to clamping technique
adopted.

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6.4 Component count
Proposed converter has maximum components and converter
in [24] uses least number of components. Presence of more
components in the presented converter is acceptable since
higher voltage gain and power transfer of 3 kW is simulta-
neously achieved. In [17], additional switches are used to
reduce the voltage stress on the main switches leading to
increased component count. Other converters presented in
Table 2 have a moderate component count.
6.5 MPPT implementation
To facilitate easy implementation of maximum power point
tracking (MPPT) algorithm, the relation between the duty
ratio (D), equivalent resistance (seen by the source) at max-
imum power point (RConv−MPP ) and load resistance (R L ) is
provided in (35).
converters for photovoltaic applications. Renew Sustain Energy
Rev 17:216–227
2. Kuang Y, Zhang Y, Zhou B, Li C, Cao Y, Zeng L (2016) A review
of renewable energy utilization in islands. Renew Sustain Energy
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3. Grasso AD, Pennisi S, Ragusa M, Tina GM, Ventura C (2015)
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high voltage gain and reduced switch stress. IET Power Electron
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IEEE J Emerg Sel Top Power Electron 04(2):352–362

RConv-MPP
D = 1 − (3 + 3nk) . (35)
RL
7 Conclusion
A non-isolated DC–DC converter was developed using
hybrid combination of IBC, coupled inductors, voltage lift
technique and VMCs to achieve high voltage gain at higher
power level. When excited from a 60 V input, the converter
yielded 1.1 kV at the output terminals and delivered 3 kW of
power at 92.6% efficiency. Voltage stress on the switches was
reduced due to the gain extension technique employed in the
proposed converter. The input current ripple was reduced by
using a uniformly phase-shifted three-phase IBC. Some of
the main desirable features of the described converter are
(i) modular structure, (ii) low switch voltage and current
stresses, (iii) very low input current ripple and (iv) higher
voltage conversion ratio at higher power level. These desir-
able features combined with the flexibility to extend the
voltage gain and meet standard DC voltage levels make the
converter an attractive choice for use in sustainable energy
microgrids. Standard safety precautions, suitable protection
arrangements and proper isolation must be provided before
interfacing the converter with a real-time microgrid.
Acknowledgements This work is carried out with a seed fund granted
by VIT Chennai, India through an official letter dated 14th August 2014.
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