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Altium Designer’s FPGA development environment can be used to capture, synthesize, place and
route and download a digital system design into an FPGA. Place and route, the process of
implementing the design on the target silicon, requires an intimate understanding of the functionality
and architecture of the device, a task best performed by software tools provided by the device vendor.
The vendor software is operated by the Altium Designer environment, which automatically manages all
project and file handling aspects required to generate the FPGA program file. There is a large degree
of user-control over this process, which this application note details.
Introduction
Xilinx tools are integrated and accessed in the Altium Designer environment through the Devices view
(View » Devices View). This view allows step-by-step control over the entire FPGA design process,
enabling you to program and debug your system design on the FPGA.
For information on using the Devices view to process the design, see the Processing the
Captured FPGA Design application note.
This application note makes reference to a number of Xilinx documents. Users wishing to
change any of the default settings should refer to these documents for details: Xilinx
Development System Reference Guide, Constraints Guide, and XST User Guide.
If you are not familiar with the Xilinx tools it is recommended that you start designing with the
built-in default settings.
Supported Architectures
The system supports the latest Xilinx FPGA technology and includes both FPGA and PCB schematic
library support. The following table summarizes the supported device technologies and the available
library support, at the time of publication of this document.
Virtex-II PRO Yes Xilinx Virtex-II Pro FPGA Xilinx Virtex-II Pro
For complete documentation with respect to the FPGA Generic Library, refer to the FPGA
1
Not applicable as these are configuration PROM devices.
For an example of creating a design and configuring it for a target FPGA, refer to the Getting
Started with FPGA Design tutorial in the Getting Started with Altium Designer book.
Build Options
The Build process allows
interface with Xilinx tools and
produces the bitstream (BIT) file to Options
download into your FPGA. By
clicking on the down arrow, a list of
individual steps used to complete Reports
the Build process can be found.
Click the Options icon adjacent to
each stage to configure that feature. Errors or design rules that are not allowed for your target
architecture or in the design will be picked up at each stage of the Build process. The location in the
design and the error or warning is logged in a report file, accessed by clicking on the appropriate
Report icon.
For advanced users who want more control over the options passed to the Xilinx tools, each stage in
the Build process is linked to a script file located in the \Altium Designer 6\System folder. Be
aware that these scripts are defaulted to standard optimization – any changes should be carefully
applied in consultation with the Xilinx Development System Reference Guide. Individual Build stages,
options and the corresponding default script files are described in the following sections.
Translate Design
This stage invokes the Xilinx NGDBuild tool, translating the EDIF output from the FPGA project
synthesis process to a Xilinx Native Generic Database (NGD) file and Xilinx Project Navigator project
(NPL) file. In this process, a logic design rule check is also run to confirm that the design is fit for
mapping to any target FPGA. For more information on options available with this process refer to
chapter 6 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_NGBuild.Txt script file. NGDBuild switches can be configured in this file,
in accordance with the Xilinx documentation. The Xilinx project can be opened in the Xilinx Project
Navigator if required.
information on options available with this process refer to chapter 10 of the Xilinx Development System
Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_PlaceAndRoute.Txt script file. PAR switches can be configured in this
file, in accordance with the Xilinx documentation.
Timing Analysis
This stage invokes the Xilinx Trace (timing reporter and evaluator) tool. This conducts static timing
analysis on the design, based on the input timing constraint. It verifies that the design meets the timing
constraints, generating a report on the analysis. For more information on options available with this
process refer to chapter 13 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_Trace.Txt script file. Trace switches can be configured in this file, in
accordance with the Xilinx documentation. Timing analysis can be switched off if required, click on the
Timing Analysis Options icon.
Ignore UCF file option, accessed by clicking the Options button associated with the Translate Design
stage of the Build process.
If you are not familiar with the Xilinx synthesis tools, it is recommended that you start designing
with the built-in DXP or Altium synthesis engines.
Revision History
Date Version No. Revision