ECE 375 Winter 2020 Quiz #1 Name: Key

1. Suppose that you are working with a 3-operand instruction format such as the following:
SUB z, x, y ;zx-y
Each instruction word (16 bits total) consists of a 7 bit op-code and the remaining 9 bits are evenly distributed among the 3
address fields (which we will call x, y and z). Based on this information, select the most accurate statement from below.
A) x, y, and z can each represent a register index from 0-3.
B) x, y, and z can each represent a register index from 0-7.
C) x, y, and z can each represent a register index from 0-9.
D) x, y, and z can each represent a register index from 0-31.

2. Consider the following hypothetical 1-address assembly instruction called “Add Indirect with Pre-decrement” of the form
ADD -(x) ; M(x) ← M(x) - 1, AC ← AC + M(M(x))

Suppose we want to implement this instruction on the pseudo-CPU discussed in class (augmented with a TEMP register as
shown below). An instruction consists of 16 bits: A 4-bit opcode and a 12-bit address. All operands are 16 bits. PC and MAR
each contain 12 bits. AC, MDR, TEMP each contains 16 bits, and IR is 4 bits. The original value of TEMP does not need to
be preserved.

Give the sequence of microoperations required to implement the Execute cycle for the above ADD -(x) instruction. Be sure to
perform register transfer operations in parallel when possible. Your solution should result in exactly 7 microoperations (i.e.
cycles) for the Execute cycle. The Fetch cycle is already shown below.

Fetch Cycle
Step 1: MAR ← PC;
Step 2: MDR ← M(MAR), PC ← PC+1 ; Read inst. & increment PC
Step 3: IR ← MDRopcode, MAR ← MDRaddress ;

Solution

Execute Cycle
Step 1: MDR ← M(MAR), TEMP ← AC ; Read M(x) (i.e., EA+1) and store AC
Step 2: AC ← MDR ;
Step 3: AC ← AC – 1 ; Decrement EA+1
Step 4: MDR ← AC ;
Step 5: M(MAR) ← MDR , MAR ← MDR ; Store EA back in M(x)
Step 6: MDR ← M(MAR), AC ← TEMP ; Read operand pointed to by EA and restore AC
Step 7: AC ← AC + MDR ; Add operand to AC