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Performance Analysis of 4-Leg IB APF for 3-Phase 4-Wire System with

Renewable Energy Interface Fuzzy Control DC-Bus Capacitor

Chapter · January 2020

DOI: 10.1007/978-981-32-9578-0_5

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 Performance Analysis of 4-Leg IB APF for 3-phase 4-
wire System with Renewable Energy Interface Fuzzy
control DC Bus Capacitor

Ranjeeta Patel1[0000-0001-8874-7907], Anup Kumar Panda2[0000-0001-5836-0568] and Josep M.

Guerrero3[0000-0001-5236-4592]
1
KaIinga Institute of Industrial Technology, Bhubaneswar, 751024, INDIA
2
National Institute of Technology, Rourkela, 769008, INDIA
3
Aalborg University, 9220 Aalborg East, DENMARK
ranu.susa@gmail.com,akpanda.ee@gmail.com, and joz@et.aau.dk

Abstract. This paper proposes the 4-leg active power filter (APF), which
consists of interleaved buck inverter interfaced with the photovoltaic (PV)
renewable energy source. The photovoltaic renewable energy system along with
the boost converter associated with the 4-leg interleaved buck active power
filter (4L IB APF) is not only for harmonic compensation but can well handle
the active power requirement during the load hike. The most perilous shoot-
through phenomenon associated with the conventional 4-leg inverter is fully
eliminated by this 4-leg interleaved buck inverter enhancing the reliability. The
id-iq control strategy is used for the reference compensating current generation.
Along with this, Mamdani based fuzzy logic controller (MFLC) is implemented
for the well control of inverter dc-bus capacitor voltage for having more
sensitivity to harmonics, unbalancing and dynamic condition. The detail
analysis of harmonic, neutral current, load unbalancing and active power
compensation has depicted for nonlinear three-phase and single-phase
unbalanced load for different voltage condition during steady and dynamic
state. Matlab/Simulation and OPAL Real Time simulator results verify the
efficacy and feasibility of the photovoltaic renewable energy based 4L IB APF.

Keywords: 4L IB APF, shoot-through, FLC, PV

1 Introduction

The use of a large number of power electronics devices with commercial and
industrial load makes a leaping development in the APF [1]. The key work of APF is
the harmonic compensation, but here photo voltaic (PV) renewable energy system is
interfaced with the APF to be responsible for the active power requirement of the
distribution system during unbalanced and load hike dynamic condition. The extra
active power requirement is provided by the inverter dc-bus capacitor interfaced by
the photo voltaic renewable energy system through boost converter [2-3]. Out of
various maximum power point tracking (MPPT) schemes, Perturb and Observe (P &
O) is implemented here as it is one of the unadorned method [4-6].
 2

In recent years only, the researchers are very much worried about the APF reliability.
As conventional inverter deals with the perilous shoot-through phenomenon, here the
interleaved buck inverter (IBI) is chosen with no shoot-through phenomenon [7-8].

In distribution system, due to the unbalancing of load, the flow of high neutral current
is there and is being considered as one of the most common problem. There are
various three-phase four-wire APFs for harmonic, unbalancing and neutral current
compensation, but 4-leg topology is the best. The fourth leg is specially introduced in
inverter for the alleviation of high neutral current flow causes due to unbalancing [9-
10].

The control strategy development and its implementation to the APF with satisfactory
results for ideal and non-ideal source has become a serious issue for the researchers.
On available of various control strategies the id-iq is most suitable [11]. For
controlling the dc-bus voltage of inverter, the FLC well able to normalized the PI
controller drawbacks. The inverter dc-bus capacitor voltage control is required
because it has a great impact on the harmonic current compensation performance
process. After the generation of the reference current, the switching pulses need to be
produced for the power devices of the interleaved buck inverter by some pulse width
modulation (PWM) techniques. From various research papers, a conclusion can be
drawn that the hysteresis band current controller (HBCC) is well enough for having
good accuracy and fast response [12].

This paper presents the 4L IB APF based on photo voltaic (PV) and id-iq control
strategy using FLC. Section 2 puts the clear idea about the 4-leg interleaved buck
inverter and photo voltaic based active power filter. Section 3 describes clearly about
the fuzzy based id-iq control strategy. Section 4 presents the simulation and OPAL-RT
followed by section 5 describing conclusion.

2 Three-Phase Four Leg APF (4L APF) topology

(a) (b)
Fig. 1. (a) 3-phase 4-leg conventional shunt APF (b) Dead time in the switching pulse
 3

The 3-phase 4-leg conventional shunt APF is illustrated in Fig. 1(a). It consists of an
additional leg, which has been solely added for neutral current compensation being
raised due to the unbalancing of loads as compared with split capacitor (2C)
conventional inverter based APF [1]. In this topology, the load neutral current is being
directly controlled hence more well alleviation of the neutral current.

This conventional 4-leg inverter used as APF suffers from the dangerous occurrence of
shoot-through that takes place if two power switches however turned on at same instant
of the same limb. The shoot through can be eliminated by the dead time introduction as
illustrated in Fig. 1(b), but it causes complicacy in its control scheme and non-
uniformity in the output. So, the interleaved buck inverter topology has been chosen.

Fig. 2. 4-leg interleaved buck active power filter (4L IB APF)

The interleaved buck inverter is formed by replacing the two power device limb of the
conventional inverter with one power device limb. The arrangement is made like a cell
of having two limbs for one conventional inverter limb. The each limb consists of one
power device and on series with a diode as can be seen in Fig. 2. The circuit principle
is as conventional inverter circuit [8]. Hence the conventional inverter is replaced by
power devices with discrete diodes in series; as no two power switches in each limb,
therefore, no occurrence of shoot-through phenomenon having no necessity of dead
time introduction in the switching pulse.

In, 4L IB APF arrangement, the conventional filter inductor of each phase has been
replaced by two coupling inductors for the respective phase as can be seen clearly in
the above Fig.2. However, with no shoot-through, the presented 4L IB APF topology
is more reliable and has a more prolonged lifetime with a comparison to conventional.
[6]. In this topology, the three-phase voltage (400 V) exists across the interleaved
buck inverter. The minimum requirement of dc-link voltage by the 4-leg IB APF is

= √3 × √2 × ,
given by the calculation as follows:
, (1)
 4

Here, only one dc-bus capacitor exists and hence the only voltage needs to be tracked
as required for generation of compensating current using id-iq control strategy. The
control scheme is very easy to implement due to one dc-link capacitor. As same as the
2C IB APF topology [10], it is being used for the low power application, and some
researchers being chosen this topology as the most adept alternate in 3-phase 4-wire
distribution power network to be employed in shunt APFs.

3 id-iq Control Strategy with fuzzy logic controller for PV

based 4L IB APF

Fig. 3 presents the control strategy that is FLC based id-iq for PV based 4L IB APF.
The id-iq control strategy employs the Clarke’s followed by Park’s transformation for
reference compensating currents ( ∗ , ∗ , ∗ ) generation.
The Clarke’s (αβ0) transformation applied to source voltage ( , , ) and load
current ( , , ) to get ( , ) and ( , , ) are depicted as follows:

−1 2 −1 2
1 &
= . 2 $ . % ')
3
0 √3 2 − √3 2
(2)
(

⎡ 1 −1 2 −1 2 ⎤
⎢ √3 −√3 ⎥ . % )
$ = 2 3.⎢ 0 2 2⎥
⎢1 1 1 ⎥
(3)

⎣ √2 √2 √2 ⎦

sequence equivalence current ( , 1 , ) is as follows,

Again, with the application of Park’s transformation, the active, reactive and zero

cos 6 sin 6 0 >

% 1) = %− sin 6 cos 6 0) . $ 6 = tan;< = ? A
>@
0 0 1
(4)

Where, 6 represents the instantaneous voltage vector angle. The equation (4) can also
be represented as in terms of and .
0
% 1) = . − 0 $. $
<

0 0
B C> B
(5)
>@ ?

The value of the direct voltage component can be found in terms of αβ as =

D ̅ 1D = D ̅ D= F + F
and with zero q axis voltage.
 5

Fig. 3. Block diagram of id-iq control for 4-leg interleaved buck active power filter (4L IB
APF) using FLC

The instantaneous active ( ) and reactive ( 1 ) load current comprises of both

average as well as oscillating current. The average component needs to be blocked
and the oscillating part needs to be passed out and injected by the 4L IB APF as made
known in Fig. 3. The high pass filter may be implemented directly to pass out the
oscillating component, but here an alternate arrangement has been done where the
average component is allowed to pass out by the help of low pass filter and then
deducted the average component from the total active load current( ).
H = − C <H (6)
1 H = 1 − C
1<H (7)
Where, C <H , C
1<H are the average component and H, 1 H are the oscillating
component.

The Butterworth filters are being used as low pass filter and designed for cut off
frequency 25 Hz. As can be seen in Fig. 3 another component called the first harmonic
positive sequence direct current ( C<H ) required to produce the compensating current
reference. This component C<H is obtained from the voltage regulator system of dc-
bus. Here the FLC is castoff for the generation of C<H . The two requisite dc-bus
voltage regulator inputs are dc-bus reference voltage ∗ and inverter sensed dc-bus
voltage producing the output as C<H .
 6

The error voltage ∆ = ∗" of the dc-bus is being minimized here by

implementing FLC. The two requisite inputs to the FLC are named as error (E) dc-bus

The seven variables of E and ∆E are negative (big, medium and small), zero, and
voltage and change in error (∆E) dc bus voltage which has been depicted in Fig. 3.

positive (small, medium and big) [12]. They are sequentially noted as NB, NM, NS,
0, PS, PM, and PB. With these two inputs 49 rules need to be formed to get the output
C ∗
<H . After extracting the and ∗1 that is the dq compensating current reference as

to excerpt the compensating current reference ∗ , ∗ and ∗ which is presented below

can be noted in Fig. 3, the inverse Park’s followed by Clarke’s transformation applied

∗ " 0
in equations (8) and (9).
∗
∗
$=
<
. 0 $ . ∗1 $
0 0
B C> B
(8)
∗ >@ ? ∗

1
⎡ 1 0
√2⎤ ∗
⎢ ⎥
∗
√3
∗
$ = 2 3 . ⎢" 1 2 2
1 ⎥. ∗ $
⎢ √2⎥ ∗
(9)
∗
⎢" 1 "√3 1 ⎥
⎣ 2 2 √2⎦

= ∗ + ∗ + ∗
The neutral reference compensating current can be calculated by the formula as:
∗
(10)

3.1 Photo Voltaic (PV) system with boost converter and MPPT
Here the PV array has been taken in edict to make available the active power during
the sudden hike in distribution system load. The energy stored by the inverter dc-bus
capacitor can provide the active power for a very short time, but for a long time it
cannot handle during the load hike, hence it becomes a good idea to associate the
renewable PV energy with APF for sudden compensation of active power and for a
long time. However, PV can supply power during day time only and load change can
be expected more in day time. The day time load hike can be handled well in this
method.
12 500
10
Power(W)

400
Current(A)

8
300
6
4 200
2 100
0 0
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70
Voltage(V) Voltage(V)

(a) (b) (c)

Fig. 4. (a) Detailed diagram of boost converter with MPPT system (b) PV panel curve of
current versus voltage (c) PV panel curve of power versus voltage

The PV array maximum power can be hauled out by employing the maximum power
point tracking (MPPT) scheme by means of the boost converter that has been
 7

instanced in Fig. 4(a). From existed MPPT schemes the simplest schemes perturb and
observe (P & O) is executed for tracking the PV system maximum power as
illustrated in Fig. 5 [4]. The algorithm is being started by setting the value of

to be maximized when slope ∆P⁄∆ is equal to zero. Then at specific intervals the
maximum power as an initial. In the curve of power versus voltage, the power is said

actual PV voltage as well as current are tracked out to calculate the instantaneous
power P(k). Then a slight perturbation is made to cause the change in solar PV
module power and calculated power at some delay that is P(b).

Fig. 5. Perturb and observe maximum power point tracking system used by solar array

Then a comparison is done between the P(k) and P(b) and the resultant is ∆P. If ∆P is
zero, then the duty cycle (D) is being updated, and if ∆P is not equal to zero, then

verifying the ∆V. If the slope is greater than zero, and relying on the sign, the duty
needs to check whether it has greater value than zero or not, with this, also requires

cycle (D) has to be perturbed to get the peak point which is clearly explained in Fig.
4(c). The used PV module’s voltage versus current and power versus voltage curves
is shown in Fig. 4(b) & 4(c) respectively. The characteristics of the PV panel that has
been used here, represents: maximum rated power at standard test condition (STC) is
500 W, maximum power voltage (Vmp) is 48.35 V, maximum power current (Imp) is
9.93 A. The STC defines the condition of irradiance 1000 W/m2, module temperature
25°M and air mass 1.5. The used PV system consists of 9 series modules and then the
boost converter has been used to get the required dc-bus voltage. The conversion ratio
of input to out is well known as:
=
<
<;N
(11)
 8

Where depicts the boost converter output voltage, and O are PV voltage the duty
ratio respectively.

4 Simulation and OPAL-RT Results

Switch current(Amp)
3500

2500

1500
Ethernet
Link 500
0
0.7 0.75 0.8 0.85 0.9
Time(sec)
Fig. 7(a). Conventional inverter
(a) Probe Link (b) switch current
50

Switch current(Amp)
40
(a) OPAL-Real Time Simulator
30
Lab Command Station
20
(b) OPAL-Real Time Simulator
10
(c) TPS 2014 Tektronix DSO
0
0.7 0.75 0.8 0.85 0.9
(c) Time(sec)
Fig. 6. OPAL-RT LAB Setup Fig. 7(b). Interleaved buck
inverter switch current
The parameters that applied for simulation and OPAL-RT implementation of 4L IB
APF using fuzzy based id-iq control staregy are as: 400 V(line voltage) supply voltage
(RMS), 50 Hz supply frequency, 2800 µF dc-bus capacitance, 800 V dc-bus capacitor
voltage, APF coupling capacitor 600 µH, non-linear load value : two three-phase
non-linear load R1 = 16 Ώ and L1=50 mH and one single-phase non-linear load R2 = 16
Ώ and L2 = 50 mH connected with phase-b, fuzzy logic controller Mamdani (Type-1),
Input-2, output-1, 7 triangular MFs, 49 rules, Continuous universe of discourse
fuzzification, Mamdani’s min operator implication and centroid of area defuzzification.

300
Vs(Volt)

Vdc(Volt)

50
iL(Amp)

0 800
0
-300
-50 400
0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9
Time(sec) Time(sec) Time(sec)
icb(Amp)
ica(Amp)

icc(Amp)

50 50 50
0 0 0
-50 -50 -50
0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9
Time(sec) Time(sec) Time(sec)
is(Amp)

50
isn(Amp)
iLn(Amp)

20 20
0 0 0
-50 -20 -20
0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9 0.8 0.82 0.84 0.86 0.88 0.9
Time(sec) Time(sec) Time(sec)

Fig. 8(a). Steady state simulation results of source voltage (vs), load current (iL), capacitor
voltage (Vdc), phase compensating current (ic), source current (is), load neutral current (iLn),
source neutral current (isn)
 9

50
Vs(Volt)
300 50

IL(Amp)

is(Amp)
0 0 0
-300 -50
-50
0.25 0.3 0.35 0.4 0.45 0.25 0.3 0.35 0.4 0.45 0.25 0.3 0.35 0.4 0.45
Time(sec) Time(sec) Time(sec)

50 50
ica(Amp)

icb(Amp)
50

icc(Amp)
0 0 0
-50 -50 -50
0.25 0.3 0.35 0.4 0.45 0.25 0.3 0.35 0.4 0.45 0.25 0.3 0.35 0.4 0.45
Time(sec) Time(sec) Time(sec)
1000 20
Vdc(Volt)

iLn(Amp)

is(Amp)
20
0 0
500 -20
0 0.1 0.2 0.3 0.4 0.5 -20
0.25 0.3 0.35 0.4 0.45 0.25 0.3 0.35 0.4 0.45
Time(sec) Time(sec) Time(sec)
Fig. 8(b). Dynamic state simulation results of unbalanced source voltage (vs), load current (iL),
capacitor voltage (Vdc), phase compensating current (ic), source current (is), load neutral current
(iLn) and source neutral current (isn)

vs iL

(a)

ica iLn
Vdc icb
icc is isn
(b)
Fig. 9(a).Surface viewer of FLC from MATLAB/Simulink (b) OPAL-RT steady state results of
source voltage(vs), load current (iL), capacitor voltage (Vdc), phase filter current (ic), source
current (is), load neutral current (iLn), source neutral current (isn)

Table 1. THD before and after compensation.

Supply voltage State Without APF With APF

Condition Ph-a, Ph-b, Ph-c Ph-a, Ph-b,Ph-c
Sinusoidal Steady state 29.81,19.79,29.68 3.08, 3.18, 3.17
Unbalanced Dynamic state
28.03, 41.02, 36.03 4.86,4.72, 4.10
sinusoidal

Fig. 6 depicts the OPAL-RT lab consisting of the console monitor, OP5142
reconfigurable board based OPAL-RT and data storage oscilloscope.Fig.9(a)
represents the Simulink of surface viewer of the used FLC.
 10

5. Conclusion
Fig7(a) and 7(b) presents the switch current of single phase conventional and IB
inverter respectively.As can be realized that in conventional inverter too much high
(shoot-through) current nearly 3500 A is flowing at some instant but in IB inverter the
shoot-through eliminated. Fig. 8(a) & (b) illustrates the simulation results for steady
and dynamic state with unbalanced load for ideal and non-ideal voltage supply. Fig.
9(b) provides the OPAL-RT results of steady state. The proposed PV based 4L IB
APF well proved that it is more reliable as there is no shoot-through. With this the
harmonic compensation is well below 5 % as per the IEEE 519 standard. Due to the
PV arrangement the 4L IB APF is able to provide the active power during the sudden
load hike and also during the unbalance condition

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