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Laundry Example:
Ann, Brian, Cathy, Dave
each have one load of clothes
A B C D
to wash, dry, and fold
Washer takes 30 minutes
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Sequential Laundry
6 PM 7 8 9 10 11 Midnight
Time
30 40 20 30 40 20 30 40 20 30 40 20
T
a A
s
k
B
O
r
d C
e
r
D
30 40 40 40 40 20
T
a A
s
k
B
O
r
d C
e
r
D
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Review: Unpipelined MIPS Datapath
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The Five Stages of a RISC Instruction
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5
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Example: Load Instruction
lw $1, -70($2)
lw $5, 100($0)
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Pipelining the LOAD Instruction
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
Clock
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A Pipelined MIPS Datapath
1 2 3 4 5
Load Ifetch Reg/Dec Exec Mem WrB
1 2 3 4
R-type Ifetch Reg/Dec Exec WrB
R-type uses Register File’s Write Port during its 4th stage
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Solution: Delay R-type’s Write by 1 Cycle
Delay R-type’s register write by one cycle:
Now R-type instrs also use Reg File’s write port at Stage 5
Mem stage is a NO-OP stage: nothing is being done
1 2 3 4 5
R-type Ifetch Reg/Dec Exec Mem Wr
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Summary: Key Idea of Pipelining
Each instruction has 5 stages:
Ifetch Reg/Dec Exec Mem WrB
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