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Fast Adders
http://www.syssec.ethz.ch/education/Digitaltechnik_14
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Adapted
from
Digital
Design
and
Computer
Architecture,
David
Money
Harris
&
Sarah
L.
Harris
©2007
Elsevier
Carnegie Mellon
In
This
Lecture
¢ What
slows
down
adders
§ The
“curse
of
the
carry”
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¢ The carry has to propagate from LSB to MSB
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Generate = G = A & B
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Generate = G = A & B
Propagate
=
P
=
A
^
B
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G
=
A
&
B
P
=
A
^
B
G P
Co
Ci
S
=
P
^
Ci
Co
=
G
|
(Ci
&
P)
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¢ Pi-‐1:k
=
0
(not
all
propagate
signals
from
bit
i-‐1
to
bit
k
are
1),
the
result
of
the
carry
is
generated
within
this
block.
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¢ Pi-‐1:k
=
0
(not
all
propagate
signals
from
bit
i-‐1
to
bit
k
are
1),
the
result
of
the
carry
is
generated
within
this
block.
¢ Pi-‐1:k = 1, the carry of the previous block is propagated
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¢ When carry is known, in the worst case the output is incremented
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¢ Two parallel adders, one assumes Cin 0, the other 1
¢ Once
the
previous
stage
decides
on
the
Carry,
the
correct
calculaHon
is
selected.
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C0 = Ci
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¢ Adders
differ
only
in
the
way
the
carry
propagaHon
is
calculated.
Pre
and
post
processing
is
idenHcal
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(Gi:i0,Pi:i0)
(Gn:0k,Pn:0k)
Merge Feedthrough
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¢ Number
of
Stages:
Determines
the
criHcal
path,
the
more
stages,
the
longer
the
criHcal
path
¢ Maximum
Fan
Out:
How
many
inputs
are
driven
by
a
single
cell,
determines
stage
delay,
the
more
connecHons,
the
higher
the
delay
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PPA: Sklansky
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Summary
Adders
¢ RCA
is
a
very
efficient
adder
§ It
is
the
smallest
and
simplest
adder,
for
small
bit
widths
it
is
not
too
slow
either
¢ KS
and
HC
are
very
fast,
but
suffer
from
rouHng
§ The
fastest
adders,
resource
and
rouDng
intensive
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assign a = b + c;
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