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● Because there are independent read and write channels, read and
1. AXI bus write can happen at the same time
1.1. What are the basic concepts of the AXI bus? ● AXI Protocol:
● Instead of one bus for data transaction, there are five channels. ○ Permits address info to be issued ahead of actual data
● These 5 channels are: ○ Supports multiple transactions
○ Write address ○ Supports out-or-order completion of transactions
○ Write data
○ Read address 1.4. How many sub busses does the AXI bus contain? What function does
○ Read data each perform?
○ Write response ● There are five sub busses
● Key features of AXI Protocol: ● See P1.2 for their function
○ Separate address/control and data phases
○ Support unaligned data transfers
○ Uses burst-based transactions with only start address issued 2. PCI-E
○ Separate read and write data channels 2.1. What are the layers of PCI-E?
○ Support for issuing multiple outstanding address
○ Support for out-of-order transaction completion
○ Permits easy addition of register stages to provide timing closure
1.2. How are the different portions of the AXI bus used?
● AXI is burst-based and has five independent transaction channels.
● Address channels carries control information that describes nature of
data to be transferred.
● Data channels transfer data between the master and slave by:
○ Write data channel
■ Master to slave
■ Carries write data
■ This channel is always treated as buffered, so master can
perform write transaction without slave ack of previous write
transaction
■ Slave uses write response channel to signal completion of
transfer to master
● PCI-E uses packets to communicate information between components
○ Read data channel
● Packets are formed in TL and DLL to carry information from TX to RX
■ Slave to master
● As transmitted packets flows through other layers, they are extended
■ Carries both read data and read response
with additional info necessary to handle packets at those layers
■ Read response indicates completion status of read transaction
● At RX, the reverse process occurs, and packets gets transformed from
● Write response channel responds to write transaction
PL representation to DLL representation to TLP so TL from receiving
● Each channel has a set of information signals and VALID and READY
device can process it
signals to provide a two-way handshake
○ VALID
■ From source
■ show when valid address/data/control info is available
○ READY
■ From destination
■ Show when it can accept info
○ LAST
■ Both read and write data channel have this
■ Indicate transfer of final data in transaction
● TLP Header
○ Fmt and Type provide information required to determine size of
remaining part of TLP Header
○ Traffic Class (TC) – associates Transaction with type of required
service
■ Allows differentiation of transaction into eight traffic classes
■ As packet traverses across fabric, this info is used at every
Link and within each Switch to make decisions with regards to
proper servicing of traffic
2.3. Where does input for the TLP come from? Why is it not in the spec?
● Root Complex
○ Denotes root of an I/O hierarchy that connects CPU/Memory
subsystem to I/O
● Intel did not want to get into trivia hence it is not placed above TL
2.7. Can PCI-E be handled with routers? How? 2.11. How many packet wrappings happen in PCI-E?
● Yes. Since the messages are sent through transactions which contains ● Three, once at each layer
the information of the source and destination, these packets can be
routed 2.12. Can the input and output busses work at the same time?
● Yes, since they are independent from each other. Only Ack and Nak
2.8. What actions does the physical layer perform? cross overs
● Takes packets, adds 3rd header, checks it, recode and sends to DL/Link
● Contains all circuitry for interface operations, initialization, and 2.13. How does the PCI-E bus achieve high data rates?
maintenance ● By having extremely high clocks
● PL exchanges info with DLL in implementation-specific format ● PL isolates TL and DLL from signaling technology used for Link data
● Is responsible for converting info received from DLL into an interchange
appropriate serialized format and transmitting across PCI Link ● Logical sub-block and electrical sub-block in PL coordinate state of
● Isolates TL and DL from signaling technology used for Link data each Transceiver through status and control register interface or
interchange functional equivalent
● Is divided into two sub-blocks ● PCI-E used 8b/10b encoding when data rate is 2.5 GT/s or 5.0 GT/s
○ Logical Sub-block ○ 8-bit data characters are treated as 3 bits and 5 bits mapped onto
■ Directs control and management functions of PL a 4-bit code group and a 6-bit code group, respectively
■ Has two main sections ○ Control bit with data character is used to identify when to encode
● Transmit one of the 12 special symbols included in 8b/10b transmission
○ Prepares outgoing info passed from DLL for code
transmission by electrical sub-block ○ They are concatenated to form a 10-bit symbol
● Receiver ○ Bits are placed on a Lane
○ Identifies and prepares received info before passing
to DLL
○ Electrical Sub-block
2.14. As an external bus how does PCI-E deal with low cost devices?
● If PL indicates Receiver Error ● Run at slower clock rates 2.5 GT/s or 5.0 GT/s
○ Discard any DLLP currently being received
○ Free any storage allocated for DLLP
○ Reporting such errors to software is done by PL
3. Ring busses
3.1. How does a ring bus work?
● Data is passed in a ring
2.10. How is retry enabled in the DLP?
● Each device has an in and out
● Nak DLLP
● If message is not for the device, it is passed to next device
○ TLP sequence number negative acknowledgement
○ Used to initiate a DLL Retry
● DLLP has Ack/Nak (0000_0000/0001_0000) DLLP Type Encodings for
successful/unsuccessful receipt of TLP
● Copies of transmitted TLPs must be stored in DLL Retry Buffer in the
order of their arrival, except for nullified TLPs
● Replay initiated by reception of Nak or REPLAY_TIMER expiration
3.2. How is arbitration handled on a ring bus? ■ Unidirectional 8-bit
● There is no master and slave ● Ultra Fast-mode 5MB/s
● A token is passed around the ring ○ On-chip filtering rejects spikes on bus data line to preserve data
● Whichever device requests and is granted bus ownership can start integrity
data transfer ○ Number of ICs that can be connected to same bus is limited only
by max bus capacitance
3.3. What is a token passing arbitration method?
● A token is passed among all devices on the bus ● Benefits of SPI:
● If device wishes for bus ownership, it must assert want token signal ○ Master mode and slave mode
● When request is granted, device assert have token signal until transfer ○ Bi-directional mode
is complete ○ Slave select output
● Else device passes token if no transfer or transaction is complete ○ Mode fault error flag with CPU interrupt capability
○ Double-buffered data register
○ Serial clock with programmable polarity and phase
3.4. How can high performance be obtained with a ring bus? ○ Control of SPI operation during wait mode
● Multiple rings
● Small ring size (less devices in ring, reduces latency) 4.2. Why are I2C and SPI found on most SOC designs?
● High clock rates ● Both are serial buses
● No central arbitration to avoid long wires ● Very cheap to implement in terms of pin count
● Passing continuously in large burst size ● Stable communication protocol
● Multiple messages ● Smaller printed circuit boards
● Simplified design
3.5. Why do ring busses tend to have large latency? ● Typically, lower power consumption
● Data packet has to pass all devices between sender and receiver
● This causes latency, especially if the number of devices increases 4.3. How is the protocol performed in I2C and SPI?
● Max latency occurs when sender is first node and receiver is the very ● I2C
last node 1. Send START bit (S)
2. Send slave address
3.6. What is the benefit of implementing a ring bus? 3. Send R/W bit
● Simple 4. Wait for or send Ack
● Easy to reuse because everything is built into the nodes 5. Send/receive data byte (8-bits)
● Short wires between nodes 6. Expect/send Ack bit
7. Send STOP bit (P)
3.7. Why are bi-directional busses a benefit?
● Uses less pins since transmitting (TX and RX) happens on same pin
● Complexity increases linearly with addition of devices
● If long latency in one direction, the other direction has short latency
● SPI
6.6. What is the use of the with keyword? What is the with syntax? 6.8. What other functions and variables may be placed in a class with rand
● In arrays and randc variables?
○ Accepts expression enclosed in parentheses ● Variables – integer, reg, enum, bit, array
Array Locator ● Functions
string SA[10], qs[$];
○ $urandom_range
int IA[int], qi[$]; ■ returns unsigned integer with specified range
■ Example: returns a value between 0 to 7
SA[1:5] = {“Bob”,”Abc”,”Bob”,”Henry”,”John”}; val = $urandom range(7, 0);
IA[2] = 3;
IA[3] = 13; ○ $urandom
IA[5] = 43; ■ returns 32-bit random number (seed optional)
IA[8] = 36; ■ will produce same numbers if same seed is used
IA[55] = 4; ■ Example: using $urandom
IA[28] = 1;
bit [64:0] addr;
bit [3:0] number;
//Find all items greater than 5
qi = IA.find(x ) with (x > 5); // 13,43,36
addr[32:0] = $urandom(254); // Initialize generator,
qi = IA.find(x ); // error
addr = {$urandom, $urandom}; // 64-bit random number
// Find indices of all items equal to 3
number = $urandom & 15; // 4-bit random number
qi = IA.find_index with (item == 3); // 2
○ $srandom – Allows manually seeding RNG of objects/threads
// Find first item equal to Bob ○ $set_randstate – Sets state of an object’s RNG
qs = SA.find first with (item == "Bob"); // Bob ○ $get_randstate – Retrieves current state of object’s RNG
Array Ordering 6.9. Create test cases using constraints to meet a testing requirement?
● Constraint block
string s[] = {"hello", "sad", "world"}; ○ Values of random variables are determined using constraint
s.reverse; // s = {"world", "sad", "hello"};
expression declared in constraint blocks
int q[$] = {4, 5, 3, 1}; ○ They are class members just like variables, functions, and tasks
q.sort; // q = {1, 3, 4, 5} ○ Example: ensures “mode” is between 2 and 6
class C;
struct {byte red, green, blue;} c [512]; rand bit [3:0] mode;
c.sort with (item.red); // sort red field only constraint c_mode { mode > 2;
c.rsort(x) with ({x.blue, x.green}); // green, blue mode <= 6;
};
endclass
6.10. How can pre and post functions be used to further modify a test case? ○ Example: interface using named bundle
● Every class contains pre_randomize() and interface simple_bus;
post_randomize() methods, which are automatically called by logic req, gnt;
randomize() before and after computing new random values logic [7:0] addr, data;
● Can be used to manipulate constraints logic [1:0] mode;
● pre_randomize() logic start, rdy;
endinterface : simple_bus
○ perform initialization and set preconditions before object is
randomized module memMod(simple_bus a, input logic c lk);
● post_randomize() logic avail;
○ perform cleanup, print diagnostics, and check post-conditions always @(posedge clk) a.gnt <= a.req & avail;
after object is randomized endmodule
coverpoint v_a
{
bins a = { [0:63],65 };
bins b[] = { [127:150],[148:191] }; // overlapping
bins c[] = { 200,201,202 }; 9.4. What is cross coverage? How is it used?
bins d = { [1000:$] }; // “$” max value of v_a ● cross coverage between two or more coverage points or variables
bins others[] = default; ● specified using cross construct
} ● Example: cross coverage of two 4-bit variables (a and b)
endgroup
○ coverpoint is created for each variable
● specifying bins for transitions ○ each variable has 16 bins (4-bits = 0 to 15)
○ accepts a subset of sequence ○ cross of a and b has 256 cross products, thus 256 bins
○ Example: a single value transition
bit [3:0] a, b;
value1 => value 2 covergroup cov @(posedge clk);
○ Example: sequence of transitions aXb : cross a, b;
endgroup
value1 => value3 => value4 => value5
○ Example: specifies the four transitions
9.5. What is the purpose of the 'iff' element in coverage?
range_list1 => range-list2
1,5 => 6,7 // (1=>6), (1=>7), (5=>6), (5=>7)
● the expression within the iff construct specifies an optional
condition that disables coverage for that coverpoint
○ Example: repetitions of transitions
● expressions cannot be used directly in cross; a coverage point must be
trans_item [* repeat_range]
3 [* 5] // 3=>3=>3=>3=>3
explicitly defined first
○ Example: range of repetitions
9.6. How is the coverage checking started?
3 [* 3:5]
// (3=>3=>3), (3=>3=>3=>3), (3=>3=>3=>3=>3) ● coverage starts and ends when simulation ends
○ Example: goto repetition where any number of sample points can ● declaring covergroup doesn’t start coverage collection
occur before the first occurrence of the specified value and also ● covergroup is instantiated with new operator
between each occurance (transition must immediately follow last ● In a class, instance name not required and new operator is called on
occurrence of repetition) covergroups instead of class constructor
● see 9.1
3 [-> 4] // ...=>3...=>3...=>3...=>3
9.7. How is a covergroup used? ○ have lifetime of the call or block and are initialized on each entry
● can be defined in a package, module, program, interface, or class to the call of block
● encapsulates the following information 10.4. What can be placed in a class?
○ set of coverpoints ● everything (except modules) such as
○ cross coverage between coverpoints ○ variables
○ an event that defined when a covergroup sampled ○ functions and tasks
○ other options to configure overage object ○ covergroups
○ classes
9.8. How many items may a covergroup contain?
● no limitations 10.5. What restrictions exist on class usage?
● in order to use class object, it must be instantiated
9.9. How is the data for a covergroup saved? ● classes can only see variables they created in the scope they are in
● using $coverage_save ● cannot have assertions
● saves current state of coverage to tool’s cover database ● is dynamic by nature, thus not synthesizable
$coverage_save(coverage_type, "name")
10.6. Can a class be synthesized?
● if no type specified, then all types are saved into database ● No, automatic functions are not synthesizable
9.10. Where is a good place to place a covergroup? 10.7. Why are classes a good way to write reusable code?
● outside the DUT ● a class can be extended into class and inherit another class
● classes are used to model data
9.11. Provide code to detect coverage for a given situation ● Example: a packet might be an object
● see 9.1 ○ may contain command field, address, sequence number, time
stamp, and payload
9.12. Why are post processing routines used after simulation? ○ things can be done to packet such as initializing packet, set
● for processing database of covergroups which is not in simulation commands, read packet’s status, or check sequence
● coverage tools gather information during simulation and then does
post-processing into coverage report 10.8. Provide examples of a class to perform a desired function/task with
● report is used to look for coverage holes and modify existing tests or local variables.
creating new ones to fill holes
class btclass; // Binary Tree Homework
● once coverage database is formed, you can analyze coverage data, do btclass lpt;
some post-simulation procedures, or merge data after multiple btclass gpt;
simulation runs real value;