Documente Academic
Documente Profesional
Documente Cultură
Research Article
Abstract: In this study, a novel topology for the single-phase transformerless grid-connected inverters family is proposed. By
using the series–parallel switching conversion of the integrated switched-capacitor module in a packed unit, several merits can
be added to the proposed inverter, such as higher efficiency, boosting ability within a single-stage operation, and removing the
leakage current problem by using the common grounding technique. In this study, a peak current controller strategy is
implemented in order to generate the gate pulses of semiconductor switches. Moreover, this strategy is used to control both the
active and reactive powers. Therefore, a thoroughly controlled current with a proper quality can be supplied to the grid from a
single source renewable energy resource. The operating procedure, design consideration, comparison study, and the
experimental results for a 510 W prototype are presented in order to validate the correctness and feasibility of the proposed
topology.
1 Introduction is almost constant with respect to the variation of time. In this case,
to improve the power quality supplied to the grid a unipolar PWM
The use of the transformerless inverters as an interface for scheme can be used; however extra DC–DC converters at the input
renewable energy resources like photovoltaic (PV) panels in side are needed to increase the inverter's output voltage to a proper
commercial and domestic grid-connected distributed generation level in compliance with the ac grid [10].
(DG) systems has been increased in recent years. The main In order to solve the voltage level problem in grid-connected
advantages of these inverters in comparison to the transformer- systems, many studies have been done in recent years. The variable
based systems are higher efficiency, proper power density, and high-frequency CMV in unipolar PWM method appears by
lower cost. However, some extra steps shall be taken in order to generating zero voltage level at the inverter's output voltage.
meet the requirements of the grid code [1–4]. Therefore, in order to eliminate the leakage current caused by the
The most important parameter in supplying current to the grid is variable CMV, the PV module should be separated from the ac grid
its noisy dc offset, which should be eliminated by controlling the during the freewheeling mode. To achieve this aim, H5 [12],
leakage current. This undesirable leakage current is a consequence Optimised H5 [13], different family of H6 [14–16], HERIC [17,
of variable high frequency common-mode voltage (CMV) of the 18] and HB-ZVRB [19] have modified the FB inverter by adding
inverter, which circulates between the neutral point of the ac grid extra switches and decoupling the PV source from the grid in dc or
and the parasitic capacitor of the negative terminal of the PV array, ac side during the freewheeling period. Paralleled buck [20] and
for which the parasitic capacitance value is around 100 nF per 1 Karschny [21] inverters are other case studies to maintain the CMV
kW [5, 6]. Consequently, a resonant path between the output at the relatively constant value. Nevertheless, apart from using the
inductor-based filter and the parasitic capacitor is formed, in which extra elements in the forward current flowing path, the operation of
not only can decrease the quality of the supplied current to the grid, such circuit architectures are not workable for a wide range of
but also makes additional power losses and might saturate the core demanded power factor and in some cases like the Karschny and
of the other energised distributed transformers of the ac grid. HERIC-based inverters, the reactive current injection cannot be
According to VDE 0126-1-1 IEEE standard, the value of leakage theoretically supported. Here, in all the above-mentioned circuits,
current for any type of transformerless grid-connected inverters the leakage current problem can be mitigated but never is
should not exceed 100 mA [7]. suppressed. Also, meeting the grid's voltage amplitude requirement
Due to the aforementioned code, many approaches have been is again a challenging issue since another dc–dc power processing
put forward in the literature for eliminating this leakage current. stage is required to recruit a much lower scaled PV panel at the
The simplest method for overcoming the leakage current issue is to input side of the converter.
use the bi-polar PWM strategy as well as half-bridge (HB) inverter For preserving the system against the leakage current problem,
instead of full-bridge (FB) one [8, 9]. Here, the CMV is almost the use of common-grounded type inverters can have an
constant; however, due to the presence of the output or filter's appropriate performance. In such types of inverters, the negative
inductor, the current ripple losses degrade the injected power terminal of the PV panel is directly connected to the neutral point
quality, which can violate the grid code requirements of the grid- of the grid; therefore the overall CMV can be properly bypassed
connected interfaces. Nevertheless, the output voltage of the HB [22]. From this viewpoint, a virtual dc link method with five active
inverter must have complied with the grid voltage amplitude power switches is introduced in [22]. Here, the dc link is realised
requirement, which results in another stage to increase the input by the auxiliary capacitor. During the positive half-cycle of the
voltage; therefore, it leads to extra costs and higher losses for the grid, this capacitor charges, whereas during the negative cycle one,
interface system [9]. the voltage across the capacitor is converted to the inverter's output
Another method for providing a constant CMV across the voltage. The same approach is used in [23], where the virtual dc-
parasitic capacitors can be done by implementing neutral point link capacitor is charged indirectly by a charge-pumped circuit and
clamp (NPC) or active NPC inverter [10, 11]. Here, the midpoint of a few excess diodes. In following three different common-
the dc source connecting to the dc-link capacitors is directly grounded circuit architectures were presented in [24], where the dc
connected to the neutral point of the grid, where the value of CMV to ac energy conversion can be obtainable through four power
vg According to (1) and the above equation, the ripple of the current
D= (2) through the inductor can be calculated as the following:
2V PV
vg (V out − vg)D
G= = 2D (3) ΔILf = (5)
V PV f sLf
where V out is the inverter output voltage. By replacing (3) into (5), we can also write
2V PV ⋅ vg − vg2
4 Design guidelines and loss analysis ΔILf = (6)
2 f s ⋅ Lf ⋅ V PV
In this section, the design considerations for selecting proper
values for the inductance of the L-type filter and the required value As the maximum value of the current ripple occurs at the instance
of the capacitors are presented. Moreover, based on the switching corresponds to the peak value of the grid voltage (V m, g), the
duty cycle of the proposed system, current stress analysis of the formulations for the value of Lf can be restated as follows:
switches as well as their power losses calculations, are given in the
following. 2
2V PV ⋅ V m, g − V m ,g
Lf = (7)
2 f s ⋅ V PV ⋅ ΔILf, max
4.1 Determination of inductor (L f )
The relationship between the voltage and current of an inductor is Considering 180 V as the fixed value of the PV voltage
formulated as the following [27]: (V PV = 180) and 220 2 as the V m, g along with regarding 25 kHz as
the switching frequency and 0.56 as the maximum current ripple
across the inductor, the value of Lf will be around 3 mH.
∫
t
1
V C1(t) = iC1(t)dt + vC1(0) (8)
C1 0
iL ⋅ vg
ΔV C1 = (9)
2 f s ⋅ C1 ⋅ V PV
Im, g × V m, g
C1 = (10)
2ΔV C1, max × f s × V PV
4Im, g × V m, g
C1 = (11)
2ΔV C1 × π 2 × f s × V PV
where V m, g and Im, g are the maximum values of the grid voltage
and grid or inductor current, respectively. From the proposed
current control-based strategy and Fig. 3, it is obvious that Im, g is
related to the MPPT block and the required value of active and
reactive powers injecting to the grid. According to (10) and (11),
the same procedure and result can be obtained for the C2 being
considered in the negative half-cycle of the grid voltage. Having
considered the same parameters for the V PV and V m, g as discussed
in the inductor design guideline and taken a 3.3 A maximum
current injection to the grid with the 25 kHz as the maximum
Fig. 5 switching frequency used in the proposed PCC strategy, the
(a) Applied PCC operation and the switching pulses flowchart, required capacitance will be around 120 μF.
Q6 (b) Logic-based diagram of switching pulses
0 0 0 0 0
S5 DIm, g Im, gD D ⋅ Im, g 2
rDS5Im , gD
2 f S ⋅ V PV ⋅ Im, gD(ton + toff )
; DT S < t ≤ T S
(1 − D)π π π 1−D 2
π (1 − D) 3π
I m, g Im, gD Im, g 2
rDS5Im , gD
f S ⋅ V PV ⋅ Im, gD(ton + toff )
; 0 < t ≤ DT S D
π π π π2 3π
S6 0 0 0 0 0
I m, g Im, g Im, g rDS6Im2
,g
≈0
; 0 < t ≤ DT S
π π π π 2
The equations of the current stress and power losses of the other In order to highlight the advantages of the proposed topology, a
involved switches have the same principle as mentioned for S1. comparison is conducted between the proposed inverter and the
Such calculations have been summarised in Table 1 for the other conventional ones. The results of this comparison are summarised
involved switches. in Table 2. In this study, the comparative criteria can be expressed
According to the proposed PCC method, S4 and S6 are turned as the number of active and passive components, the value of
ON during positive and negative half-cycles, respectively, while S1, passive elements, the number of ON-state switches at each
S2, S3, and S5 are switched in both half-cycles. Thus, the power loss switching instance, the required value of input voltage for grid-
of OFF switches considered to be zero, which is accordingly stated connected applications, boosting feature, output voltage type of the
in Table 1. The switching frequency of S4 and S6 is equal to the grid inverter, the leakage current elimination capability, the maximum
frequency; therefore the corresponding switching loss of them can average current stresses of switches and the weighted overall
be neglected. Regarding Table 1 and the presented procedure for system efficiency. According to Table 2, excluding the presented
calculating the switching and conduction losses of S1, the details of structure in [27], all the mentioned topologies offer a buck-based
losses for the other involved switches can be derived. characteristic without any boosting ability; therefore, in order to
meet the grid's amplitude requirement, another power processing
energy conversion stage should be added to the input dc side of
5 Comparison study such inverters. Such extra dc–dc stage affects the overall system
efficiency since the efficiency of each stage should be multiplied to
ton
PS2, SW = ∫0
f S ⋅ V DS1 ⋅ iS2 dt
ton
= ∫0
f S ⋅ V PV ⋅
Im, g ⋅ V m, g
−
Im, g ⋅ V m, g
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
cos(2ωt) dt (32)
Im, g ⋅ V m, g 1
= t − sin(2ωton)
4 ⋅ Req1 ⋅ C1 on 2ω
1
2
∫
π
1 Im, g ⋅ V m, g ⋅ sin2ω t 2
∫
π
Im, g ⋅ V m, g 1 2
2
= 1 − 2cos(2ωt) + cos (2ωt) dωt (33)
2 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1 4π 0
3
Im, g ⋅ V m, g ⋅
2
=
4 ⋅ f s ⋅ V PV ⋅ Req1 ⋅ C1
6 IET Power Electron.
© The Institution of Engineering and Technology 2019
Table 2 Comparative study
Type of Total no. No. of on Output filter Vin, Boosting Type of Leakage Max. Overallb
converter components state V feature PWM current average system
S D Ca L switches Lf1 Lf2 Cf current efficiency %
stresses of
switches
H5 5 0 1 0 3 3 mH 3 mH 0.47 μF 400 no unipolar 89 mA 0.32 × Im, g 0.95 × 0.985
= 93.5%
common- 7 2 3 1 3 2.8 mH — — 400 no unipolar 10 mA 0.16 × Im, g 95.31%
ground-type [4]
NPC [10] 6 0 2 2 4 4 mH — 2 μF 100 yes unipolar NA 0.34 × Im, g 96.33%
OH5 [13] 6 0 2 0 3 4 mH 4 mH 6.6 μF 400 no unipolar 44 mA 0.32 × Im, g 0.95 × 0.972
= 92.3%
H6 [14, 15] 6 2 2 0 3 3 mH 3 mH 0.47 μF 400 no unipolar 45 mA 0.32 × Im, g 0.95 × 0.974
= 92.5%
HERIC 6 2 1 0 2 3 mH 3 mH 2.2 μF 400 no unipolar 84 mA 0.16 × Im, g 0.95 × 0.97
= 92.1%
ActiveNPC [11] 6 0 2 0 2 NA NA NA 800 no unipolar NA 0.32 × Im, g 0.95 × 0.973
= 92.4%
Modified H6 7 0 2 0 3 3 mH 3 mH 6 μF 400 no unipolar 9 mA 0.32 × Im, g 0.95 × 0.97
[16] = 92.18%
HB-ZVR [19] 5 5 2 0 2 1.8 mH 1.8 mH 2 μF 400 no unipolar 27 mA 0.16 × Im, g 0.95 × 0.948
= %90.13
non common- 4 4 1 - 2 3 mH 3 mH 3.3 μF 400 no unipolar NA 0.32 × Im, g 0.95 × 0.987
ground-type = 93.76%
[20]
Karschny [21] 5 2 1 1 3 NA NA NA 400 no unipolar < 5 mA 0.33 × Im, g NA
virtual DC bus 5 0 2 0 2 8 mH 0.8 mH 0.34 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.95
type [22] = 90.25%
common- 4 2 2 0 2 4 mH 2 mH 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.975
ground-type = 92.62%
[23]
common-ground-type [24]
type I 4 1 2 0 2 3 mH — 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.992
= 94.24%
type II 4 1 2 0 2 3.5 mH — 2.2 μF 400 no unipolar ≃0 0.32 × Im, g 0.95 × 0.992
= 94.28%
type III 4 0 2 0 1 3 mH — 10 μF 400 no unipolar ≃0 0.16 × Im, g 0.95 × 0.978
= 92.91%
common- 2 0 2 1 1 1 mH 1 mH 2.2 μF 400 no bipolar ≃0 0.34 × Im, g 0.95 × 0.96
ground-type = %91.2
[26]
common- 5 0 2 1 2 3.5 mH — 3.3 μF 100 yes unipolar ≃0 0.34 × Im, g 92.50%
ground-type
[27]
NIIFBC [29] 6 4 2 - 4 3 mH 3 mH 2 μF 400 no unipolar 7.6 mA 0.32 × Im, g 0.95 × 0.977
= 92.81%
proposed 6 1 3 0 2 or 3 3 mH — — 200 yes unipolar ≃0 0.32 × Im, g 98.1%
Where Vin = input voltage (for 220 V grid voltage), S = switch, D = diode, C = capacitor, L = inductor, NA = not available in the publication,
aIncluding the input capacitor.
bIt shows the total system efficiency with the front-end boost stage dc-dc converter.
each other as mentioned in Table 2. Herein, it is assumed that the In following, in order to reflect the performance of the proposed
weighted efficiency of the dc–dc stage for boosting the value of the topology over the others from current stress viewpoint and
input voltage is to be 95%. Regarding these descriptions, the regarding Table 1, an average value over a full cycle of the grid's
required source for the active NPC structure presented in [11] frequency for the switching duty cycle has been considered as (35)
exceeds 750 V and the one required for the structure presented in which is derived on the basis of (2). Hereby, it is assumed to
the other references is 400 V. The common-grounded type inverters modulate all the involved switches of other mentioned structures
presented in [22–27] can eliminate the undesired leakage current, by the use of the proposed PCC-based technique. Having taken the
while the other ones can only reduce this current. If the grid same parameters like the same type of switches and the same value
demands reactive power supplied by the inverter, the value of the of the local grid voltage and considered 25 kHz switching
leakage current will be high due to some restrictions posed by the frequency used in the proposed PCC technique, the average value
modulation, although the HERIC and Karschny topologies of the switching duty cycle will be around 0.55. As it is shown in
basically are not able to pass the reverse current as for the reactive Table 2, the proposed topology possesses a suitable condition from
power support operation. the maximum average value of the current stress on the switches
Fig. 7
(a) Voltage across C1 (100 V/div),
(b) Voltage across C2 (200 V/div)
6 Experimental results
In order to revalidate the analyses and proper operation of the
proposed inverter, the experimental results of a 510 W built
prototype inverter are presented in this section. Regarding the
control block diagram of the proposed system shown in Fig. 3 and
considering the proposed PCC procedure implied in Fig. 4, the dc
voltage source has been assumed to be fixed at 180 V. In this case,
the details of the MPPT process of the proposed system are beyond
the scope of the paper, a PV simulator as the dc source and the
Beagle Bone Black (Texas instrument) as the microprocessor have
been used to implement the proposed PCC method. The circuit
elements used in the prototype inverter and their description are
summarised in Table 3. Here the peak and frequency of the local
grid's voltage are respectively 311 V and 50 Hz.
As explained in Fig. 3, a hardware-based PLL procedure has
been used to detect the zero-crossing point of the local grid
voltage. Such detection is used to find out the phase of the
Fig. 6 Obtained experimental results reference current used in the proposed PCC. Considering such PLL
(a) Inverter output voltage waveforms (200 V/div) and the injected current (4 A/div), and 3.3 A as the amplitude obtained by the PV simulator, a proper
(b) Inverter output voltage waveforms (200 V/div) and the local grids voltage (200 V/ reference current is made. Such a peak value of the reference
div), current has been obtained by the P&O MPPT technique, like what
(c) Reference current (up-side) (4 A/div) and the injected current (down-side) (4 A/ has been using in the conventional approach.
div) waveforms Regarding the working principle of the proposed topology
Fig. 6a shows the inverter output voltage with the peak of the 360
aspect. Here, the maximum value of the average current stress V besides the injected grid current waveform with the peak value
among different involved switches has been considered. of 3.3 A. As it is clear, through a 180 V input dc voltage, a two
times voltage boosting feature has been obtained which results in
V m, g 1 360 V as the peak voltage value of the proposed inverter. The
Davg = × (35) unipolar boosted three-level output voltage of the proposed inverter
V PV π
and the local grid's voltage have also been depicted in Fig. 6b,
According to this table, the proposed structure, which consists of while the reference current and the injected grid current waveform
six semiconductor switches and a reduced number of passive generated by the proposed current-controlled technique have been
elements, has the capability to eliminate the leakage current, while shown in Fig. 6c. Considering such taken results, the realisation of
it possesses two times boosting feature. Due to the step-up the PCC method and fine tracking capability of the proposed
capability of the proposed structure, the required dc power source method can be confirmed. Here, the total harmonic distortion of the
or the PV panel value is 200 V, which results in lower costs, power current supplied to the grid is <2.1%.
losses, and system size. Moreover, the conduction loss of the Additionally, the balanced voltage waveforms across C1 and C2
proposed structure is quite compatible with the other conventional as well as the injected current are presented in Figs. 7a and b,
topologies, since the number of conducting switches in the first respectively. According to Fig. 7, the voltages across C1 and C2
three operating modes and in the fourth one is two or three. The have satisfactory ripples through the explained self-voltage
structures presented in [26, 27] have fewer switches, however, balancing and they could be fixed at 180 and 360 V, respectively.
some extra passive elements are added to their topologies. In this
Table 4 Details of switching and conduction losses of different involved power switches and diodes in the proposed topology
Pout, W S1 S2 S3 S4 S5 S6 D1 D2 Tot. loss, W
PCon
P 100 0.0014 0.0724 0.0014 0.0026 0.0017 0 0.091 0 0.773
N 0.0017 0.0017 0 0.0014 0.0026 0.0908 0.1838
PSw
P 0.015 0.1378 0.015 0 0.031 0 0.0101 0
N 0.015 0.015 0 0.031 0 0.0101 0.0405
Tot., W 0.0331 0.2102 0.0331 0.0026 0.0651 0.0026 0.202 0.2243
PCon
P 300 0.0127 0.6522 0.0127 0.023 0.0155 0 0.2786 0 2.869
N 0.0155 0.0155 0 0.0127 0.023 0.2771 0.5739
PSw
P 0.0451 0.4134 0.0451 0 0.0902 0 0.0304 0
N 0.0451 0.0451 0 0.0902 0 0.0304 0.1216
Tot., W 0.1184 1.0656 0.1184 0.023 0.2086 0.023 0.6165 0.6955
PCon
P 500 0.0351 1.8118 0.0351 0.0639 0.043 0 0.4736 0 5.7053
N 0.043 0.043 0 0.0351 0.0639 0.4694 0.9936
PSw
P 0.0752 0.6891 0.0752 0 0.1504 0 0.0507 0
N 0.0752 0.0752 0 0.1504 0 0.0507 0.2027
Tot., W 0.2285 2.5009 0.2285 0.0639 0.3789 0.0639 1.0444 1.1963
PCon
P 700 0.0689 3.5512 0.0689 0.1252 0.0842 0 0.676 0 9.2795
N 0.0842 0.0842 0 0.0689 0.1252 0.6677 1.4431
PSw
P 0.1052 0.9647 0.1052 0 0.2104 0 0.0709 0
N 0.1052 0.1052 0 0.2104 0 0.0709 0.2837
Tot., W 0.3635 4.5159 0.3635 0.1252 0.5739 0.1252 1.4855 1.7268
In order to calculate the losses in this table, the following values are used: P = positive half cycle, N = negative half cycle, PCon = conduction loss, PSw = switching loss.
By measuring the input and output powers, the efficiency of the vg V m, gsin(ω t)
D= = ⇒ Dave = 0.55 (37)
proposed structure is captured, which is around 98%. Fig. 8 shows 2V PV 2V PV
the efficiency curve of the proposed inverter for different output
powers. rDS = 0.061 Ω , ton, S = 35 ns , toff , S = 143 ns (38)
As it is obvious, the proposed topology with its PCC technique
possesses around 98.1% as the overall efficiency for a wide range rD = 0.033 Ω , V γ = 0.8 V, ton, D = 60 ns, toff , D = 60 ns (39)
of output power. Herein, to consider the details of switching and
conduction losses of different power switches and diodes used in
where the maximum value of the grid current to the grid and the
the proposed structure. Table 4 can be taken into account.
maximum grid voltage are expressed by (36), while considering
Regarding the internal resistance of the power switches and diodes
(2), the average value of the switching duty cycle is denoted by
derived from datasheet thereof and considering the procedure
(37). Also, the information about the internal resistance of the
presented for switching and conduction loss calculation in Section
switches and diodes are also shown in (38) and (39), respectively.
4.3 and Table 1, the details of losses for different active and passive
In this case, regarding (31), the maximum value of the current
devices can be realised here. In this case, the following parameters
passing through the S2 which occurs at ω t = π/2 can be
have been used for a proper loss calculation:
expressed by the following equation: (see (40)) .
2Pout To confirm this derived value for the current stress of S2, Fig. 9
I m, g = , V m, g = 220 2 (36) can be considered. As shown here, the peak current of this switch
V m, g
is about 8.8 A, which is accorded by the relation expressed as (40).
From Table 4, it is also found that the highest value of total
power losses for different value of output power belongs to S2,
IET Power Electron. 9
© The Institution of Engineering and Technology 2019
Im, g ⋅ V m, g
IS2, max =
2. f s ⋅ V PV ⋅ Req1 ⋅ C1
(40)
3.2 × 220 2
= = 8.8 A
2 × 25 × 103 × 180 × (0.061 + 0.033 + 0.01) × 120 × 10−6
Fig. 10 Grids voltage (100 V/div) and the injected current (5 A/div)
waveforms under
(a) Leading PF,
(b) Lagging PF
while two low-frequency switches (S4 and S6) possess the minimal
ones.
To confirm the accurate performance of the proposed controlled
system under the non-unity PF value, the voltage and current of the
grid for leading and lagging power factors are shown in Figs. 10a Fig. 11 Experimental results of the proposed topology in a dynamic state
and b. According to the experimental results, the output current of (a) Grid voltage(100 V/div) and the injected current to the grid (5 A/div),
the proposed structure controlled by the PCC method generates a (b) Voltage of capacitor C1 (100 V/div) and the injected current to the grid (5 A/div),
sinusoidal waveform for any needed PF. (c) Voltage of capacitor C2 (200 V/div) and the injected current to the grid (5 A/div),
In the following of the dynamic results clarification, the overall (d) Output voltage of inverter (400 V/div) and the injected current to the grid (5 A/div)
performance of the proposed inverter under the input power
changes can be observed in Fig. 11. In this case, since the 7 Conclusion
performance of the MPPT block may affect the dynamic result of A new topology of single-phase grid-tied inverters was proposed in
the proposed current-controlled technique, so the MPPT block has this paper. In the proposed structure, in order to provide a boost
been excluded, and only the peak value of reference current feature, the SC technique was used as well as the provision of the
changes has been applied. Regarding this, once the input voltage common ground feature. The capacitors used in the SC module of
possesses an upward trend, the input power will be increased. So, the proposed inverter are balanced by series–parallel switching
through increasing the range of input voltage, the active power has conversion and can handle the power-boosting single-stage process
changed from 510 to 620 W. Therefore, the injected current to the in the positive and negative half-cycle of the grid frequency.
grid has changed from a peak value of 3.2 to 4 A, as shown in According to the introduced PCC method, by using a small-sized
Fig. 11a. Figs. 11b and c also show the capacitors voltage inductor-based filter the injected current can be thoroughly
variations along with the variations in the injected current to the controlled for any desired value of power factor. The leakage
grid. It can be seen that when the output power is increased, the current issue is solved by common grounding the neutral point the
voltage of the capacitor is slightly increased. Fig. 11d also shows grid and the negative terminal of the PV panel. In this paper, the
the output voltage of the inverter along with the injected current to design considerations for the proposed structure were presented as
the grid. As can be concluded from these results, the performance well as the power loss analyses for the switches. Moreover, in
of the control system and the inverter are desirable in response to order to highlight the advantages and disadvantages of the
the power changes.
Q Please make sure the supplied images are correct for both online (colour) and print (black and white). If changes are required
please supply corrected source files along with any other corrections needed for the paper.
Q1 As per journal style references are renumbered in the text and reference list. Please confirm.
Q2 Please check your references thoroughly as we have updated them according to Crossref, and not all information may be correct.
Q3 Please confirm inserted year, volume and page ranges as per crossref.org in Ref. [23]
Q4 References [30, 31] are listed in the reference list but not cited in the text. Please cite in the text, else delete from the list.
Q5 Please provide place of conference in Ref. [30].
Q6 Please supply a main caption for figures 5, 7. Please note this should not contain the subfigure captions as these should be defined
separately.