Microcontroller

Embedded Systems Design: A Unified
Embedded systems overview

Hardware/Software Introduction
• Embedded computing systems
Computers are in here...
– Computing systems embedded within
electronic devices and here...
– Hard to define. Nearly any computing and even here...

system other than a desktop computer
– Billions of units produced yearly, versus
millions of desktop units
– Perhaps 50 per household and per
automobile Lots more of these,
though they cost a lot
less each.
1 Embedded Systems Design: A Unified 4

Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Outline A “short list” of embedded systems

Anti-lock brakes Modems
Auto-focus cameras MPEG decoders
• Embedded systems overview Automatic teller machines
Automatic toll systems
Network cards
Network switches/routers
Automatic transmission On-board navigation
– What are they? Avionic systems
Battery chargers
Pagers
Photocopiers
Camcorders Point-of-sale systems
• Design challenge – optimizing design metrics Cell phones
Cell-phone base stations
Portable video games
Printers
Cordless phones Satellite phones
• Technologies Cruise control

Curbside check-in systems
Digital cameras
Scanners
Smart ovens/dishwashers
Speech recognizers
– Processor technologies Disk drives

Electronic card readers
Stereo systems
Teleconferencing systems
Electronic instruments Televisions
– IC technologies Electronic toys/games

Factory control
Temperature controllers
Theft tracking systems
Fax machines TV set-top boxes
– Design technologies Fingerprint identifiers
Home security systems
VCR’s, DVD players
Video game consoles
Life-support systems Video phones
Medical testing systems Washers and dryers
And the list goes on and on

Embedded Systems Design: A Unified 2 Embedded Systems Design: A Unified 5
Hardware/Software Introduction, (c) 2000 Vahid/Givargis Hardware/Software Introduction, (c) 2000 Vahid/Givargis
Some common characteristics of embedded

Embedded systems overview
systems
• Computing systems are everywhere • Single-functioned
• Most of us think of “desktop” computers – Executes a single program, repeatedly
– PC’s • Tightly-constrained
– Laptops – Low cost, low power, small, fast, etc.
– Mainframes • Reactive and real-time
– Servers – Continually reacts to changes in the system’s environment
• But there’s another type of computing system – Must compute certain results in real-time without delay
– Far more common...

1
An embedded system example -- a digital
Design challenge – optimizing design metrics
camera
Digital camera chip • Common metrics (continued)
CCD
A2D
CCD preprocessor Pixel coprocessor D2A – Time-to-prototype: the time needed to build a working version of the
system
lens
– Time-to-market: the time required to develop a system to the point that it
JPEG codec Microcontroller Multiplier/Accum
can be released and sold to customers
DMA controller Display ctrl – Maintainability: the ability to modify the system after its initial release
– Correctness, safety, many more
Memory controller ISA bus interface UART LCD ctrl
• Single-functioned -- always a digital camera

• Tightly-constrained -- Low cost, low power, small, fast
• Reactive and real-time -- only to a small extent
Design metric competition -- improving one

Design challenge – optimizing design metrics
may worsen others
• Obvious design goal: Power • Expertise with both software
– Construct an implementation with desired functionality and hardware is needed to
Performance Size
optimize design metrics
• Key design challenge: – Not just a hardware or
– Simultaneously optimize numerous design metrics software expert, as is common
NRE cost – A designer must be
• Design metric comfortable with various
– A measurable feature of a system’s implementation CCD
Digital camera chip technologies in order to choose
CCD preprocessor Pixel coprocessor D2A the best for a given application
– Optimizing design metrics is a key challenge A2D
lens
and constraints
JPEG codec Microcontroller Multiplier/Accum
DMA controller Display ctrl Hardware
Memory controller ISA bus interface UART LCD ctrl

Software

Design challenge – optimizing design metrics Time-to-market: a demanding design metric
• Common metrics • Time required to develop a

– Unit cost: the monetary cost of manufacturing each copy of the system, product to the point it can be
excluding NRE cost sold to customers
– NRE cost (Non-Recurring Engineering cost): The one-time • Market window
Revenues ($)
monetary cost of designing the system – Period during which the

– Size: the physical space required by the system product would have highest
sales
– Performance: the execution time or throughput of the system
• Average time-to-market
– Power: the amount of power consumed by the system Time (months) constraint is about 8 months
– Flexibility: the ability to change the functionality of the system without • Delays can be costly
incurring heavy NRE cost

2
Losses due to delayed market entry NRE and unit cost metrics
• Compare technologies by costs -- best depends on quantity

• Simplified revenue model – Technology A: NRE=$2,000, unit=$100
Peak revenue
– Product life = 2W, peak at W – Technology B: NRE=$30,000, unit=$30
Peak revenue from
Revenues ($)
delayed entry – Time of market entry defines a – Technology C: NRE=$100,000, unit=$2

On-time triangle, representing market $200,000
A
$200
A
Market rise Market fall penetration $160,000
B
$160
B
C C
to ta l c ost (x1000)
p e r p rod uc t c ost
Delayed – Triangle area equals revenue $120,000 $120
• Loss $80,000 $80
D W 2W – The difference between the on- $40,000 $40
On-time Delayed Time time and delayed triangle areas $0 $0

entry entry 0 800 1600 2400 0 800 1600 2400
Num b e r of units (volu m e) Num b e r o f units (vo lu m e)
• But, must also consider time-to-market

Losses due to delayed market entry (cont.) The performance design metric
• Widely-used measure of system, widely-abused

• Area = 1/2 * base * height – Clock frequency, instructions per second – not good measures
Peak revenue – On-time = 1/2 * 2W * W – Digital camera example – a user cares about how fast it processes images, not
– Delayed = 1/2 * (W-D+W)*(W-D) clock speed or instructions per second
Peak revenue from
Revenues ($)
delayed entry
• Percentage revenue loss = • Latency (response time)
On-time
– Time between task start and end
Market rise Market fall (D(3W-D)/2W2)*100% – e.g., Camera’s A and B process images in 0.25 seconds
Delayed • Try some examples • Throughput
– Lifetime 2W=52 wks, delay D=4 wks – Tasks per second, e.g. Camera A processes 4 images per second
D W 2W
– (4*(3*26 –4)/2*26^2) = 22% – Throughput can be more than latency seems to imply due to concurrency, e.g.
On-time Delayed Time – Lifetime 2W=52 wks, delay D=10 wks Camera B may process 8 images per second (by capturing a new image while
entry entry – (10*(3*26 –10)/2*26^2) = 50% previous image is being stored).
– Delays are costly! • Speedup of B over S = B’s performance / A’s performance
– Throughput speedup = 8/4 = 2

NRE and unit cost metrics Three key embedded system technologies
• Costs: • Technology
– Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost – A manner of accomplishing a task, especially using technical
– NRE cost (Non-Recurring Engineering cost): The one-time monetary cost of processes, methods, or knowledge
designing the system
– total cost = NRE cost + unit cost * # of units • Three key technologies for embedded systems
– per-product cost = total cost / # of units – Processor technology
= (NRE cost / # of units) + unit cost
• Example – IC technology
– NRE=$2000, unit=$100 – Design technology
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300
Amortizing NRE cost over the units results in an
additional $200 per unit

3
Processor technology Single-purpose processors
• The architecture of the computation engine used to implement a • Digital circuit designed to execute exactly Controller Datapath
system’s desired functionality one program Control index
• Processor does not have to be programmable – a.k.a. coprocessor, accelerator or peripheral logic
total
– “Processor” not equal to general-purpose processor
Controller Datapath
• Features State
register +
Controller Datapath Controller Datapath
Control Control logic Registers

Control index – Contains only the components needed to
Register logic
logic and
State register
file and State
register
total execute a single program Data
Custom State +
General
ALU register
– No program memory memory
IR PC ALU IR PC
Data Data • Benefits
memory memory
Program Data Program memory – Fast
memory memory
Assembly code Assembly code
for:
– Low power
for:
total = 0 total = 0 – Small size

for i =1 to … for i =1 to …
General-purpose (“software”) Application-specific Single-purpose (“hardware”)

Processor technology Application-specific processors
• Processors vary in their customization for the problem at hand • Programmable processor optimized for a Controller Datapath
total = 0 particular class of applications having Control Registers

logic and
for i = 1 to N loop common characteristics State register
total += M[i] – Compromise between general-purpose and Custom
end loop ALU
Desired single-purpose processors IR PC
functionality • Features Data
Program memory
– Program memory memory
– Optimized datapath Assembly code
– Special functional units for:
total = 0
• Benefits for i =1 to …
General-purpose Application-specific Single-purpose
processor processor processor – Some flexibility, good performance, size and
power
General-purpose processors IC technology

• Programmable device used in a variety of
applications Controller Datapath • The manner in which a digital (gate-level)
– Also known as “microprocessor” Control Register implementation is mapped onto an IC
logic and file
• Features State register – IC: Integrated circuit, or “chip”
– Program memory General – IC technologies differ in their customization to a design
– General datapath with large register file and IR PC ALU
general ALU – IC’s consist of numerous layers (perhaps 10 or more)

• User benefits Program Data • IC technologies differ with respect to who builds each layer and
memory memory when
– Low time-to-market and NRE costs
Assembly code
– High flexibility for:
• “Pentium” the most well-known, but total = 0

gate
for i =1 to …
there are hundreds of others IC package IC
source
oxide
channel drain
Silicon substrate

4
IC technology PLD (Programmable Logic Device)
• Three types of IC technologies • All layers already exist

– Full-custom/VLSI – Designers can purchase an IC
– Semi-custom ASIC (gate array and standard cell) – Connections on the IC are either created or destroyed to
– PLD (Programmable Logic Device) implement desired functionality
– Field-Programmable Gate Array (FPGA) very popular
• Benefits
– Low NRE costs, almost instant IC availability
• Drawbacks
– Bigger, expensive (perhaps $30 per unit), power hungry,
slower
Full-custom/VLSI Moore’s law
• All layers are optimized for an embedded system’s • The most important trend in embedded systems
particular digital implementation – Predicted in 1965 by Intel co-founder Gordon Moore
– Placing transistors IC transistor capacity has doubled roughly every 18 months
– Sizing transistors for the past several decades
– Routing wires 10,000
1,000
• Benefits Logic transistors 100

per chip 10
– Excellent performance, small size, low power (in millions) 1
0.1
• Drawbacks Note:
0.01
logarithmic scale
– High NRE cost (e.g., $300k), long time-to-market 0.001

Semi-custom Moore’s law
• Lower layers are fully or partially built • Wow

– Designers are left with routing of wires and maybe placing – This growth rate is hard to imagine, most people
some blocks underestimate
– How many ancestors do you have from 20 generations ago
• Benefits • i.e., roughly how many people alive in the 1500’s did it take to make
– Good performance, good size, less NRE cost than a full- you?
custom implementation (perhaps $10k to $100k) • 220 = more than 1 million people
– (This underestimation is the key to pyramid schemes!)
• Drawbacks
– Still require weeks to months to develop

5
Graphical illustration of Moore’s law The co-design ladder
• In the past: Sequential program code (e.g., C, VHDL)
1981 1984 1987 1990 1993 1996 1999 2002 Behavioral synthesis
– Hardware and software Compilers
(1990's)
(1960's,1970's)
design technologies were
10,000 150,000,000 Register transfers
transistors transistors very different Assembly instructions RT synthesis
– Recent maturation of Assemblers, linkers
(1980's, 1990's)
Leading edge Leading edge
chip in 1981 chip in 2002 synthesis enables a unified (1950's, 1960's) Logic equations / FSM's
Logic synthesis
view of hardware and (1970's, 1980's)
Machine instructions
software Logic gates
• Something that doubles frequently grows more quickly • Hardware/software

Implementation
than most people realize! “codesign” Microprocessor plus

program bits: “software”
VLSI, ASIC, or PLD
implementation: “hardware”
– A 2002 chip can hold about 15,000 1981 chips inside itself The choice of hardware versus software for a particular function is simply a tradeoff among various
design metrics, like performance, power, size, NRE cost, and especially flexibility; there is no
fundamental difference between what hardware or software can implement.

Independence of processor and IC

Design Technology
technologies
• The manner in which we convert our concept of • Basic tradeoff
desired system functionality into an implementation – General vs. custom
Compilation/
Synthesis
Libraries/
IP
Test/
Verification
– With respect to processor technology or IC technology
System System Hw/Sw/ Model simulat./ – The two technologies are independent
Compilation/Synthesis: specification synthesis OS checkers
Automates exploration and
insertion of implementation
details for lower level. General- Single-
purpose ASIP purpose
Behavioral Behavior Cores Hw-Sw
specification synthesis cosimulators
General, processor processor Customized,
Libraries/IP: Incorporates pre- providing improved: providing improved:
designed implementation from
lower abstraction level into Flexibility
higher level. RT RT RT HDL simulators Power efficiency
specification synthesis components Maintainability Performance
NRE cost Size
Test/Verification: Ensures correct Time- to-prototype
functionality at each level, thus Cost (high volume)
reducing costly iterations Logic Logic Gates/ Gate Time-to-market
between levels. specification synthesis Cells simulators Cost (low volume)
To final implementation PLD Semi-custom Full-custom

Design productivity exponential increase Design productivity gap

100,000
• While designer productivity has grown at an impressive rate
10,000
over the past decades, the rate of improvement has not kept
(K) Trans./Staff – Mo.
1,000
pace with chip capacity
Productivity
100
10,000 100,000
10
1,000 10,000
1 Logic transistors 100 1000
per chip 10 Gap 100 Productivity
0.1 IC capacity (K) Trans./Staff-Mo.
(in millions) 1 10
0.01 0.1 1
2003
2005
1983
1985
1987
1993
2001
1989
1991
1995
1997
1999
2007
2009
productivity
0.01 0.1
0.001 0.01
• Exponential increase over the past few decades

6
Design productivity gap
• 1981 leading edge chip required 100 designer months

– 10,000 transistors / 100 transistors/month
• 2002 leading edge chip requires 30,000 designer months
– 150,000,000 / 5000 transistors/month
• Designer cost increase from $1M to $300M
10,000 100,000
1,000 10,000
Logic transistors 100 1000
10 Gap 100 Productivity
per chip IC capacity
(in millions) 1 10 (K) Trans./Staff-Mo.
0.1 1
productivity
0.01 0.1
0.001 0.01
Embedded Systems Design: A Unified 37

The mythical man-month
• The situation is even worse than the productivity gap indicates

• In theory, adding designers to team reduces project completion time
• In reality, productivity per designer decreases due to complexities of team management
and communication
• In the software community, known as “the mythical man-month” (Brooks 1975)
• At some point, can actually lengthen project completion time! (“Too many cooks”)
Team
60000 15
• 1M transistors, 1 16 16
50000 19 18
designer=5000 trans/month
40000 24 23
• Each additional designer
reduces for 100 trans/month 30000
Months until completion
20000 43
• So 2 designers produce 4900 Individual
10000
trans/month each
0 10 20 30 40
Number of designers

Summary
• Embedded systems are everywhere

• Key challenge: optimization of design metrics
– Design metrics compete with one another
• A unified view of hardware and software is necessary to
improve productivity
• Three key technologies
– Processor: general-purpose, application-specific, single-purpose
– IC: Full-custom, semi-custom, PLD
– Design: Compilation/synthesis, libraries/IP, test/verification


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Embedded Systems Design: A Unified

Embedded systems overview

– Hard to define. Nearly any computing and even here...

1 Embedded Systems Design: A Unified 4

Outline A “short list” of embedded systems

• Technologies Cruise control

– Processor technologies Disk drives

– IC technologies Electronic toys/games

And the list goes on and on

Some common characteristics of embedded

Embedded Systems Design: A Unified 3 Embedded Systems Design: A Unified 6

• Single-functioned -- always a digital camera

Design metric competition -- improving one

DMA controller Display ctrl Hardware

Memory controller ISA bus interface UART LCD ctrl

Embedded Systems Design: A Unified 8 Embedded Systems Design: A Unified 11

Design challenge – optimizing design metrics Time-to-market: a demanding design metric

• Common metrics • Time required to develop a

monetary cost of designing the system – Period during which the

Embedded Systems Design: A Unified 9 Embedded Systems Design: A Unified 12

• Compare technologies by costs -- best depends on quantity

delayed entry – Time of market entry defines a – Technology C: NRE=$100,000, unit=$2

• Loss $80,000 $80

D W 2W – The difference between the on- $40,000 $40

On-time Delayed Time time and delayed triangle areas $0 $0

• But, must also consider time-to-market

• Widely-used measure of system, widely-abused

Embedded Systems Design: A Unified 14 Embedded Systems Design: A Unified 17

Embedded Systems Design: A Unified 15 Embedded Systems Design: A Unified 18

Control Control logic Registers

total = 0 total = 0 – Small size

Embedded Systems Design: A Unified 19 Embedded Systems Design: A Unified 22

Processor technology Application-specific processors

total = 0 particular class of applications having Control Registers

General-purpose processors IC technology

general ALU – IC’s consist of numerous layers (perhaps 10 or more)

• “Pentium” the most well-known, but total = 0

Embedded Systems Design: A Unified 21 Embedded Systems Design: A Unified 24

• Three types of IC technologies • All layers already exist

Full-custom/VLSI Moore’s law

• Benefits Logic transistors 100

Embedded Systems Design: A Unified 26 Embedded Systems Design: A Unified 29

Semi-custom Moore’s law

• Lower layers are fully or partially built • Wow

Embedded Systems Design: A Unified 27 Embedded Systems Design: A Unified 30

• In the past: Sequential program code (e.g., C, VHDL)

• Something that doubles frequently grows more quickly • Hardware/software

than most people realize! “codesign” Microprocessor plus

Embedded Systems Design: A Unified 31 Embedded Systems Design: A Unified 34

Independence of processor and IC

To final implementation PLD Semi-custom Full-custom

Embedded Systems Design: A Unified 32 Embedded Systems Design: A Unified 35

Design productivity exponential increase Design productivity gap

• Exponential increase over the past few decades

Embedded Systems Design: A Unified 33 Embedded Systems Design: A Unified 36

• 1981 leading edge chip required 100 designer months

Embedded Systems Design: A Unified 37

The mythical man-month

• The situation is even worse than the productivity gap indicates

Embedded Systems Design: A Unified 38

• Embedded systems are everywhere

Embedded Systems Design: A Unified 39

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