Sunteți pe pagina 1din 43

5 4 3 2 1

Chocolate_AMD Carrizo(L) DIS/UMA (14.0"/15.6"/17.3")


D DDR3L SODIMM1 PCB 6L/10L STACK UP D
DDR3 800 ~ 1600 MT/s VRAM DDR3L x 8 (900 MHz)
Maxima 8GBs AMD Meso-XT 64 bit
RVS 256 x 16 x 4
PAGE 11 Gen3 x 8 Lane
256 x 16 x 8 LAYER 1 : TOP
Gen2 x4 Lane LAYER 1 : TOP
Power : 25 (Wat t) LAYER 2 : SGND
DDR3L SO-DIMM2 Max 4GBs PAGE 18.19 LAYER 2 : SGND
DDR3 800 ~ 1600 MT/s Package : S3 LAYER 3 : IN1
Maxima 8GBs LAYER 3 : IN1
Size : 23 x 23 (mm) LAYER 4 : IN2
STD PAGE 12 AMD APU 27MHz LAYER 4 : IN2
PAGE 14 LAYER 5 : VCC
LAYER 5 : SVCC
PAGE 10-14 LAYER 6 : GND
PCIE Gen 1 x 1 Lane LAYER 6 : BOT
Processor : Carrizo LAYER 7 : IN3
DP Port1
HDMI Conn LAYER 8 : IN4
Power : 15 (Wat t)
RTL8166EH-CG PAGE 22 Power Source LAYER 9 : GND
Realtek RTS5239 M2230 Package : FP4 BGA
25MHz

RTL8111HSH-CG LAYER 10 : BOT


Card Reader WLAN / BT Combo RTD2136R BQ24728H
DP Port0 LCD Conn
DP to LVDS System Charge Power (+BATCHG)
Translator PAGE 20 PAGE 21
Power : LAN CHIP
Package : LQPF24 PAGE 29
C eDP RT7238B / RT7238C C
Size : 4 x 4 (mm) on DB
PAGE 21 System Power (+3VPCU/+5VPCU/
on DB +3VS5/+5VS5)
NS892407
RJ45 Conn
TRANSFORMER RT8231BGQW
USB3.0 Interface USB3 x1 on DB 2
PAGE 25 on DB System Memory Power (+1.35VSUS/
USB3 PORT2,3 USB3 x1 on MB 3 +0.65V_DDR_VTT)
SATA - HDD
SATA0 6GB/s ISL62771
PAGE 27 Processor Power
USB2.0 Interface (+VCC_CORE/+VDDNB_CORE)
SATA0 6GB/s
SATA - ODD E
PAGE 02-07 AOZ1267QI-02 / APW8824
PAGE 27 Processor Power
(+0.95V/++0.95VS5/+1.5VS5)
System BIOS 48MHz Camera External USB BT Touch screen USB2.0 x 2
SPI ROM SPI Interface 4 7 5 1 0,6 RT8899AGQW
Azalia

PAGE 06 PAGE 21 PAGE 28 PAGE 29 PAGE 29 on DB DGPU Power


B B
(+VGA_CORE/+1.35V_VGA)

LPC Interface RT8068 / APL3523A


TPM SLB9665 DGPU Power
PAGE 29 (+0.95V_VGA/+3V_VGA/+1.8V_VGA)
ENE KB9028Q C ALC3227 HPA022642RTJR
Embedded Controller Audio Codec Headphone amplif i er
Hp
TOP PAGE 24 Combo Jack
Keyboard MIC
PAGE 28 Power : Power : PAGE 24
Package : LQFP 128P Package : MQFN
Touch Pad
PAGE 27 Size : 14 x 14 (mm) Size : 6 x 6 (mm)
G-sensor N PAGE 30 PAGE 23
PAGE 29
FAN
PAGE 27 Speaker Digital MIC
A PAGE 23 PAGE 21 A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
1A
Block Diagram
NB5 RD
Date: Friday, October 17, 2014 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1

QBCON TOPBSQ
Carrizo AJ1802CUT01 AJ1802CUT02
U2B
PCIE

D
Carrizo DB phase use AJ1802CUT00 23 PCIE_RXP2_CARD
U10
U9
P_GPP_RXP[0] P_GPP_TXP[0] R1
R2
PCIE_TXP2_C
PCIE_TXN2_C
C6
C7
0.1U/10V_4
0.1U/10V_4
PCIE_TXP2_CARD 23 D
P_GPP_RXN[0] P_GPP_TXN[0] PCIE_TXN2_CARD 23
23 PCIE_RXN2_CARD
T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_TXP1_LAN_C C4 0.1U/10V_4
23 PCIE_RXP1_LAN PCIE_TXN1_LAN_C PCIE_TXP1_LAN 23
T5 P_GPP_RXN[1] P_GPP_TXN[1] R3 C5 0.1U/10V_4 PCIE_TXN1_LAN 23
23 PCIE_RXN1_LAN
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1 PCIE_TXP0_WLAN_C C2 0.1U/10V_4
29 PCIE_RXP0_WLAN PCIE_TXN0_WLAN_C C3 PCIE_TXP0_WLAN 29
T8 N2 0.1U/10V_4
29 PCIE_RXN0_WLAN P_GPP_RXN[2] P_GPP_TXN[2] PCIE_TXN0_WLAN 29
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3

P_ZVDDP_P_TX_ZVDD_095 U7 P_ZVSS_P_RX_ZVDD_095
P_ZVDDP P_ZVSS/P_RX_ZVDDP U6
CZ support GFX 0~7 & Gen3
CZ-L only support GFX 0~3 & Gen2
P10 M2 GFX_TX0P_C C10 0.22U/10V_4 Platform Type P/N
13 PEG_RXP0 P_GFX_RXP[0] P_GFX_TXP[0]
GFX_TX0N_C PEG_TXP0 13
P9 M1
13 PEG_RXN0 P_GFX_RXN[0] P_GFX_TXN[0] C11 0.22U/10V_4 PEG_TXN0 13 Carrizo Gen 3 CH4222K9B04
N6 L1 GFX_TX1P_C
13 PEG_RXP1 N5
P_GFX_RXP[1]
P_GFX_RXN[1]
P_GFX_TXP[1]
P_GFX_TXN[1] L2 GFX_TX1N_C
C12
C13
0.22U/10V_4
0.22U/10V_4
PEG_TXP1 13 Carrizo-L Gen 1/Gen 2 CH4102K1B03
13 PEG_RXN1 PEG_TXN1 13
N9 P_GFX_RXP[2] P_GFX_TXP[2] L4 GFX_TX2P_C C14 0.22U/10V_4
13 PEG_RXP2 GFX_TX2N_C PEG_TXP2 13
N8 L3 C15 0.22U/10V_4
13 PEG_RXN2 P_GFX_RXN[2] P_GFX_TXN[2] PEG_TXN2 13
C GFX_TX3P_C C
L7 P_GFX_RXP[3] P_GFX_TXP[3] J1 C16 0.22U/10V_4
13 PEG_RXP3 GFX_TX3N_C PEG_TXP3 13
L6 P_GFX_RXN[3] P_GFX_TXN[3] J2 C17 0.22U/10V_4 PEG_TXN3 13
13 PEG_RXN3
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4 GFX_TX4P_C C18 0.22U/10V_4
13 PEG_RXP4 GFX_TX4N_C PEG_TXP4 13
L9 P_GFX_RXN[4] P_GFX_TXN[4] J3 C19 0.22U/10V_4 PEG_TXN4 13
13 PEG_RXN4
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2 GFX_TX5P_C C20 0.22U/10V_4
13 PEG_RXP5 GFX_TX5N_C PEG_TXP5 13
K5 H1 C21 0.22U/10V_4
13 PEG_RXN5 P_GFX_RXN[5] P_GFX_TXN[5] PEG_TXN5 13
K9 P_GFX_RXP[6] P_GFX_TXP[6] G1 GFX_TX6P_C C22 0.22U/10V_4
13 PEG_RXP6 GFX_TX6N_C PEG_TXP6 13
K8 P_GFX_RXN[6] P_GFX_TXN[6] G2 C23 0.22U/10V_4
13 PEG_RXN6 PEG_TXN6 13
J7 P_GFX_RXP[7] P_GFX_TXP[7] G4 GFX_TX7P_C C24 0.22U/10V_4
13 PEG_RXP7 GFX_TX7N_C PEG_TXP7 13
J6 G3 C25 0.22U/10V_4
13 PEG_RXN7 P_GFX_RXN[7] P_GFX_TXN[7] PEG_TXN7 13
For DIS GPU
FP4 REV 1.0

FP4

B B

+0.95V +0.95V

+0.95V

R554 R3 R4
*1K/F_4 196/F_4 *1.69K/F_4
C26
0.1U/10V_4 P_ZVSS_P_RX_ZVDD_095 P_ZVDDP_P_TX_ZVDD_095

R5
196/F_4 CZ: R5 & R3
CZ-L: R4 & R554

A A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 Carrizo 1/7 (PCIE)
Date: Friday, October 17, 2014 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1

U2A U2I
D M_A_DQ[0..63] 11 M_B_DQ[0..63] 12 D

MEMORY A MEMORY B
11 M_A_A[15:0] M_A_A0 M_A_DQ0 12 M_B_A[15:0] M_B_A0 M_B_DQ0
AE28 MA_ADD[0] MA_DATA[0] H17 AG31 MB_ADD[0] MB_DATA[0] A25
M_A_A1 Y27 J17 M_A_DQ1 M_B_A1 AC30 C25 M_B_DQ1
MA_ADD[1] MA_DATA[1] MB_ADD[1] MB_DATA[1]
M_A_A2 Y29 MA_ADD[2] MA_DATA[2] F20 M_A_DQ2 M_B_A2 AC31 MB_ADD[2] MB_DATA[2] C27 M_B_DQ2
M_A_A3 Y26 H20 M_A_DQ3 M_B_A3 AB32 D27 M_B_DQ3
MA_ADD[3] MA_DATA[3] MB_ADD[3] MB_DATA[3]
M_A_A4 W28 E17 M_A_DQ4 M_B_A4 AA32 B24 M_B_DQ4
MA_ADD[4] MA_DATA[4] MB_ADD[4] MB_DATA[4]
M_A_A5 W29 MA_ADD[5] MA_DATA[5] F17 M_A_DQ5 M_B_A5 AA33 MB_ADD[5] MB_DATA[5] B25 M_B_DQ5
M_A_A6 W26 K18 M_A_DQ6 M_B_A6 AA31 B27 M_B_DQ6
MA_ADD[6] MA_DATA[6] MB_ADD[6] MB_DATA[6]
M_A_A7 U29 MA_ADD[7] MA_DATA[7] E20 M_A_DQ7 M_B_A7 Y33 MB_ADD[7] MB_DATA[7] A27 M_B_DQ7
M_A_A8 W25 M_B_A8 AA30
MA_ADD[8] MB_ADD[8]
M_A_A9 U26 A21 M_A_DQ8 M_B_A9 W32 A29 M_B_DQ8
MA_ADD[9] MA_DATA[8] MB_ADD[9] MB_DATA[8]
M_A_A10 AG29 MA_ADD[10] MA_DATA[9] C21 M_A_DQ9 M_B_A10 AG32 MB_ADD[10] MB_DATA[9] C29 M_B_DQ9
M_A_A11 U27 C23 M_A_DQ10 M_B_A11 Y32 B32 M_B_DQ10
MA_ADD[11] MA_DATA[10] MB_ADD[11] MB_DATA[10]
M_A_A12 T28 MA_ADD[12] MA_DATA[11] D23 M_A_DQ11 M_B_A12 W33 MB_ADD[12] MB_DATA[11] D32 M_B_DQ11
M_A_A13 AK26 B20 M_A_DQ12 M_B_A13 AL31 B28 M_B_DQ12
MA_ADD[13] MA_DATA[12] MB_ADD[13] MB_DATA[12]
M_A_A14 T26 B21 M_A_DQ13 M_B_A14 W30 B29 M_B_DQ13
MA_ADD[14]/MA_BG[1] MA_DATA[13] MB_ADD[14]/MB_BG[1] MB_DATA[13]
M_A_A15 T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 M_A_DQ14 M_B_A15 V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31 M_B_DQ14
A23 M_A_DQ15 C31 M_B_DQ15
MA_DATA[15] MB_DATA[15]

11 M_A_BS#[2..0] M_A_DQ16 12 M_B_BS#[2..0] M_B_DQ16


MA_DATA[16] G22 MB_DATA[16] E30
M_A_BS#0 AG26 H22 M_A_DQ17 M_B_BS#0 AH32 E31 M_B_DQ17
MA_BANK[0] MA_DATA[17] MB_BANK[0] MB_DATA[17]
M_A_BS#1 AG27 MA_BANK[1] MA_DATA[18] E25 M_A_DQ18 M_B_BS#1 AG33 MB_BANK[1] MB_DATA[18] G33 M_B_DQ18
M_A_BS#2 T29 G25 M_A_DQ19 M_B_BS#2 W31 G32 M_B_DQ19
MA_BANK[2]/MA_BG[0] MA_DATA[19] MB_BANK[2]/MB_BG[0] MB_DATA[19]
MA_DATA[20] J20 M_A_DQ20 MB_DATA[20] C33 M_B_DQ20
11 M_A_DM[7..0] M_A_DM0 M_A_DQ21 12 M_B_DM[7..0] M_B_DM0 M_B_DQ21
E19 MA_DM[0] MA_DATA[21] E22 D25 MB_DM[0] MB_DATA[21] D33
M_A_DM1 D21 H23 M_A_DQ22 M_B_DM1 D29 G30 M_B_DQ22
MA_DM[1] MA_DATA[22] MB_DM[1] MB_DATA[22]
M_A_DM2 K21 MA_DM[2] MA_DATA[23] J23 M_A_DQ23 M_B_DM2 E33 MB_DM[2] MB_DATA[23] G31 M_B_DQ23
M_A_DM3 F29 M_B_DM3 J33
MA_DM[3] MB_DM[3]
M_A_DM4 AP28 MA_DM[4] MA_DATA[24] F26 M_A_DQ24 M_B_DM4 AR30 MB_DM[4] MB_DATA[24] J30 M_B_DQ24
M_A_DM5 AV26 E27 M_A_DQ25 M_B_DM5 AW30 J31 M_B_DQ25
MA_DM[5] MA_DATA[25] MB_DM[5] MB_DATA[25]
M_A_DM6 AR22 J26 M_A_DQ26 M_B_DM6 BC30 L33 M_B_DQ26
MA_DM[6] MA_DATA[26] MB_DM[6] MB_DATA[26]
M_A_DM7 BC22 MA_DM[7] MA_DATA[27] J27 M_A_DQ27 M_B_DM7 BC26 MB_DM[7] MB_DATA[27] L32 M_B_DQ27
M_A_DM8 K29 H25 M_A_DQ28 M_B_DM8 N33 H32 M_B_DQ28
MA_DM[8] MA_DATA[28] MB_DM[8] MB_DATA[28]
TP2 M_A_DQ29 TP1 M_B_DQ29
MA_DATA[29] E26 MB_DATA[29] H33
H19 G28 M_A_DQ30 B26 L30 M_B_DQ30
MA_DQS_H[0] MA_DATA[30] MB_DQS_H[0] MB_DATA[30]
11 M_A_DQSP0 G19 G29 M_A_DQ31 12 M_B_DQSP0 A26 L31 M_B_DQ31
MA_DQS_L[0] MA_DATA[31] MB_DQS_L[0] MB_DATA[31]
11 M_A_DQSN0 12 M_B_DQSN0
C B22 MA_DQS_H[1] B30 MB_DQS_H[1] C
11 M_A_DQSP1 A22 AN26 M_A_DQ32 12 M_B_DQSP1 A30 AN31 M_B_DQ32
MA_DQS_L[1] MA_DATA[32] MB_DQS_L[1] MB_DATA[32]
11 M_A_DQSN1 M_A_DQ33 12 M_B_DQSN1 M_B_DQ33
F23 MA_DQS_H[2] MA_DATA[33] AP29 F32 MB_DQS_H[2] MB_DATA[33] AP32
11 M_A_DQSP2 M_A_DQ34 12 M_B_DQSP2 M_B_DQ34
E23 MA_DQS_L[2] MA_DATA[34] AR26 E32 MB_DQS_L[2] MB_DATA[34] AT32
11 M_A_DQSN2 G27 AP24 M_A_DQ35 12 M_B_DQSN2 K32 AU32 M_B_DQ35
MA_DQS_H[3] MA_DATA[35] MB_DQS_H[3] MB_DATA[35]
11 M_A_DQSP3 M_A_DQ36 12 M_B_DQSP3 M_B_DQ36
F27 MA_DQS_L[3] MA_DATA[36] AN29 J32 MB_DQS_L[3] MB_DATA[36] AN33
11 M_A_DQSN3 AP25 AN27 M_A_DQ37 12 M_B_DQSN3 AR32 AN32 M_B_DQ37
MA_DQS_H[4] MA_DATA[37] MB_DQS_H[4] MB_DATA[37]
11 M_A_DQSP4 M_A_DQ38 12 M_B_DQSP4 M_B_DQ38
AP26 MA_DQS_L[4] MA_DATA[38] AR29 AR33 MB_DQS_L[4] MB_DATA[38] AR31
11 M_A_DQSN4 M_A_DQ39 12 M_B_DQSN4 M_B_DQ39
AW27 MA_DQS_H[5] MA_DATA[39] AR27 AW32 MB_DQS_H[5] MB_DATA[39] AT33
11 M_A_DQSP5 AV27 12 M_B_DQSP5 AW33
MA_DQS_L[5] MB_DQS_L[5]
11 M_A_DQSN5 M_A_DQ40 12 M_B_DQSN5 M_B_DQ40
AV22 MA_DQS_H[6] MA_DATA[40] AU26 BA29 MB_DQS_H[6] MB_DATA[40] AU30
11 M_A_DQSP6 AU22 AV29 M_A_DQ41 12 M_B_DQSP6 AY29 AV32 M_B_DQ41
MA_DQS_L[6] MA_DATA[41] MB_DQS_L[6] MB_DATA[41]
11 M_A_DQSN6 M_A_DQ42 12 M_B_DQSN6 M_B_DQ42
BA21 MA_DQS_H[7] MA_DATA[42] AU25 BA25 MB_DQS_H[7] MB_DATA[42] BA33
11 M_A_DQSP7 M_A_DQ43 12 M_B_DQSP7 M_B_DQ43
AY21 MA_DQS_L[7] MA_DATA[43] AW25 AY25 MB_DQS_L[7] MB_DATA[43] AY32
11 M_A_DQSN7 L27 AU29 M_A_DQ44 12 M_B_DQSN7 P32 AU33 M_B_DQ44
MA_DQS_H[8] MA_DATA[44] MB_DQS_H[8] MB_DATA[44]
L26 MA_DQS_L[8] MA_DATA[45] AU28 M_A_DQ45 N32 MB_DQS_L[8] MB_DATA[45] AU31 M_B_DQ45
AW26 M_A_DQ46 AW31 M_B_DQ46
MA_DATA[46] MB_DATA[46]
AE25 MA_CLK_H[0] MA_DATA[47] AT25 M_A_DQ47 AE33 MB_CLK_H[0] MB_DATA[47] AY33 M_B_DQ47
11 M_A_CLKP0 AE26 12 M_B_CLKP0 AE32
MA_CLK_L[0] MB_CLK_L[0]
11 M_A_CLKN0 AD26 AV23 M_A_DQ48 12 M_B_CLKN0 AE30 BC31 M_B_DQ48
MA_CLK_H[1] MA_DATA[48] MB_CLK_H[1] MB_DATA[48]
11 M_A_CLKP1 AD27 AW23 M_A_DQ49 12 M_B_CLKP1 AE31 BB30 M_B_DQ49
MA_CLK_L[1] MA_DATA[49] MB_CLK_L[1] MB_DATA[49]
11 M_A_CLKN1 AB28 AV20 M_A_DQ50 12 M_B_CLKN1 AD32 BB28 M_B_DQ50
MA_CLK_H[2] MA_DATA[50] MB_CLK_H[2] MB_DATA[50]
AB29 MA_CLK_L[2] MA_DATA[51] AW20 M_A_DQ51 AD33 MB_CLK_L[2] MB_DATA[51] AY27 M_B_DQ51
AB25 AR23 M_A_DQ52 AC33 BB32 M_B_DQ52
MA_CLK_H[3] MA_DATA[52] MB_CLK_H[3] MB_DATA[52]
AB26 AT23 M_A_DQ53 AC32 BA31 M_B_DQ53
MA_CLK_L[3] MA_DATA[53] MB_CLK_L[3] MB_DATA[53]
MA_DATA[54] AR20 M_A_DQ54 MB_DATA[54] BC29 M_B_DQ54
N29 AT20 M_A_DQ55 T33 BB29 M_B_DQ55
MA_RESET_L MA_DATA[55] MB_RESET_L MB_DATA[55]
11 M_A_RST# 12 M_B_RST#
AE29 MA_EVENT_L AG30 MB_EVENT_L
11 M_A_EVENT# M_A_DQ56 12 M_B_EVENT# M_B_DQ56
MA_DATA[56] BB23 MB_DATA[56] BB27
P27 MA_CKE0 BB22 M_A_DQ57 U32 MB_CKE0 BB26 M_B_DQ57
MA_DATA[57] MB_DATA[57]
11 M_A_CKE0 M_A_DQ58 12 M_B_CKE0 M_B_DQ58
P29 MA_CKE1 MA_DATA[58] BB20 U33 MB_CKE1 MB_DATA[58] BB24
11 M_A_CKE1 AY19 M_A_DQ59 12 M_B_CKE1 AY23 M_B_DQ59
MA_DATA[59] MB_DATA[59]
MA_DATA[60] BA23 M_A_DQ60 MB_DATA[60] BA27 M_B_DQ60
BC23 M_A_DQ61 BC27 M_B_DQ61
MA_DATA[61] MB_DATA[61]
AK27 BC21 M_A_DQ62 AL30 BC25 M_B_DQ62
MA0_ODT[0] MA_DATA[62] MB0_ODT[0] MB_DATA[62]
11 M_A_ODT0 M_A_DQ63 12 M_B_ODT0 M_B_DQ63
AL26 MA0_ODT[1] MA_DATA[63] BB21 AM32 MB0_ODT[1] MB_DATA[63] BB25
11 M_A_ODT1 AH25 12 M_B_ODT1 AJ32
MA1_ODT[0] MB1_ODT[0]
AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
B B
MA_CHECK[1] K28 MB_CHECK[1] N31
AH26 MA0_CS_L[0] MA_CHECK[2] N26 AJ33 MB0_CS_L[0] MB_CHECK[2] R33
11 M_A_CS#0 12 M_B_CS#0
AL29 MA0_CS_L[1] MA_CHECK[3] N28 AL32 MB0_CS_L[1] MB_CHECK[3] R32
11 M_A_CS#1 AH29 J29 12 M_B_CS#1 AJ30 M32
MA1_CS_L[0] MA_CHECK[4] MB1_CS_L[0] MB_CHECK[4]
AL28 MA1_CS_L[1] MA_CHECK[5] K25 AL33 MB1_CS_L[1] MB_CHECK[5] M33
MA_CHECK[6] L29 MB_CHECK[6] R30
MA_CHECK[7] N25 MB_CHECK[7] R31
AG24 MA_RAS_L/MA_RAS_L_ADD[16] AH33 MB_RAS_L/MB_RAS_L_ADD[16]
11 M_A_RAS# AK29 12 M_B_RAS# AK32
MA_CAS_L/MA_CAS_L_ADD[15] MB_CAS_L/MB_CAS_L_ADD[15]
11 M_A_CAS# 12 M_B_CAS#
AH28 MA_WE_L/MA_WE_L_ADD[14] AJ31 MB_WE_L/MB_WE_L_ADD[14]
11 M_A_WE# +1.35VSUS 12 M_B_WE# +1.35VSUS

B19 MA_VREFDQ MA_ZVDDIO_MEM_S AD29 M_A_ZVDDIO R6 39.2/F_4 A19 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 M_B_ZVDDIO R7 39.2/F_4
11 M_A_VREFDQ T32 12 M_B_VREFDQ
M_VREF M_VREF

FP4 REV 1.0 FP4 REV 1.0

FP4 FP4

+1.35VSUS M_VREF CR-L only channel B

R8

1K/F_4

R9 0_4
2

R10 C27 C28


C29
1K/F_4 1000P/50V_4 0.1U/10V_4 0.47U/10V_4
1

A A

Place within 1000mil of the APU

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
1A
Carrizo 2/7 (MEM)
NB5 Date: Friday, October 17, 2014 Sheet 3 of 43
5 4 3 2 1
5 4 3 2 1

+1.8V

R11 301/F_4 APU_RST#

R12 301/F_4 APU_PWRGD

+3V CZ18V_CZL30V
U2C
CZ18V_CZL30V R29 *0_4
DISPLAY/SVI2/JTAG/TEST
+1.8V
R555 1K/F_4 APU_PROCHOT#_R CZ: 1.8V interface (level-shifter)
D
R33 0_4 B6 DP2_TXP[0] DP_ZVSS A9 DP_ZVSS R18 2K/F_4 CZ-L: 3.3V interface D
R14 1K/F_4 APU_ALERT# A6 B9 DP_AUX_ZVSS R13 150/F_4
DP2_TXN[0] DP_AUX_ZVSS
DP_BLON G5 APU_LVDS_BLON_R
APU_SIC APU_DISP_ON_R
R15 1K/F_4 CZ: R33 D7
C7
DP2_TXP[1]
DP2_TXN[1]
DP_DIGON
DP_VARY_BL
G6
F11 APU_DPST_PWM_R CZ: Q3, R57, R565, R57
R16 1K/F_4 APU_SID CZ-L: R29 CZ-L: R564, R568,
A7 DP2_TXP[2]
B7 DP2_TXN[2] DP2_AUXP H9
DP2_AUXN G9
9/10: EMI request place near CONN D9 DP2_TXP[3] DP2_HPD E9 +3V
C9 DP2_TXN[3] +1.8V
+3V +1.8V F7
DPB_LANE0_P
DP1_AUXP INT_HDMI_AUXP 22
22 IN_D2 C30 0.1U/10V_4 A2 DP1_TXP[0] DP1_AUXN E7 INT_HDMI_AUXN 22
C31 0.1U/10V_4 DPB_LANE0_N A3 F5
22 IN_D2# DP1_TXN[0] DP1_HPD
HDMI_HPD_Q 22
C32 0.1U/10V_4 DPB_LANE1_P B4 F8 INT_eDP_AUXP R57 R565
22 IN_D1 DPB_LANE1_N
DP1_TXP[1] DP0_AUXP
INT_eDP_AUXN INT_eDP_AUXP 20
A4 E8

5
R53 R54 22 IN_D1# C33 0.1U/10V_4 DP1_TXN[1] DP0_AUXN INT_eDP_AUXN 20 2.2K_4 2.2K_4
2.2K_4 2.2K_4 5 DP0_HPD G8
DPB_LANE2_P D5 EDP_HPD 20,21 APU_LVDS_BLON_R APU_LVDS_BLON
22 IN_D0 C34 0.1U/10V_4 DP1_TXP[2] 4 3
3 4 APU_SIC DPB_LANE2_N APU_LVDS_BLON 21
12,20,30 MBCLK2 MBCLK2 HDMI 22 IN_D0# C35 0.1U/10V_4 C5 DP1_TXN[2] RSVD_1 K24 CORETYPE TP3
TEMPIN0 E15 APU_TEMPIN0 TP4
C36 0.1U/10V_4 DPB_LANE3_P A5 E14 APU_TEMPIN1 TP5
22 IN_CLK DP1_TXP[3] TEMPIN1
C38 0.1U/10V_4 DPB_LANE3_N B5 DP1_TXN[3] TEMPIN2 E12 APU_TEMPIN2 TP6
22 IN_CLK#
TEMPINRETURN F14 APU_TEMPRETURN R24 0_4 APU_DISP_ON_R 1 6 APU_DISP_ON
MBDATA2 6 1 APU_SID E2 AK24 APU_TEST410 APU_DISP_ON 21
12,20,30 MBDATA2 20 INT_eDP_TXP0 DP0_TXP[0] TEST410
E1 DP0_TXN[0] TEST411 AL24 APU_TEST411 TP7 Q3
20 INT_eDP_TXN0
Q1 TEST4 P24 APU_THERMDA TP8 DMN5L06DWK/50V_0.302A
DMN5L06DWK/50V_0.302A E3 N24 APU_THERMDC TP9

2
DP0_TXP[1] TEST5
20 INT_eDP_TXP1
CZ: Q1, R53, R54 E4 AN24 APU_TEST6 TP10
2

DP0_TXN[1] TEST6
20 INT_eDP_TXN1
eDP TEST9 AB8 APU_TEST9 TP11
CZ-L: R37, R40 D1 DP0_TXP[2] TEST10 Y9 APU_TEST10 TP12 +1.8V
+1.8V D2 DP0_TXN[2] TEST14 B10 APU_TEST14 TP13 R25 *1K/F_4
TEST15 D11 APU_TEST15
APU_LVDS_BLON_R APU_LVDS_BLON
C1 DP0_TXP[3] TEST16 A10 APU_TEST16 TP14 R27 *1K/F_4 R564 *0_4
+3V +1.8V B1 DP0_TXN[3] TEST17 C11 APU_TEST17 R28 *1K/F_4 APU_DISP_ON_R R568 *0_4 APU_DISP_ON
TEST11 B11 APU_TEST11 R30 *1K/F_4
CZ: Q2, R17, R7109 SVT C15 SVT0 TEST18 A14 APU_TEST18 R31 1K/F_4
C SVC D17 SVC0 TEST19 B14 APU_TEST19 R32 1K/F_4 C
CZ-L: R578, R572 SVD D19 SVD0
R17 R7109
GFX_SVT_R B15 A13 APU_TEST28_H
5

2.2K_4 2.2K_4 SVT1 TEST28_H TP15


GFX_SVC_R B16 TEST28_L B13 APU_TEST28_L TP16 R558 *1K/F_4
SVC1 +1.8V
APU_PROCHOT# APU_PROCHOT#_R GFX_SVD_R APU_TEST31
5 APU_PROCHOT#
3 4 Thermal Sensor A18 SVD1 TEST31

DP_STEREOSYNC/TEST36
P26
E11 DP_STEREOSYNC
R559
R36
*1K/F_4
1K/F_4
APU_SIC APU_TEST37 CZ18V_CZL30V
MBCLK2 R37 *0_4 B18 SIC TEST37 A17 R39 *1K/F_4
MBDATA2 R40 *0_4 APU_SID C17 R41 *1K/F_4
SID +1.8V
R42 *1K/F_4
APU_DPST_PWM APU_DPST_PWM_R TP17 APU_RST# D15
6 1 RESET_L
20 APU_DPST_PWM APU_PWRGD
36,38 CPU_PWRGD_SVID_REG
R26 0_4 C19 PWROK DP_STEREOSYNC: HDMI enable pin.
Q2
APU_PROCHOT#_R A15 DIFFERENTIAL ROUTING
DMN5L06DWK/50V_0.302A PROCHOT_L
APU_ALERT# B17
2

ALERT_L
APU_PROCHOT# R578 *0_4 APU_PROCHOT#_R H11 VDDCR_GFX_SENSE R43 0_4
VDDCR_GFX_SENSE APU_VDDGFX_RUN_FB_H 38
APU_DPST_PWM R572 *0_4 APU_DPST_PWM_R APU_RST# APU_TDI H15 J12 VDDCR_NB_SENSE R45 0_4
TDI VDDCR_NB_SENSE CPU_VDDNB_RUN_FB_H 36
APU_PWRGD APU_TDO H14 G12 VDDCR_CPU_SENSE R46 0_4
+1.8V TDO VDDCR_CPU_SENSE CPU_VDD0_RUN_FB_H 36
APU_TCK D13 AY18 VDDP_SENSE TP7003
TCK VDDP_SENSE
APU_TMS G15 TMS
APU_TRST# J14 TRST_L VSS_SENSE H12 VSS_SENSE R562 0_4
APU_DBRDY APU_VDDGFX_RUN_FB_L 38
EC new option C47
*150P/50V_4
C48
*150P/50V_4 APU_DBREQ#
C13
A11
DBRDY R49
R50
0_4
0_4
CPU_VDDNB_RUN_FB_L 36
DBREQ_L
CPU_VDD0_RUN_FB_L 36
R20 0_4
36,38 VRHOT

APU_PROCHOT#
30 H_PROCHOT#
R557 0_4 FP4 REV 1.0

FP4
CZ: R43, R562 Stuff
CZ-L: R43, R562 No Stuff
C37
220P/50V_4 VDDCR_CPU_SENSE TP7004
VDDCR_NB_SENSE TP7005
VDDCR_GFX_SENSE TP7006

+1.8V
B APU Serial VID B

R566 R567 R62


HDT+ Connector for Debug only +3V IO Thermal Protect
Place near APU within 500mil *1K/F_4 *1K/F_4 *1K/F_4

Can remove on MP J1 R569 0_4 SVT


36 CPU_SVT
+1.8V 20 +3VPCU R65 0_4 SVC
APU_TEST18 19 36 CPU_SVC
C51
APU_TEST19 18 R571 0_4 SVD
0.1U/10V_4 17 36 CPU_SVD
APU_RST_L_BUF
U3 INT CPU_LDT_RST_HTPA# 16
TP26 APU_DBREQ# 15
5

TC7SH08FU R560
2 APU_RST# APU_DBRDY 14 16.5K/F_4
CPU_LDT_RST_HTPA# 4 APU_TCK 13 +1.8V
1 APU_TMS 12
For 65 degree, 1.8V limit, (SW)
APU_TDI
APU_TRST#
APU_TDO
11
10
9
GFX Serial VID 9/2: confirm setting with AMD Ronald
3

APU_PWROK_BUF 8 C49
VFIX MODE VID Override table (VDD)
7 0.1U/10V_4
6
1

+3V +1.8V 5
R44 SVC SVD Boot Voltage
3.3K/F_4 R76 R77 R78
4 Place near APU within 500mil
3 For 75 degree, 1.2v limit, (HW) *1K/F_4 1K/F_4 *1K/F_4
0 0 1.1V
2
1 THRM_MONITOR1 30
R80 0_4 GFX_SVT_R 0 1 1.0V
+1.8V 38 GFX_SVT
R68 R69 *HDT CONN
0_4 *0_4 88511-2001-20p-l R81 0_4 GFX_SVC_R 1 0 0.9V
38 GFX_SVC
R52
Close to HDT & No remove. 0_4 38 GFX_SVD R83 0_4 GFX_SVD_R 1 1 0.8V
2

A R71 R72 +1.8V A


1K/F_4 1K/F_4 C50
C52 APU_TDI R573 1K/F_4 0.1U/10V_4
APU_TCK
1

0.1U/10V_4 R574 1K/F_4 R56


APU_TMS R75 1K/F_4 100K_4 NTC
APU_TRST# R79 1K/F_4
U4
APU_RST# 1 6 APU_RST_L_BUF
2 A1 Y1 5
PROJECT : X21
APU_PWRGD 3 GND VCC 4 APU_PWROK_BUF APU_DBREQ# R82 1K/F_4
A2 Y2
9/2: Del by Talant's mail 22:01
74LVC2G07GW Quanta Computer Inc.
Size Document Number Rev
1A
Carrizo 3/7 (DIS/MISC)
NB5 Date: Friday, October 17, 2014 Sheet 4 of 43
5 4 3 2 1
5 4 3 2 1

+3V

BOARD ID TABLE BOARD ID SETTING


R84 10K/F_4 BOARD_ID0 R575 *10K/F_4
BOARD_ID1 Board ID 0 Definition
R86 *10K/F_4 R87 10K/F_4
R88 *10K/F_4 BOARD_ID2 R89 10K/F_4
R90 *10K/F_4 BOARD_ID3 R91 10K/F_4 ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 0 UMA
R93 *10K/F_4 BOARD_ID4 R94 10K/F_4 Model
R7103 10K/F_4 BOARD_ID5 R7104 *10K/F_4
R7105 *10K/F_4 BOARD_ID6 R7106 10K/F_4
R7107 *10K/F_4 BOARD_ID7 R7108 10K/F_4
CZ 14" UMA 0 0 0 0 0 1 0 0 1 SG

+3VS5 +3VS5
CZ 14" SG 1 0 0 0 0 1 0 0
Board ID [2:1] Definition

U5 R92 CZ 15" UMA 0 1 0 0 0 1 0 0


D *MC74VHC1G08DFT2G
00 14" D
*4.7K/F_4

3
1 CZ 15" SG 1 1 0 0 0 1 0 0
PCIE_RST#_R1 4 01 15"
13,23,29 PCIE_RST#_R1 PCIE_RST#_R PCIE_RST#
2 R95 33_4
CZ 17" UMA 0 0 1 0 0 1 0 0
10 17"

5
C53 150P/50V_4
CZ 17" SG 1 0 1 0 0 1 0 0
Board ID [4:3] Definition
R96 0_4
00 Pavilion
+1.8VS5
01 Reserve
U2D
150P/50V_4 C54
LPC_RST#_R
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
BOARD_ID5 10 Reserve
R97 R98 33_4 BB12 LPC_RST_L S0 S0 SD0_WP/EGPIO101 BB2
29,30 KBC_RST# PCIE_RST#
47K/F_4 AN7 PCIE_RST_L/EGPIO26 S5 X S0 X SD0_PWR_CTRL/AGPIO102 BB5
S0 S5 SD0_CD/AGPIO25 BC2
RSMRST#_R BOARD_ID6
30 RSMRST#
1 2 AE4 RSMRST_L S0 S0 SD0_CLK/EGPIO95 BB4
BOARD_ID0 Board ID [5] Definition
S0 S0 SD0_CMD/EGPIO96 AY5
D2 RB501V-40
30 DNBSWON#
DNBSWON#
SYS_PWRGD
AE1 PWR_BTN_L/AGPIO0 S5 X
C55 BC9 PWR_GOOD 0/1 CZ/CZ-L
SYS_RST# AF2
1U/6.3V_4 6 SYS_RST# PCIE_WAKE#
SYS_RESET_L/AGPIO1 S5 S5 BOARD_ID1
AG2 WAKE_L/AGPIO2 S5 X S0 S0 SD0_DATA0/EGPIO97 BC3
+3V 23,29 PCIE_WAKE# BOARD_ID2
to DDR3 SMBUS C56 *100P/50V_4 S0 S0 SD0_DATA1/EGPIO98 BA3
AK7 BOARD_ID3
SMB_RUN_CLK 30 SUSB# SLP_S3_L S0 S0 SD0_DATA2/EGPIO99 BC5
BOARD_ID4 Board ID [7:6] Definition
R99 2.2K_4 AH5 SLP_S5_L S0 S0 SD0_DATA3/EGPIO100 BA5
30 SUSC# BOARD_ID7
S0 S0 SD0_LED/EGPIO93 BB6
SMB_RUN_DAT DGPU_PWROK AE8
R100 2.2K_4
30,41,43 DGPU_PWROK S0A3_GPIO/AGPIO10 S5 S5 SMB_RUN_CLK 00 Reserve
AH8 S5_MUX_CTRL/EGPIO42 S5 X S0 S0 SCL0/I2C2_SCL/EGPIO113 BA15
40 APU_S5_MUX_CTRL SMB_RUN_DAT SMB_RUN_CLK 11,12,20
APU_TEST0
S0 S0 SDA0/I2C2_SDA/EGPIO114 AY17
SMB_RUN_DAT 11,12,20
Only CZ Stuff APU_TEST1
AH6
AK8
TEST0 Power Domain
SCL1/I2C3_SCL/AGPIO19 AG5
SMB_ALW_CLK +3VS5
R196 10K/F_4 CLKREQG# TP27
APU_TEST2
TEST1/TMS
CZ CZ-L S5 S5 SMB_ALW_DAT SMB_ALW_CLK 27
C AE3 TEST2 S5 S5 SDA1/I2C3_SDA/AGPIO20 AG4 SMB_ALW_DAT 27 C
R7044 10K/F_4 PCIE_CLKREQ_CARD#
EC_RCIN#
30 EC_RCIN# EC_A20GATE
AY15 ESPI_RESET_L/KBRST_L/AGPIO129 S0 S0 AGPIO4 R197 *10K/F_4
R576 *1K/F_4 SYS_RST# internal 10K pull up BC19 S0 S0
+3VS5 30 EC_A20GATE SIO_EXT_SCI#
GA20IN/AGPIO126
AD7 LPC_PME_L/AGPIO22 S5 S5 S5 S5 AGPIO3 AL5 AGPIO8 R198 10K/F_4
SYS_RST# 30 SIO_EXT_SCI# SIO_EXT_SMI# AGPIO3 6
G2 1 2 BB13 LPC_SMI_L/AGPIO86 S0 X S5 S5 AGPIO4 AL6 AGPIO4
30 SIO_EXT_SMI#
S5 S5 AGPIO5 AJ1
ODD_DA#_FCH 27
*SOLDERJUMPER-2 AG3 S5 S5
AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 S5 S5 AGPIO6/LDT_RST_L AJ3
27 ODD_PLUGIN#
AD5 S5 S5
IR_TX0/USB_OC5_L/AGPIO13 S5 S5 AGPIO7/LDT_PWROK AH1
R102 0_4 AL8 S5 S5
IR_TX1/USB_OC6_L/AGPIO14 S5 S5 AGPIO8 AJ4 AGPIO8 +3V
30 PCI_SERR#
AN8 IR_RX1/AGPIO15 S5 S5 S5 S5 AGPIO9 AK5
TP30 LLB# AE2 IR_LED_L/LLB_L/AGPIO12 S5 S5 S5 X VDDGFX_PD/AGPIO39 AD8
PCIE_CLKREQ_CARD# VDDGFX_PD 38
23 PCIE_CLKREQ_CARD# PCIE_CLKREQ_LAN#
BC15 S0 S0
CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 S5 X AGPIO40 AG8
PROCHOT#_CTRL APU_VRM_GFX_PWRGD 38 AGPIO69 R201 10K/F_4
BB17 CLK_REQ1_L/AGPIO115 S0 S0 S0 S0 AGPIO64 AW15 R103 0_4
23 PCIE_CLKREQ_LAN# PCIE_CLKREQ_WLAN# BC17 BT_COMBO_OFF APU_PROCHOT# 4 BT_COMBO_OFF
29 PCIE_CLKREQ_WLAN# CLK_REQ2_L/AGPIO116 S0 S0 S0 S0 AGPIO65 AU15
BT_COMBO_OFF 29 R7051 *10K/F_4
BB18 S0 S0
CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
27 ODD_PWR BB16
CLKREQG# CLK_REQG_L/OSCIN/EGPIO132S0 S0 S0 S0 AGPIO66/SHUTDOWN_L AT15 AGPIO66 TP7002 AGPIO66 R7052 *10K/F_4
JTAG_TRST# AH9 USB_OC0_L/TRST_L/AGPIO16 S5 S5
TP35
JTAG_TDI
S0 S0 AGPIO68/SGPIO_CLK AU12
ACC_LED# 27
TP36 AG1 USB_OC1_L/TDI/AGPIO17 S5 S5 S0 S0 AGPIO69/SGPIO_LOAD AT14 AGPIO69
JTAG_TCK AH2
+3VS5
TP37
JTAG_TDO
USB_OC2_L/TCK/AGPIO18 S5 S5 S0 S0 AGPIO71/SGPIO_DATAOUT AR14 VGA_RSTB 13
to TP SMBUS TP39 AL9 S5 S5 S0 S0 AGPIO72/SGPIO_DATAIN BC13
USB_OC3_L/TDO/AGPIO24
VGA_ON_SB 30 Only CZ Stuff if no used
SMB_ALW_CLK ACZ_BCLK_R
R104 2.2K_4 R105 *10K/F_4
ACZ_SDIN0
AU6 AZ_BITCLK/I2S_BCLK_MIC S0 S0 SPKR/AGPIO91 BA17
ACZ_SPKR 23 Only CZ-L Stuff if no used
R106 *10K/F_4 AR8 AZ_SDIN0/I2S_DATA_MIC[0]
SMB_ALW_DAT ACZ_SDIN1 AP6 AN5
R107 2.2K_4 R7091 10K/F_4
ACZ_SDIN2
AZ_SDIN1/I2S_LR_PLAYBACK S5 S0 BLINK/USB_OC7_L/AGPIO11
AGPIO11 6 GENINT1: HVB function
R7092 10K/F_4 AR5 AZ_SDIN2/I2S_DATA_PLAYBACK Vss:enabke
ACZ_RST#_R AU9 BB14
R110 10K/F_4 DNBSWON#
ACZ_SYNC_R
AZ_RST_L/I2S_LR_MIC S0 S0 GENINT1_L/AGPIO89 R111 *0_4
NC: disable
PCIE_WAKE# ACZ_SDOUT_R
AT9 AZ_SYNC/I2S_BCLK_PLAYBACK S0 S0 GENINT2_L/AGPIO90 BA19 R112 0_4
ACCEL_INTH# 29
R113 10K/F_4 AR7 AZ_SDOUT/I2S_DATA_MIC1

DGPU_PWROK
S0 S0 FANIN0/AGPIO84 BC18
RF_OFF 29
R114 *10K/F_4 R7053 10K/F_4 GPIO145 BB10 I2C0_SCL/EGPIO145 S0 X S0 S0 FANOUT0/AGPIO85 BB19 TP40
for GPIO145~148 R7054 10K/F_4 GPIO146 BB9 I2C0_SDA/EGPIO146 S0 S0
PCIE_WAKE# PU & LAN use 0 ohm to open. CZ pop those resistor R7055 10K/F_4 GPIO147 BB7
BC7
I2C1_SCL/EGPIO147 S0
I2C1_SDA/EGPIO148 S0
S0 S0 X UART0_CTS_L/EGPIO135 AY9

CZ-L can NC them


R7056 10K/F_4 GPIO148 S0 S0 X UART0_RXD/EGPIO136 AW8
S0 X UART0_RTS_L/EGPIO137 AV5
6,30 RTC_CLK 32K_X1
AG7 RTCCLK S0 X UART0_TXD/EGPIO138 AV8
C57 18P/50V_4 S0 X UART0_INTR/AGPIO139 AW9
B B
AT1 X32K_X1 S0 X UART1_CTS_L/BT_I2S_BCLK/EGPIO140AV11
1
2

S0 S5 UART1_RXD/BT_I2S_SDI/EGPIO141AU7
R116 S0 X UART1_RTS_L/EGPIO142 AT11
Y1 20M_4 S0 X UART1_TXD/BT_I2S_SDO/EGPIO143AR11
32.768KHZ AT2 X32K_X2 S5 S0 UART1_INTR/BT_I2S_LRCLK/AGPIO144AP9
32K_X2
4
3

C58 18P/50V_4 FP4 REV 1.0 +3VS5


FP4
R117 *2.2K_4 APU_TEST0 R118 15K/F_4

R119 *1K/F_4 APU_TEST1 R120 15K/F_4

To Azalia R121 *2.2K_4 APU_TEST2 R122 15K/F_4

R123 33_4 ACZ_SDOUT_R


23 ACZ_SDOUT_AUDIO
ACZ_SYNC_R
23 ACZ_SYNC_AUDIO
R124 33_4 Follow AMD checklist 53537_1_03 suggestion to stuff R118/R120/R122
C59 *10P/50V_4 For EMI

R125 33_4 ACZ_BCLK_R TEST2 TEST1 TEST0 Description


23 BIT_CLK_AUDIO
ACZ_RST#_R
23 ACZ_RST#_AUDIO
R126 33_4
ACZ_SDIN0
SYS PWRGD 0 0 0
FCH TAP accessible from APU when TAPEN is asserted
FCH JTAG pins are overloaded for multiple
23 ACZ_SDIN0 functions, in this configuration the FCH JTAG are
+1.8V +3V used as non-JTAG pins

R127 R128 0 0 1 Reserved


*10K/F_4 10K/F_4
D1 BAT54AW-L
36 CPU_VRM8380_PG
2 0 1 X Reserved
3 R129 0_4 SYS_PWRGD FCH JTAG multi-function pins are configured as
1 TMS 0 JTAG pins, in this configuration the FCH TAP
1 can be accessed from FCH JTAG pins
30 ECPWROK
A C60 A

Pure UMA can remove


*2.2U/6.3V_6 CZ: R128 1 TMS 1
Use on ATE only
Yuba JTAG enabled
VGA_REQ 1 2 CLKREQG# TP41 CZ-L: R127
3

D12 RB500V-40
R469
2
30,41,43 DGPU_PR_EN
30K/F_4
Q31
METR5213-G
PROJECT : X21
1

C589
0.47U/6.3V_4 Quanta Computer Inc.
Size Document Number Rev
1A
Carrizo 4/7 (GPIO/AZ/UARTH)
NB5 Date: Friday, October 17, 2014 Sheet 5 of 43
5 4 3 2 1
5 4 3 2 1

Only CZ Stuff if no used


+3V U2E
CLK/SATA/USB/SPI/LPC
R202 10K/F_4 EGPIO67 AU3 SATA_TX0P USBCLK/25M_48M_OSC AP8
27 SATA_TXP0
AU4 SATA_TX0N
27 SATA_TXN0 USB_ZVSS
R203 10K/F_4 EGPIO70 HDD AV1 SATA_RX0N
USB_ZVSS AP5 R133 11.8K/F_4
27 SATA_RXN0 AV2 AR2
SATA_RX0P USB_HSD0P
+3V 27 SATA_RXP0
USB_HSD0N AR1
USBP0+
USBP0-
23
23
Left side USB2.0 port
AY2 SATA_TX1P
27 SATA_TXP1 AY1 AR3
R204 10K/F_4 AGPIO76 SATA_TX1N USB_HSD1P
27 SATA_TXN1 USBP1+ 29
R580 10K/F_4 EGPIO119
ODD AW4 SATA_RX1N
USB_HSD1N AR4
USBP1- 29 TOUCH SCREEN
27 SATA_RXN1
AW3 SATA_RX1P USB_HSD2P AN2
D 27 SATA_RXP1 D
USB_HSD2N AN1
C61 SATA_CALRN
R130 1K/F_4 AW1 SATA_ZVSS
*0.1U/10V_4 R134 1K/F_4 SATA_CALRP AW2 AN3
+0.95V SATA_ZVDDP USB_HSD3P
U6 EGPIO67 AT17 DEVSLP[0]/EGPIO67 USB_HSD3N AN4

5
*MC74VHC1G08DFT2G +3V R131 *560_4/F EGPIO70 AT12 DEVSLP[1]/EGPIO70
2 SB_SATA_LED# BB15 AM1
SATA_ACT_L/AGPIO130 USB_HSD4P

27 SATA_LED#
4 USB_HSD4N AM2 USBP4+
USBP4-
21
21
Camera USB
1 TP42 AU2 SATA_X1

Integrated Clock Mode: USB_HSD5P AL2


USBP5+ 29
Leave unconnected.
USB_HSD5N AL1
USBP5- 29 WLAN Min-Card

3
TP43 AU1 SATA_X2 USB_HSD6P AL3
USBP6+ 23
USB_HSD6N AL4
USBP6- 23 Left side USB Combo 3.0/2.0.
R132 0_4 RP2 2 1 CLK_GFX_P_R U4 GFX_CLKP USB_HSD7P AK2
13 CLK_GFX_P CLK_GFX_N_R USBP7+ 28
13 CLK_GFX_N 0_4P2R_4 4 3 U3 GFX_CLKN USB_HSD7N AJ2
USBP7- 28 Right side USB Combo 3.0/2.0.
RP3 2 1 CLK_PCIE_CARDP_R U1 GPP_CLK0P
23 CLK_PCIE_CARDP CLK_PCIE_CARDN_R
23 CLK_PCIE_CARDN 0_4P2R_4 4 3 U2 GPP_CLK0N CZ: Maximum 8 devices (Ex: 8 USB2.0 – OR-- 4 USB2.0 + 4 USB3.0 external, etc…)
RP1 2 1 CLK_PCIE_LANP_R W4
23 CLK_PCIE_LANP GPP_CLK1P
C66 5.6P/50V_4 48M_X1 0_4P2R_4 4 3 CLK_PCIE_LANN_R W3
23 CLK_PCIE_LANN GPP_CLK1N
CZ-L: Maximum 8 devices (Ex: 8 USB2.0 – OR-- 6 USB2.0 + 2 USB3.0 external, etc…)
RP4 2 1 CLK_PCIE_WLAN_R W1
29 CLK_WLAN_P GPP_CLK2P
CLK_PCIE_WLAN#_R
2
1

29 CLK_WLAN_N 0_4P2R_4 4 3 W2 GPP_CLK2N


+0.95VS5
GPP_CLK3P
Y2
48MHZ +-10PPM
R140
1M/F_4
TP59
TP60 GPP_CLK3N
Y2
Y1
GPP_CLK3P
GPP_CLK3N R579 0_4
Support S3~S5 wake up
4
3

BC10 X25M_48M_OSC
+0.95V
C67 48M_X2 AD2 USBSS_CALRN
5.6P/50V_4 USB_SS_ZVSS
USB_SS_ZVDDP AD1 USBSS_CALRP
1K/F_4
1K/F_4
R135
R136 R194 *0_4
No support S3~S5 wake up
TP44 48M_X1 T2 X48M_X1
C62 *10P/50V_4 USB_SS_0TXP AA3
USB_SS_0TXN AA4
C64 *10P/50V_4
TP45 48M_X2 T1 W9
X48M_X2 USB_SS_0RXP
C USB_SS_0RXN W8 C

R138 22_4 LPC_CLK0 AW14 LPCCLK0/EGPIO74 USB_SS_1TXP AA2


30 CLK_33M_KBC LPC_CLK1
R137 *22_4 AY13 AA1
29 CLK_PCI_TPM LPCCLK1/EGPIO75 USB_SS_1TXN
R139 22_4
29 CLK_33M_DEBUG
29,30 LAD0 BB11 LAD0 USB_SS_1RXP W5
C65 *10P/50V_4 BA11 LAD1 USB_SS_1RXN W6
29,30 LAD1
29,30 LAD2 AY11 LAD2
BA13 LAD3 USB_SS_2TXP AC1
29,30 LAD3 USB30_TX2+ 23
LFRAME# AV14 LFRAME_L USB_SS_2TXN AC2
29,30 LFRAME# USB30_TX2- 23
LDRQ#0 BA1 ESPI_ALERT_L/LDRQ0_L
TP46
29,30 SERIRQ
BC14
BC11
SERIRQ/AGPIO87 USB_SS_2RXP Y6
Y7
USB30_RX2+ 23 Left side USB Combo 3.0/2.0.
30 CLKRUN# LPC_PD#
LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN
USB30_RX2- 23
AE9 LPC_PD_L/AGPIO21
10K/F_4 USB_SS_3TXP AC4
R7110 USB30_TX3+ 28
USB_SS_3TXN AC3
SPI_CLK USB30_TX3- 28
TP48 SPI_CS0#
BC6
BB8
SPI_CLK/ESPI_CLK/EGPIO117
SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
Right side USB Combo 3.0/2.0.
TP49 AW7 AB6 USB30_RX3+ 28
EGPIO119 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN
SPI_SI BA9 USB30_RX3- 28
SPI_DI/ESPI_DATA/EGPIO120
TP51 SPI_SO AY7 SPI_DO/EGPIO121
TP52 SPI_WP AW11 SPI_WP_L/EGPIO122
TP53 SPI_HOLD# BA7 SPI_HOLD_L/EGPIO133
TP54
AGPIO76 AW12 SPI_TPM_CS_L/AGPIO76

FP4 REV 1.0

FP4

+3V +3V +3V +3VS5 +3VS5 +3VS5 +3VS5

STRAPS PINS
R141 R142 R577 R144 R145 R146 R147
B OVERLAP COMMON PADS WHERE *10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4 *10K/F_4 10K/F_4
B

POSSIBLE FOR DUAL-OP RESISTORS.


LPC_CLK0

LPC_CLK1

LFRAME#

5 AGPIO3

5,30 RTC_CLK

5 AGPIO11

5 SYS_RST#

CZ: pop R144


CZ-L:pop R153 R150 R151 R152 R153 R154 R155 R156
2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4 *2K/F_4
CZ:1.8V +1.8V_ROM +3VS5
CZ-L:3.3V
R7101 0_4 R7102 *0_4
CZ-L use 3.3V ROM SPI_CLK +1.8V_ROM +3VS5
REQUIRED STRAPS Follow FAE comment: R154 change to 2K, R147 to 10k, R146 is NC
CZ use 1.8V ROM(Default) EC50 AGPIO11
*22P/50V_4 LPC_CLK0 LPC_CLK1 LFRAME# AGPIO3 RTC_CLK BLINK SYS_RST#
APU SPI ROM EMI
R7100
10K/F_4
R148
*10K/F_4
C68 0.1U/10V_4
CZ-L
Int Pull-Up
CZ
Int Pull-Up Int Pull-Up Int Pull-Up

PULL BOOT FAIL TIMER Use 48Mhz crystal clock Coin battery is LDT_RST#/LDT_PWRGD normal reset mode
A Vender Size P/N (3.3V) P/N (1.8V) HIGH ENABLED and generate both internal SPI ROM 1.8V SPI ROM Enhanced reset logic on board. output to APU A
U7 and external clocks (for quicker S5 resume)
WND 8M AKE3EFP0N07 SPI_CS0#
SPI_CLK
R157 33_4 EC_BIOS_CS#
EC_BIOS_SPI_CLK_I
1
CE# VDD
8 R149 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
R158 33_4 6 10K/F_4
GGD 8M AKE3EGN0Q01 SPI_SO
SPI_SI
R159 33_4 EC_BIOS_WR#
EC_BIOS_RD#
5 SCK
SI PULL BOOT FAIL TIMER Use 100Mhz PCIE clock as Coin battery is LDT_RST#/LDT_PWRGD short reset mode
R160 0_4 2 7 LOW DISABLED reference clock and generate LPC ROM 3.3V SPI ROM Default to not on board. output to Pads
EON 8M AKE3EZN0Q01
SPI_WP
SO HOLD#
internal clocks only traditional reset logic
R161 *0_4 EC_SPI_WP_R 3 4 DEFAULT DEFAULT
WP# VSS
Socket DFHS08FS023
+3VS5 R162 *10K/F_4 A25QE32M-F/Q
EC_SPI_WP_R R7072 1K/F_4
CZ-L: R162
DFHS08FS023
91960-0084L-8P-SOCKET
PROJECT : X21
Quanta Computer Inc.
30 EC_SPI_WP_R EC_BIOS_CS# +1.8V_ROM
30 EC_BIOS_CS# EC_BIOS_SPI_CLK_I CZ: R7072
30 EC_BIOS_SPI_CLK_I EC_BIOS_WR#
30 EC_BIOS_WR# EC_BIOS_RD# SPI_HOLD# R163 0_4 Size Document Number Rev
30 EC_BIOS_RD#
1A
Carrizo 5/7 (SATA/USB/SPI)
NB5 Date: Friday, October 17, 2014 Sheet 6 of 43
5 4 3 2 1
5 4 3 2 1

+1.35VSUS U2F +VCC_CORE

3A POWER 22~39A
P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8
P28 VDDIO_MEM_S3_2 VDDCR_CPU_2 W7
T24 VDDIO_MEM_S3_3 VDDCR_CPU_3 W12
T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15
C86 C69 C87 C88 C70 C71 C72 C89 C73 C90 C74 U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18 C75 C76 C91 C77 C78 C92 C79 C93 C80
22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 *22U/6.3VS_6 *22U/6.3VS_6 *22U/6.3VS_6 U28 VDDIO_MEM_S3_6 VDDCR_CPU_6 W21 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6
D D
V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
V33 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y10
W24 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y13
W27 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
Y25 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y19
Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 VDDIO_MEM_S3_15 VDDCR_CPU_15 AB12
C81 C82 C83 C94 C84 C85 C95 AB30 VDDIO_MEM_S3_16 VDDCR_CPU_16 AB15 C96 C97 C98 C99 C100 C101 C102 C103 C104
0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4 AB33 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB18 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4
AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6
AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10
AE24 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD13
AE27 VDDCR_CPU_22 AD16
BOTTOM SIDE DECOUPLING UNDER APU AF30
VDDIO_MEM_S3_22
VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19 BOTTOM SIDE DECOUPLING UNDER APU
AF33 VDDIO_MEM_S3_24 VDDCR_CPU_24 AD22
AG25 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE7
AG28 VDDIO_MEM_S3_26 VDDCR_CPU_26 AE12
AH24 VDDCR_CPU_42 AK9
+0.95V
AH27
VDDIO_MEM_S3_27 BOTTOM SIDE DECOUPLING UNDER APU
C105 C106 C107 C108 C109 C110 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4 180P/50V_4 AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10
AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
AK28 VDDIO_MEM_S3_31 VDDCR_CPU_44 AK13
AK30 VDDIO_MEM_S3_32 VDDCR_CPU_33 AG16
AK33 VDDIO_MEM_S3_33 VDDCR_CPU_45 AK16 C111 C112 C113 C114
DECOUPLING BETWEEN PROCESSOR AND DIMMs AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
AM30 VDDCR_CPU_46 AK19
ACROSS VDDNB AND VSS SPLIT VDDIO_MEM_S3_35
0.2A VDDCR_CPU_35 AG22
AR19 VDDIO_AUDIO VDDCR_CPU_47 AK22
+APU_VDDIO_AZ
1.5A VDDCR_CPU_36 AH7

+VDDP_GFX AE6 VDDP_GFX_2 VDDCR_CPU_28 AE18


AE5 VDDP_GFX_1 VDDCR_CPU_29 AE21
+VDDP_GFX
R582 +0.95V +VDDP_GFX AP19
0.2A
VDD_33_1
VDDCR_CPU_40 AH21
VDDCR_CPU_30 AG6
+APU_VDD_33
CZ: always pop AP21 VDD_33_2 VDDCR_CPU_37 AH12 C115 C116 C117 C118 C119 C120 C121
C
CZ-L PX: Stuff R582 0_6 R7047 AP16
1.5A VDDCR_CPU_49 AN6 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4 C
R7047 +1.8V_ROM VDD_18_1 VDDCR_CPU_38 AH15
UMA: No Stuff *0_4 only pop on AP18 VDD_18_2 VDDCR_CPU_39 AH18
C664 C665 0.5A VDDCR_CPU_48 AL7
10U/6.3VS_6 0.22U/10V_4
CZ-L UMA SKU. AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
+APU_VDD_18_S5 +APU_VDDGFX
AR9 VDD_18_S5_2 VDDCR_CPU_27 AE15
0.2A
+APU_VDD_33_S5 AP15 VDD_33_S5_1 22~30A
AR15 VDD_33_S5_2 VDDCR_GFX_14 L8
0.8A VDDCR_GFX_15 L13
+VDDP_S5 AN12 VDDP_S5_1 VDDCR_GFX_16 L16
AP12 VDDP_S5_2 VDDCR_GFX_17 L19
+VDDCR_FCH_S5 +VDDCR_FCH_S5_R 0.2A VDDCR_GFX_18 L22 C122 C123 C124 C125 C126 C127 C128 C129 C130
AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6
+VDDCR_FCH_S5_R
+VDDCR_FCH_S5 R174 0_4 AR12 VDDCR_FCH_S5_2 VDDCR_GFX_20 N12
7A VDDCR_GFX_21 N15
R174 +0.95V
AW19 VDDP_6 VDDCR_GFX_22 N18
C177 C178 C179 AU17 N21
CZ: Stuff 10U/6.3VS_6 10U/6.3VS_6 0.22U/10V_4 AU19
VDDP_1
VDDP_2
VDDCR_GFX_23
VDDCR_GFX_24 P8
CZ-L: No Stuff +VDDNB_CORE
AV17 VDDP_3 VDDCR_GFX_25 P13
AV19 VDDP_4 VDDCR_GFX_26 P16
AW17 VDDP_5 VDDCR_GFX_27 P19
12A VDDCR_GFX_28 P22
AL12 VDDCR_NB_1 VDDCR_GFX_29 T7 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140
AL13 VDDCR_NB_2 VDDCR_GFX_1 F12 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4
AL15 VDDCR_NB_3 VDDCR_GFX_2 F15
AL18 VDDCR_NB_4 VDDCR_GFX_3 G11
C141 C142 C143 C144 C145 C146 C147 C148 C149 AL21 VDDCR_NB_5 VDDCR_GFX_4 G14
0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 22U/6.3VS_6 AN13 VDDCR_NB_6 VDDCR_GFX_5 J8
AN16 VDDCR_NB_7 VDDCR_GFX_6 J9
AN19 J11
AN22
VDDCR_NB_8 VDDCR_GFX_7
K7
BOTTOM SIDE DECOUPLING UNDER APU
VDDCR_NB_9 VDDCR_GFX_8
K12
ACROSS VDDNB AND VSS SPLIT VDDCR_GFX_9

AR17 VDDBT_RTC_G
VDDCR_GFX_10
VDDCR_GFX_11
K13
K15
CZ: All +APU_VDDGFX_RUN cap Stuff.
VDDCR_GFX_12 K16 CZ-L: All +APU_VDDGFX_RUN cap No Stuff.
VDDCR_GFX_30 T12
VDDCR_GFX_31 T15
B B
C150 C151 C152 C153 C154 C155 C156 C157 C158 VDDCR_GFX_32 T18
0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 0.22U/10V_4 180P/50V_4 VDDCR_GFX_33 T21
VDDCR_GFX_34 U13
VDDCR_GFX_35 U16
VDDCR_GFX_36 U19
VDDCR_GFX_37 U22
VDDCR_GFX_13 K19
BOTTOM SIDE DECOUPLING UNDER APU E FP4 REV 1.0

FP4
U8
20MIL 2
CN18
20MIL GND +1.5V_RTC
VDDBT_RTC R165 1K/F_4 +BAT R166 470/F_4 +VCCRTC_2 2 1 +3VRTC 3
+1.5V_RTC 1 VIN
2 D3 RB500V-40 1
VOUT
1
1

G1 C159 C160 88266-020L +3VPCU 2 1 IC AP2138N-1.5TRG1


*SHORT_ PAD1 0.22U/10V_4 1U/10V_4 C161
2

D4 RB500V-40 10U/6.3V_6

1
2

C663 C163
0.1U/10V_4 1U/10V_4

2
+1.5V
+APU_VDDIO_AZ

+1.8VS5 +APU_VDD_18_S5 form BAT coin --> stuff CN13/R527/D15


--> unstuff R529
R168 0_4 R173 0_4

1.5V For HDA Only C164 C165 C166 C175 C176


form BAT pack --> unstuff CN13/R527/D15
--> stuff R529
1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6 0.22U/10V_4

A A

+3V +APU_VDD_33 +3VS5 +APU_VDD_33_S5 +0.95VS5 +VDDP_S5

R169 0_4 R170 0_4 R171 0_6


PROJECT : X21
C167
10U/6.3VS_6
C168
10U/6.3VS_6
C169
0.22U/10V_4
C170
10U/6.3VS_6
C172
0.22U/10V_4
Quanta Computer Inc.
Size Document Number Rev
1A
Carrizo 6/7 (POWER)
NB5 RD
Date: Friday, October 17, 2014 Sheet 7 of 43
5 4 3 2 1
5 4 3 2 1

U2H
U2G U2J
D D
GND
GND AE10 VSS_125 VSS_187 AV30
A8 VSS_1 VSS_63 L28 AE13 VSS_126 VSS_188 AV33 APU_U30 U30 RSVD_2
ORIENT_APU# TP56 APU_U31
TP55 A12 VSS_2 VSS_64 M4 AE16 VSS_127 VSS_189 AW22 U31 RSVD_3
A16 M30 AE19 AY4 TP57 APU_AN30 AN30
VSS_3 VSS_65 VSS_128 VSS_190 RSVD_4
TP58
A20 VSS_4 VSS_66 N10 AE22 VSS_129 VSS_191 AY6
A24 VSS_5 VSS_67 N13 AF1 VSS_130 VSS_192 AY8
A28 VSS_6 VSS_68 N16 AF4 VSS_131 VSS_193 AY10
A32 VSS_7 VSS_69 N19 AG9 VSS_132 VSS_194 AY12
B2 VSS_8 VSS_70 N22 AG12 VSS_133 VSS_195 AY14
B8 VSS_9 VSS_71 N27 AG15 VSS_134 VSS_196 AY16
B12 VSS_10 VSS_72 P1 AG18 VSS_135 VSS_197 AY20
B33 VSS_11 VSS_73 P2 AG21 VSS_136 VSS_198 AY22 FP4 REV 1.0
C3 VSS_12 VSS_74 P4 AH4 VSS_137 VSS_199 AY24
D4 VSS_13 VSS_75 P5 AH10 VSS_138 VSS_200 AY26 FP4
D6 VSS_14 VSS_76 P12 AH13 VSS_139 VSS_201 AY28
D8 VSS_15 VSS_77 P15 AH16 VSS_140 VSS_202 AY30
D10 VSS_16 VSS_78 P18 AH19 VSS_141 VSS_203 BB1
D12 VSS_17 VSS_79 P21 AH22 VSS_142 VSS_204 BB33
D14 VSS_18 VSS_80 P30 AK1 VSS_143 VSS_205 BC4
D16 VSS_19 VSS_81 P33 AK4 VSS_144 VSS_206 BC8
D18 VSS_20 VSS_82 T4 AK12 VSS_145 VSS_207 BC12
D20 VSS_21 VSS_83 T10 AK15 VSS_146 VSS_208 BC16
D22 VSS_22 VSS_84 T13 AK18 VSS_147 VSS_209 BC20
C C
D24 VSS_23 VSS_85 T16 AL16 VSS_148 VSS_210 BC24
D26 VSS_24 VSS_86 T19 AL19 VSS_149 VSS_211 BC28
D28 VSS_25 VSS_87 T22 AL22 VSS_150 VSS_212 BC32
D30 VSS_26 VSS_88 T30 AM4 VSS_151
F1 VSS_27 VSS_89 U5 AN9 VSS_152
F2 VSS_28 VSS_90 U12 AN10 VSS_153
F4 VSS_29 VSS_91 U15 AN15 VSS_154
F9 VSS_30 VSS_92 U18 AN18 VSS_155
F19 VSS_31 VSS_93 U21 AN21 VSS_156
F22 VSS_32 VSS_94 U24 AN25 VSS_157
F25 VSS_33 VSS_95 V1 AN28 VSS_158
F30 VSS_34 VSS_96 V2 AP1 VSS_159
F33 VSS_35 VSS_97 V4 AP2 VSS_160
G7 VSS_36 VSS_98 W10 AP4 VSS_161
G17 VSS_37 VSS_99 W13 AP7 VSS_162
G20 VSS_38 VSS_100 W16 AP22 VSS_163
G23 VSS_39 VSS_101 W19 AP27 VSS_164
G26 VSS_40 VSS_102 W22 AP30 VSS_165
H4 VSS_41 VSS_103 Y4 AP33 VSS_166
H30 VSS_42 VSS_104 Y5 AR6 VSS_167
J5 VSS_43 VSS_105 Y12 AR25 VSS_168
J15 VSS_44 VSS_106 Y15 AR28 VSS_169
J19 VSS_45 VSS_107 Y18 AT4 VSS_170
B J22 VSS_46 VSS_108 Y21 AT19 VSS_171 B
J25 VSS_47 VSS_109 Y24 AT22 VSS_172
J28 VSS_48 VSS_110 AB1 AT30 VSS_173
K1 VSS_49 VSS_111 AB2 AU5 VSS_174
K2 VSS_50 VSS_112 AB4 AU8 VSS_175
K4 VSS_51 VSS_113 AB10 AU11 VSS_176
K10 VSS_52 VSS_114 AB13 AU14 VSS_177
K22 VSS_53 VSS_115 AB16 AU20 VSS_178
K27 VSS_54 VSS_116 AB19 AU23 VSS_179
K30 VSS_55 VSS_117 AB22 AU27 VSS_180
K33 VSS_56 VSS_118 AD4 AV4 VSS_181
L5 VSS_57 VSS_119 AD9 AV7 VSS_182
L12 VSS_58 VSS_120 AD12 AV9 VSS_183
L15 VSS_59 VSS_121 AD15 AV12 VSS_184 VSS_213 L24
L18 VSS_60 VSS_122 AD18 AV15 VSS_185 VSS_215 AL10
L21 VSS_61 VSS_123 AD21 AV25 VSS_186 VSS_214 AK21
L25 VSS_62 VSS_124 AD24
FP4 REV 1.0
FP4 REV 1.0 FP4
FP4

A A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 Carrzio 7/7 (GND)
Date: Friday, October 17, 2014 Sheet 8 of 43
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
C
DDR3 A0/B0 STD (4.0H) 1A
NB5 Date: Friday, October 17, 2014 Sheet 9 of 43
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
C
DDR3 A0/B0 STD (4.0H) 1A
NB5 Date: Friday, October 17, 2014 Sheet 10 of 43
5 4 3 2 1
5 4 3 2 1

M_A_DQ[63:0] 3
JDIM1A
3 M_A_A[15:0] M_A_A0 98 5 M_A_DQ0 2.48A +1.35VSUS
JDIM1B
M_A_A1 97 A0 DQ0 7 M_A_DQ4 75 44
M_A_A2 96 A1 DQ1 15 M_A_DQ7 76 VDD1 VSS16 48
M_A_A3 95 A2 DQ2 17 M_A_DQ3 81 VDD2 VSS17 49
M_A_A4 92 A3 DQ3 4 M_A_DQ1 82 VDD3 VSS18 54
M_A_A5 91 A4 DQ4 6 M_A_DQ5 87 VDD4 VSS19 55
M_A_A6 90 A5 DQ5 16 M_A_DQ2 88 VDD5 VSS20 60
M_A_A7 86 A6 DQ6 18 M_A_DQ6 93 VDD6 VSS21 61
M_A_A8 89 A7 DQ7 21 M_A_DQ13 94 VDD7 VSS22 65
M_A_A9 85 A8 DQ8 23 M_A_DQ9 99 VDD8 VSS23 66
D M_A_A10 107 A9 DQ9 33 M_A_DQ14 100 VDD9 VSS24 71 D
M_A_A11 84 A10/AP DQ10 35 M_A_DQ10 +1.35VSUS 105 VDD10 VSS25 72
M_A_A12 A11 DQ11 M_A_DQ12 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


83 22 106 127
M_A_A13 119 A12/BC# DQ12 24 M_A_DQ8 111 VDD12 VSS27 128
M_A_A14 80 A13 DQ13 34 M_A_DQ11 112 VDD13 VSS28 133
M_A_A15 78 A14 DQ14 36 M_A_DQ15 117 VDD14 VSS29 134
A15 DQ15 39 M_A_DQ21 118 VDD15 VSS30 138
109 DQ16 41 M_A_DQ17 123 VDD16 VSS31 139

PC2100 DDR3 SDRAM SO-DIMM


R7049
3 M_A_BS#0 108 BA0 DQ17 51 M_A_DQ19 124 VDD17 VSS32 144
3 M_A_BS#1 BA1 DQ18 M_A_DQ18 VDD18 VSS33
79 53 1K/F_4 145
3 M_A_BS#2 114 BA2 DQ19 40 M_A_DQ20 199 VSS34 150
3 M_A_CS#0 121 S0# DQ20 42 M_A_DQ16 +3V VDDSPD VSS35 151
3 M_A_CS#1 101 S1# DQ21 50 M_A_DQ23 M_A_EVENT# 77 VSS36 155
3 M_A_CLKP0 CK0 DQ22 M_A_DQ22 NC1 VSS37
103 52 122 156
3 M_A_CLKN0 102 CK0# DQ23 57 M_A_DQ25 125 NC2 VSS38 161
3 M_A_CLKP1 104 CK1 DQ24 59 M_A_DQ24 NCTEST VSS39 162
3 M_A_CLKN1 CK1# DQ25 M_A_DQ30 M_A_EVENT# VSS40
73 67 198 167
3 M_A_CKE0 CKE0 DQ26 M_A_DQ26 3 M_A_EVENT# EVENT# VSS41
74 69 30 168
3 M_A_CKE1 CKE1 DQ27 M_A_DQ28 3 M_A_RST# RESET# VSS42
115 56 172
3 M_A_CAS# CAS# DQ28 M_A_DQ29 VSS43
110 58 173
3 M_A_RAS# 113 RAS# DQ29 68 M_A_DQ31 +VREF_DQ0 1 VSS44 178
3 M_A_WE# DIMM0_SA0 WE# DQ30 M_A_DQ27 +VREF_DQ0 +VREF_CA0 VREF_DQ VSS45
197 70 126 179
DIMM0_SA1 SA0 DQ31 M_A_DQ36 +VREF_CA0 VREF_CA VSS46
201 129 184
SMB_RUN_CLK 202 SA1 DQ32 131 M_A_DQ37 VSS47 185
5,12,20 SMB_RUN_CLK SMB_RUN_DAT SCL DQ33 M_A_DQ34 VSS48
200 141 2 189
5,12,20 SMB_RUN_DAT SDA DQ34 M_A_DQ38 VSS1 VSS49
143 3 190
116 DQ35 130 M_A_DQ32 8 VSS2 VSS50 195
3 M_A_ODT0 120 ODT0 DQ36 132 M_A_DQ33 9 VSS3 VSS51 196

(204P)
3 M_A_DM[7..0] 3 M_A_ODT1 ODT1 DQ37 M_A_DQ35 VSS4 VSS52
140 13
M_A_DM0 11 DQ38 142 M_A_DQ39 14 VSS5
C M_A_DM1 28 DM0 DQ39 147 M_A_DQ41 19 VSS6 C
M_A_DM2 46 DM1 DQ40 149 M_A_DQ45 20 VSS7
M_A_DM3 63 DM2 DQ41 157 M_A_DQ47 25 VSS8

(204P)
M_A_DM4 136 DM3 DQ42 159 M_A_DQ46 26 VSS9 203
M_A_DM5 DM4 DQ43 M_A_DQ40 VSS10 VTT1 +0.65V_DDR_VTT
153 146 31 204
M_A_DM6 170 DM5 DQ44 148 M_A_DQ44 32 VSS11 VTT2
M_A_DM7 187 DM6 DQ45 158 M_A_DQ42 37 VSS12 205
DM7 DQ46 160 M_A_DQ43 38 VSS13 GND 206
3 M_A_DQSP[7:0] M_A_DQSP0 DQ47 M_A_DQ49 VSS14 GND
12 163 43 207
M_A_DQSP1 29 DQS0 DQ48 165 M_A_DQ48 VSS15 GND 208
M_A_DQSP2 47 DQS1 DQ49 175 M_A_DQ54 GND
M_A_DQSP3 64 DQS2 DQ50 177 M_A_DQ50 DDR3-DIMM1_H=4.0_RVS
M_A_DQSP4 137 DQS3 DQ51 164 M_A_DQ53 ddr-ddrrk-20401-tp4b-204p-smt
M_A_DQSP5 154 DQS4 DQ52 166 M_A_DQ52 DGMK0000158
M_A_DQSP6 171 DQS5 DQ53 174 M_A_DQ55 SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON
M_A_DQSP7 188 DQS6 DQ54 176 M_A_DQ51
3 M_A_DQSN[7:0] M_A_DQSN0 10 DQS7 DQ55 181 M_A_DQ61
M_A_DQSN1 27 DQS#0 DQ56 183 M_A_DQ60
M_A_DQSN2 45 DQS#1 DQ57 191 M_A_DQ59
M_A_DQSN3 62 DQS#2 DQ58 193 M_A_DQ63
M_A_DQSN4 135 DQS#3 DQ59 180 M_A_DQ56
M_A_DQSN5 152 DQS#4 DQ60 182 M_A_DQ57
M_A_DQSN6 169 DQS#5 DQ61 192 M_A_DQ62
M_A_DQSN7 186 DQS#6 DQ62 194 M_A_DQ58
DQS#7 DQ63

DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-smt
DGMK0000158
SOCKET DDR3 SODIMM(204P,H4.0,RVS)QBCON 4,5,6,7,12,20,21,22,23,24,27,28,29,30,36,38,40 +3V
B 3,7,12,33 +1.35VSUS B
12,33 +0.65V_DDR_VTT

Place these Caps near So-Dimm0. +1.35VSUS +1.35VSUS

EC63 180P/50V_4
+1.35VSUS +0.65V_DDR_VTT R606
EC14 180P/50V_4 *1K/F_4
C520 1U/6.3V_4 C3570 1U/6.3V_4
EC18 180P/50V_4
C519 1U/6.3V_4 C372 1U/6.3V_4 R609 0_6 +VREF_CA0
EC25 220P/50V_4 12,33 DDR_VTTREF
C366 1U/6.3V_4 C439 1U/6.3V_4 3mA
EC24 220P/50V_4 R612
C452 1U/6.3V_4 C408 1U/6.3V_4 *1K/F_4
EC17 220P/50V_4
C457 10U/6.3VS_6 C3830 10U/6.3VS_6
EC29 220P/50V_4
C412 10U/6.3VS_6 C423 *10U/6.3VS_6
EC28 220P/50V_4
C414 10U/6.3VS_6 +VREF_DQ0
EC30 220P/50V_4
C416 10U/6.3VS_6 C358 0.1U/10V_4
EC26 220P/50V_4
C458 10U/6.3VS_6 +1.35VSUS

C456 10U/6.3VS_6
C373 1000P/50V_4 EC21 220P/50V_4 53537_105 change:
EC27 0.1U/10V_4 R294 Type 1: and Type 2: from 1K/2 voltage
A C422 *10U/6.3VS_6 A
1K/F_4
EC22 2200P/50V_4
C417 10U/6.3VS_6 +VREF_CA0
R610 *0_6 +VREF_DQ0
C448 10U/6.3VS_6 3 M_A_VREFDQ
C420 0.1U/10V_4 3mA
+0.65V_DDR_VTT R296 PROJECT : X21
C419 1000P/50V_4 EC31 *120P/50V_4
1K/F_4
Quanta Computer Inc.
EC19 *120P/50V_4
C418 *0.047U/10V_4 Size Document Number Rev
Custom
System Memory 1/2 (4H) 1A
NB5 Date: Friday, October 17, 2014 Sheet 11 of 43
5 4 3 2 1
5 4 3 2 1

+1.35VSUS
M_B_DQ[63:0] 3
JDIM2A JDIM2B
3 M_B_A[15:0] M_B_A0 M_B_DQ5
98 5 75 44
M_B_A1 97 A0 DQ0 7 M_B_DQ4 76 VDD1 VSS16 48
M_B_A2 96 A1 DQ1 15 M_B_DQ3 81 VDD2 VSS17 49
M_B_A3 95 A2 DQ2 17 M_B_DQ2 82 VDD3 VSS18 54
M_B_A4 92 A3 DQ3 4 M_B_DQ0 87 VDD4 VSS19 55
M_B_A5 91 A4 DQ4 6 M_B_DQ1 88 VDD5 VSS20 60
M_B_A6 90 A5 DQ5 16 M_B_DQ6 93 VDD6 VSS21 61
M_B_A7 86 A6 DQ6 18 M_B_DQ7 94 VDD7 VSS22 65
M_B_A8 A7 DQ7 M_B_DQ9 VDD8 VSS23
D M_B_A9
89
85 A8 DQ8
21
23 M_B_DQ13 +1.35VSUS 2.48A 99
100 VDD9 VSS24
66
71 D
M_B_A10 107 A9 DQ9 33 M_B_DQ14 105 VDD10 VSS25 72
M_B_A11 A10/AP DQ10 M_B_DQ10 VDD11 VSS26

PC2100 DDR3 SDRAM SO-DIMM


84 35 106 127
M_B_A12 83 A11 DQ11 22 M_B_DQ8 111 VDD12 VSS27 128
M_B_A13 119 A12/BC# DQ12 24 M_B_DQ12 112 VDD13 VSS28 133
M_B_A14 80 A13 DQ13 34 M_B_DQ11 117 VDD14 VSS29 134
M_B_A15 78 A14 DQ14 36 M_B_DQ15 R7050 118 VDD15 VSS30 138
A15 DQ15 39 M_B_DQ20 123 VDD16 VSS31 139
109 DQ16 41 M_B_DQ21 124 VDD17 VSS32 144

PC2100 DDR3 SDRAM SO-DIMM


1K/F_4
3 M_B_BS#0 BA0 DQ17 M_B_DQ18 VDD18 VSS33
108 51 145
3 M_B_BS#1 79 BA1 DQ18 53 M_B_DQ22 199 VSS34 150
3 M_B_BS#2 BA2 DQ19 M_B_DQ17 M_B_EVENT# +3V VDDSPD VSS35
114 40 151
3 M_B_CS#0 121 S0# DQ20 42 M_B_DQ16 77 VSS36 155
3 M_B_CS#1 S1# DQ21 M_B_DQ19 NC1 VSS37
101 50 122 156
3 M_B_CLKP0 103 CK0 DQ22 52 M_B_DQ23 125 NC2 VSS38 161
3 M_B_CLKN0 102 CK0# DQ23 57 M_B_DQ25 NCTEST VSS39 162
3 M_B_CLKP1 CK1 DQ24 M_B_DQ29 M_B_EVENT# VSS40
104 59 198 167
3 M_B_CLKN1 CK1# DQ25 M_B_DQ27 3 M_B_EVENT# EVENT# VSS41
73 67 30 168
3 M_B_CKE0 CKE0 DQ26 M_B_DQ26 3 M_B_RST# RESET# VSS42
74 69 172
3 M_B_CKE1 CKE1 DQ27 M_B_DQ28 VSS43
115 56 173
3 M_B_CAS# 110 CAS# DQ28 58 M_B_DQ24 +VREF_DQ1 1 VSS44 178
3 M_B_RAS# RAS# DQ29 M_B_DQ31 +VREF_DQ1 +VREF_CA1 VREF_DQ VSS45
113 68 126 179
3 M_B_WE# DIMM1_SA0 WE# DQ30 M_B_DQ30 +VREF_CA1 VREF_CA VSS46
R339 4.7K_4 197 70 184
+3V DIMM1_SA1 SA0 DQ31 M_B_DQ36 VSS47
201 129 185
202 SA1 DQ32 131 M_B_DQ37 2 VSS48 189
5,11,20 SMB_RUN_CLK SCL DQ33 M_B_DQ35 VSS1 VSS49
200 141 3 190
5,11,20 SMB_RUN_DAT SDA DQ34 M_B_DQ34 VSS2 VSS50
143 8 195
116 DQ35 130 M_B_DQ33 9 VSS3 VSS51 196

(204P)
3 M_B_ODT0 ODT0 DQ36 M_B_DQ32 VSS4 VSS52
120 132 13
3 M_B_DM[7..0] 3 M_B_ODT1 ODT1 DQ37 M_B_DQ39 VSS5
140 14
C M_B_DM0 11 DQ38 142 M_B_DQ38 19 VSS6 C
M_B_DM1 28 DM0 DQ39 147 M_B_DQ44 20 VSS7
M_B_DM2 46 DM1 DQ40 149 M_B_DQ40 25 VSS8
M_B_DM3 63 DM2 DQ41 157 M_B_DQ42 26 VSS9 203

(204P)
M_B_DM4 DM3 DQ42 M_B_DQ43 VSS10 VTT1 +0.65V_DDR_VTT
136 159 31 204
M_B_DM5 153 DM4 DQ43 146 M_B_DQ45 32 VSS11 VTT2
M_B_DM6 170 DM5 DQ44 148 M_B_DQ41 37 VSS12 205
M_B_DM7 187 DM6 DQ45 158 M_B_DQ46 38 VSS13 GND 206
DM7 DQ46 160 M_B_DQ47 43 VSS14 GND 207
3 M_B_DQSP[7:0] M_B_DQSP0 12 DQ47 163 M_B_DQ49 VSS15 GND 208
M_B_DQSP1 29 DQS0 DQ48 165 M_B_DQ48 GND
M_B_DQSP2 47 DQS1 DQ49 175 M_B_DQ54 DDR3-DIMM0_H=4.0_STD
M_B_DQSP3 64 DQS2 DQ50 177 M_B_DQ55 ddr-ddrsk-20401-tp4b-204p-smt
M_B_DQSP4 137 DQS3 DQ51 164 M_B_DQ52 DGMK0000160
M_B_DQSP5 154 DQS4 DQ52 166 M_B_DQ53 SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON
M_B_DQSP6 171 DQS5 DQ53 174 M_B_DQ50
M_B_DQSP7 188 DQS6 DQ54 176 M_B_DQ51
3 M_B_DQSN[7:0] M_B_DQSN0 10 DQS7 DQ55 181 M_B_DQ61
M_B_DQSN1 27 DQS#0 DQ56 183 M_B_DQ56 4,5,6,7,11,20,21,22,23,24,27,28,29,30,36,38,40 +3V
M_B_DQSN2 45 DQS#1 DQ57 191 M_B_DQ63 3,7,11,33 +1.35VSUS
M_B_DQSN3 62 DQS#2 DQ58 193 M_B_DQ62 11,33 +0.65V_DDR_VTT
M_B_DQSN4 135 DQS#3 DQ59 180 M_B_DQ57
M_B_DQSN5 152 DQS#4 DQ60 182 M_B_DQ60
M_B_DQSN6 169 DQS#5 DQ61 192 M_B_DQ58
M_B_DQSN7 186 DQS#6 DQ62 194 M_B_DQ59
DQS#7 DQ63
DDR3 Thermal Sensor
DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-smt Local Thermal Sensor
DGMK0000160 C565 *0.01U/50V_4
B SOCKET DDR3 SODIMM(204P,H4.0,STD)QBCON B
U18
DDR_THRMSEN_CLK 8 1
SCLK VCC +3V
DDR_THRMSEN_DATA 7 2 DDR_THERMDA
+1.35VSUS SDA DXP
Place these Caps near So-Dimm1. M_B_EVENT#

3
6 3
EC20 180P/50V_4 ALERT# DXN 2 Q28
+1.35VSUS R407 *10K/F_4 4 5 C579 *METR3904-G
+0.65V_DDR_VTT +3V OVERT# GND
+1.35VSUS EC62 180P/50V_4 *2200P/50V_4

1
C449 1U/6.3V_4 C433 1U/6.3V_4 EC41 220P/50V_4 *G781-1P8 DDR_THERMDC
R613
C523 1U/6.3V_4 C454 1U/6.3V_4 EC37 220P/50V_4 *1K/F_4 MBDATA2 R7113 *0_4 DDR_THRMSEN_DATA

C368 1U/6.3V_4 C453 1U/6.3V_4 EC40 220P/50V_4


+VREF_CA1
If use internal thermal IC, C9007 use 0ohm.
R615 0_6
C451 1U/6.3V_4 C463 1U/6.3V_4 EC38 220P/50V_4 11,33 DDR_VTTREF MBCLK2 R7114 *0_4 DDR_THRMSEN_CLK
3mA Q27A *2N7002KDW
C517 10U/6.3VS_6 C429 10U/6.3VS_6 EC34 220P/50V_4 R618
MBDATA2
Dual 3 4 DDR_THRMSEN_DATA
*1K/F_4 4,20,30 MBDATA2
C497 10U/6.3VS_6 C399 *10U/6.3VS_6 EC36 220P/50V_4
R392 *4.7K_4
C515 10U/6.3VS_6 +VREF_DQ1 EC39 220P/50V_4

5
+3V
C518 10U/6.3VS_6 C459 0.1U/10V_4 EC35 220P/50V_4

2
R393 *4.7K_4
C450 10U/6.3VS_6 +1.35VSUS
C471 1000P/50V_4 MBCLK2 6 1 DDR_THRMSEN_CLK
4,20,30 MBCLK2
A C516 10U/6.3VS_6 53537_105 change: Dual A

C521 *10U/6.3VS_6 +VREF_CA1 Type 1: and Type 2: from 1K/2 voltage R617
1K/F_4
Q27B
C504 0.1U/10V_4 *2N7002KDW
C367 10U/6.3VS_6 +3V
Main:AL000781039 G781-1P8(9Ah)
+VREF_DQ1
PROJECT : X21
R616 *0_6
C507 10U/6.3VS_6 C505 1000P/50V_4 C445 0.1U/10V_4 3 M_B_VREFDQ 2nd:AL001412005 EMC1412-2-ACZL-TR(9Ah)
3mA
C374 2.2U/6.3V_6
R614 Quanta Computer Inc.
C503 *0.047U/10V_4
C3590 1000P/50V_4 1K/F_4 Main:AL001412003 EMC1412-1-ACZL-TR(98h)
2nd:AL000431014 TMP431ADGKR(98h) Size
Custom
Document Number Rev
System Memory 2/2 (4H) 1A
NB5 Date: Friday, October 17, 2014 Sheet 12 of 43
5 4 3 2 1
U4000A
Platform Type P/N
9/2: CZ use 0.22u(Gen 3) ; CZ-L use 0.1u(Gen 2)
Carrizo Gen 3 CH4222K9B04
Carrizo-L Gen 1/Gen 2 CH4102K1B03
PEG_TXP0 AF30 AH30 C_PEG_RXP0 C4000 0.22U/10V_4
2 PEG_TXP0 PEG_TXN0 AE31 PCIE_RX0P PCIE_TX0P AG31 C_PEG_RXN0 PEG_RXP0 2
C4001 0.22U/10V_4 U4000G
2 PEG_TXN0 PCIE_RX0N PCIE_TX0N PEG_RXN0 2
DP POWER NC/DP POWER
PEG_TXP1 AE29 AG29 C_PEG_RXP1 C4002 0.22U/10V_4
2 PEG_TXP1 PEG_TXN1 AD28 PCIE_RX1P PCIE_TX1P AF28 C_PEG_RXN1 PEG_RXP1 2 AG15 AE11
C4003 0.22U/10V_4
2 PEG_TXN1 PCIE_RX1N PCIE_TX1N PEG_RXN1 2 NC_DP_VDDR#1 NC#AE11
AG16 AF11
AF16 NC_DP_VDDR#2 NC#AF11 AE13
PEG_TXP2 AD30 AF27 C_PEG_RXP2 C4004 0.22U/10V_4 AG17 NC_DP_VDDR#3 NC#AE13 AF13
2 PEG_TXP2 PEG_TXN2 AC31 PCIE_RX2P PCIE_TX2P AF26 C_PEG_RXN2 PEG_RXP2 2 AG18 NC_DP_VDDR#4 NC#AF13 AG8
C4005 0.22U/10V_4
2 PEG_TXN2 PCIE_RX2N PCIE_TX2N PEG_RXN2 2 AG19 NC_DP_VDDR#5 NC#AG8 AG10
1.8V ( 40mA) NC_DP_VDDR#6 NC#AG10
AF14
PEG_TXP3 C_PEG_RXP3 +1.8V_VGA DP_VDDR
AC29 AD27 C4006 0.22U/10V_4
2 PEG_TXP3 PEG_TXN3 AB28 PCIE_RX3P PCIE_TX3P AD26 C_PEG_RXN3 PEG_RXP3 2
C4007 0.22U/10V_4 C4009
2 PEG_TXN3 PCIE_RX3N PCIE_TX3N PEG_RXN3 2
C4008
10U/6.3VS_6 1U/10V_4
PEG_TXP4 AB30 AC25 C_PEG_RXP4 C4010 0.22U/10V_4
2 PEG_TXP4 PEG_TXN4 AA31 PCIE_RX4P PCIE_TX4P AB25 C_PEG_RXN4 PEG_RXP4 2 AG20 AF6
C4011 0.22U/10V_4
2 PEG_TXN4 PCIE_RX4N PCIE_TX4N PEG_RXN4 2 NC_DP_VDDC#1 NC#AF6
AG21 AF7
AF22 NC_DP_VDDC#2 NC#AF7 AF8
PEG_TXP5 AA29 Y23 C_PEG_RXP5 AG22 NC_DP_VDDC#3 NC#AF8 AF9
2 PEG_TXP5 PCIE_RX5P PCIE_TX5P
C4012 0.22U/10V_4
PEG_RXP5 2 1.0V ( 32mA) NC_DP_VDDC#4 NC#AF9
PEG_TXN5 Y28 Y24 C_PEG_RXN5 AD14

PCI EXPRESS INTERFACE


C4013 0.22U/10V_4 +1.0V_VGA
2 PEG_TXN5 PCIE_RX5N PCIE_TX5N PEG_RXN5 2 DP_VDDC
C4014 C4015 C4016
PEG_TXP6 Y30 AB27 C_PEG_RXP6 C4017 0.22U/10V_4 *10U/6.3VS_6 1U/10V_4 0.1U/10V_4
2 PEG_TXP6 PEG_TXN6 PCIE_RX6P PCIE_TX6P C_PEG_RXN6 PEG_RXP6 2
W31 AB26 C4018 0.22U/10V_4 AG14 AE1
2 PEG_TXN6 PCIE_RX6N PCIE_TX6N PEG_RXN6 2 AH14 NC_DP_VSSR#1 NC#AE1 AE3
AM14 NC_DP_VSSR#2 NC#AE3 AG1
PEG_TXP7 W29 Y27 C_PEG_RXP7 C4019 0.22U/10V_4 AM16 NC_DP_VSSR#3 NC#AG1 AG6
2 PEG_TXP7 PEG_TXN7 V28 PCIE_RX7P PCIE_TX7P Y26 C_PEG_RXN7 PEG_RXP7 2 AM18 NC_DP_VSSR#4 NC#AG6 AH5
C4020 0.22U/10V_4
2 PEG_TXN7 PCIE_RX7N PCIE_TX7N PEG_RXN7 2 AF23 NC_DP_VSSR#5 NC#AH5 AF10
AG23 NC_DP_VSSR#6 NC#AF10 AG9
V30 W24 AM20 NC_DP_VSSR#7 NC#AG9 AH8
U31 NC#V30 NC#W24 W23 AM22 NC_DP_VSSR#8 NC#AH8 AM6
NC#U31 NC#W23 AM24 NC_DP_VSSR#9 NC#AM6 AM8
AF19 NC_DP_VSSR#10 NC#AM8 AG7
U29 V27 AF20 NC_DP_VSSR#11 NC#AG7 AG11
T28 NC#U29 NC#V27 U26 AE14 NC_DP_VSSR#12 NC#AG11
NC#T28 NC#U26 DP_VSSR

T30 U24
R31 NC#T30 NC#U24 U23
NC#R31 NC#U23 AF17 AE10
NC_UPHYAB_DP_CALR NC#AE10
R29 T26
P28 NC#R29 NC#T26 T27
NC#P28 NC#T27 Meso_S3

P30 T24
N31 NC#P30 NC#T24 T23
NC#N31 NC#T23

N29 P27
M28 NC#N29 NC#P27 P26
NC#M28 NC#P26

M30 P24
L31 NC#M30 NC#P24 P23
NC#L31 NC#P23

L29 M27
K30 NC#L29 NC#M27 N26
NC#K30 NC#N26
12/10:reserve for verify
CLOCK
CLK_GFX_P AK30 +3V_VGA
6 CLK_GFX_P CLK_GFX_N AK32 PCIE_REFCLKP
6 CLK_GFX_N PCIE_REFCLKN

CALIBRATION
Y22 SUN_PCIE_CALRP R4000 1.69K/F_4
PCIE_CALR_TX +1.0V_VGA
R4001 1K/F_4 TEST_PG N10 AA22 SUN_PCIE_CALRN R4002 1K/F_4 R4003
TEST_PG PCIE_CALR_RX
1K/F_4
PEGX_RST# AL27
PERSTB PCIE_RST#_R1 2

Meso_S3 3 PEGX_RST#
+3V_VGA
DGPU_HIN_RST# 1

D4000
BAT54AW-L

14,16,40,43 +3V_VGA
C4021 14,16,40,41,43 +1.8V_VGA
U4001 *0.1U/10V_4 16,40,43 +1.0V_VGA
C4022 *0.1U/10V_4 *MC74VHC1G08DFT2G
5

5,23,29 PCIE_RST#_R1
2
4 PEGX_RST#
DGPU_HIN_RST# 1 PEGX_RST# 14
5 VGA_RSTB R4004 0_4

R4005
3

100K/F_4

PROJECT : Y23
Quanta Computer Inc.
Size Document Number Rev
1A
TOPAZ S3 PCIE/DP power
NB5
Friday, October
Date:17, 2014 Sheet 13 of 43
+1.8V_VGA +1.8V_VGA
U4000B
10/1 : Gen 3 support or not
Carrizo : PU 8.45K ; PD 2K

AF2
Carrizo-L : PU NC ; PD 4.75K
10/2 : remove TP for no use R4043 R4044
NC#AF2
DVO NC#AF4
AF4 8.45K/F_4 8.45K/F_4 Beema : PU NC ; PD 4.75K
N9 AG3 PS_0 PS_1
DBG_DATA16 NC#AG3
L9
DBG_DATA15
DPA NC#AG5
AG5
AE9
Y11 DBG_DATA14 AH3 C4027
AE8 DBG_DATA13 NC#AH3 AH1 R4046 R4048 C4028
*0.01U/25V_4
AD9 DBG_DATA12 NC#AH1 2K/F_4 2K/F_4 *0.082U/16V_4
+3V_VGA AC10 DBG_DATA11 AK3
Thermal Solution(Close to GPU) AD7 DBG_DATA10 NC#AK3 AK1
AC8 DBG_DATA9 NC#AK1
C4023 *0.01U/25V_4 AC7 DBG_DATA8 AK5
AB9 DBG_DATA7 NC#AK5 AM3 +1.8V_VGA +1.8V_VGA
R4007 U4002 AB8 DBG_DATA6 NC#AM3
9/2: modify to +3V_VGA AB7 DBG_DATA5 AK6
10K/F_4
DGPUT_CLK 8 1 AB4 DBG_DATA4 NC#AK6 AM5
SCLK VCC +3V_VGA DBG_DATA3 NC#AM5
DGPUT_DATA GPU_THERMDA
AB2
DBG_DATA2
DPB
7 2 Y8 AJ7 R4051 R4052
SDA DXP Y7 DBG_DATA1 NC#AJ7 AH6 *0_4 8.45K/F_4
VGA_ALERT R4006 0_4 VGA_ALERT_R 6 3 DBG_DATA0 NC#AH6
ALERT# DXN C4024 AK8 PS_2 PS_3
R4008 *10K/F_4 4 5 *2200P/50V_4 NC#AK8 AL7
+3V_VGA OVERT# GND NC#AL7
GPU_THERMDC BIT5 => BIT0
30 DGPU_OVT#
*G781-1P8 W6 DPC R4053 C4031 R4054 C4032
NC#W6
+1.8V_VGA V6
NC#V6
4.75K/F_4 *0.68U/4V_4 2K/F_4 *0.01U/25V_4 PS0 => 11001
V4
NC#V4 U5
Main:AL000781039 G781-1P8(9Ah) NC#U5
AC5
NC#AC5 PS1 => 11000
9/11: follow CRB change to 10K AC6
N#CAC6 V2
NC#V2
PS2 => 11000
R4009 R4010 Y4
10K_4 10K_4 AA5 NC#Y4 W5
NC#AA5 NC#W5
+3V_VGA
AA6
NC#AA6 PS3 => 11000
Y2
R4011 10K/F_4 GPU_AC_BATT R4012 *10K/F_4 NC#Y2 J8
U1 NC#J8
DGPU_TDI TP4017 NC#U1/BP_0
R4013 *10K/F_4 AA1
NC#AA1/PLL_ANALOG_IN TP4018
U3 AA3 R4014 16.2K/F_4
DGPU_TMS TP4019 NC#U3/BP_1 NC#AA3/PLL_ANALOG_OUT
R4015 *10K/F_4 Y6
NC#Y6
R4016 *10K/F_4 DGPU_TDO

R4017 *10K/F_4 DGPU_TRSTB +3V_VGA


R4018 4.7K_4 R1
*10K/F_4 PCIE_REQ_GPU# R4020 4.7K_4 R3 SCL
R4019
SDA I2C Follow AMD check list
R4021 *10K/F_4 DGPU_PROCHOT# +3V_VGA AM26 R4022 *10K/F_4
R4023 47K/F_4 GENERAL PURPOSE I/O DCM/NC_R AK26
R4024 47K/F_4 U6 NC_AVSSN#AK26
GPIO_0 AL25
NC_G AJ25 +3V_VGA
9/4: change to 47K ohm for CRB DGPUT_DATA R4025 0_4 DGPUT_DATA_R U8 NC_AVSSN#AJ25
DGPUT_CLK R4026 0_4 DGPUT_CLK_R U7 SMBDATA AH24
R4027 10K/F_4 TEMP_FAIL R4028 0_4 GPU_GPIO5 T9 SMBCLK NC_B AG25 R4029 R4105 *4.7K_4
30 GPU_AC_BATT GPU_GPIO6 GPIO_5_AC_BATT NC_AVSSN#AG25

2
T8
PCC/GPIO_6
GPIO8_ROMSO
T7
NC_GPIO_7
DAC1 NC_HSYNC
AH26 *4.7K_4 Q4004
P10 AJ27 1 3
TP4020 GPIO9_ROMSI GPIO_8_ROMSO NC_VSYNC/WAKEb TP4021
P4 *2N7002K
TP4022 GPIO10_ROMSCK GPIO_9_ROMSI
P2
TP4023 GPIO_10_ROMSCK
N6 AD22 9/4: follow CRB design by FAE
TP4024 NC_GPIO_11 NC_RSET
N5 R4030
TP4025 NC_GPIO_12
N3 AG24 4.7K_4
TP4026 NC_GPIO_13 NC_AVDD AE22
N1 NC_AVSSQ
M4 GPIO_15_PW RCNTL_0 AE23
AMD recommend VGA_ALERT R6 GPIO_16 NC_VDD1DI AD23
GPIO_17_THERMAL_INT NC_VSS1DI
R4031 0_4 TEMP_FAIL M2
30 TEMP_FAIL GPIO_19_CTF
P8 AM12
P7 GPIO_20_PW RCNTL_1 NC
Q4000A *2N7002KDW GPIO22_ROMCS N8 GPIO_21 GPU_SVD R4032 0_4
TP4027 DGPU_PROCHOT# DGPU_PROCHOT#_RAK10 GPIO_22_ROMCSB GPU_SVD SVI2_DATA 41
AK12
GPUT_DATA Dual 3 4 DGPUT_DATA
R4033 *0_4
AM10 GPIO_29 NC_SVI2#1/GPIO_SVD AL11 GPU_SVT GPU_SVC R4034 0_4
30 GPUT_DATA TP4028 PCIE_REQ_GPU# GPIO_30 NC_SVI2#2/GPIO_SVT GPU_SVC SVI2_CLK 41
N7 AJ11
DGPU_TRSTB L6 CLKREQB NC_SVI2#3/GPIO_SVC GPU_SVT R4035 0_4
TP4029 JTAG_TRSTB SVI2_SVT 41
R4196 *0_4
PEGX_RST# 13
5

DGPU_TDI L5 AL13
R4036 *4.7K_4 9/9: follow AMD CRB design TP4030 DGPU_TCK L3 JTAG_TDI NC_GENLK_CLK AJ13
+3V_VGA TP4031 DGPU_TMS JTAG_TCK NC_GENLK_VSYNC
L1 +3V_VGA +1.8V_VGA
TP4032 DGPU_TDO JTAG_TMS
2

K4
TP4033 JTAG_TDO
GPUT_CLK DGPUT_CLK
TESTEN K7
TESTEN DAC2
30 GPUT_CLK 6 1 AF24 AG13 R4037
NC#AF24 NC_SWAPLOCKA AH12 1K/F_4
Dual NC_SWAPLOCKB R4038
10K/F_4
R4197 10K/F_4 GPU_SVD R4198 10K/F_4
Q4000B*2N7002KDW GPU_GPIO6
DGPU_OCP_L 41 GPU_SVC R4200
W8 R4199 10K/F_4 10K/F_4
NC_GENERICB AC19 PS_0 C4025
R4039 0_4 W7 PS_0 R4201 10K/F_4 GPU_SVT R4202 10K/F_4
AD10 NC_GENERICD AD19 PS_1 0.1U/10V_4
AJ9 NC_GENERICE_HPD4 PS_1
+3V_VGA AL9 NC#AJ9 AE17 PS_2
DBG_CNTL0 PS_2
AE20 PS_3
PS_3 9/11: Add for SR Tool review result
R4041 C4026 12P/50V_4 PX_EN AB16 AE19 R4042 *0_4 Reserved. Do not connect on the PCB
TP4034 PX_EN TS_A
*5.1K/F_4
EVGA-XTALI
AC16
NC_DBG_VREFG
2
1

PS_3[3:1] Vendor Type Vendor P/N PU PD


TESTEN Y4000 R4045
1M_4 DDC/AUX
000 Hynix 256Mx16 *4, 900Mhz H5TC4G63CFR-N0C NC 4.75K
AE6
NC_DDC1CLK
27MHZ +-10PPM PLL/CLOCK
NC_DDC1DATA
AE5 001 Samsung 256Mx16 *4, 900Mhz K4W4G1646E-BC1A 8.45K 2K
4
3

R4047 EVGA-XTALO
1K/F_4
NC_AUX1P
AD2 010 Micron 256Mx16 *4, 900Mhz MT41J256M16HA-093G:E 4.53K 2K
C4029 12P/50V_4 AD4
NC_AUX1N
011
EVGA-XTALI AM28
AK28 XTALIN
9/2: follow Ref SCH by FAE EVGA-XTALO
XTALOUT 100
AD13 101
R4049 10K/F_4 AC22 NC_AUX2P AD11
R4050 10K/F_4 AB22 XO_IN NC_AUX2N
XO_IN2

4.53K CS24532FB08
HCB1608KF-121T30(120+-25%,3A) 1.8V(13mA TSVDD) AE16
GPU_THERMDA NC#AE16
+1.8V_VGA GPU_THERMDC
T4
DPLUS NC#AD16
AD16 4.75K CS24752FB12
L4000 T2 THERMAL
DMINUS
NC_DDCVGACLK
AC1
TP4035 8.45K CS28452FB12
C4030 AC3
NC_DDCVGADATA TP4036
+1.8V_TSVDD
R5
GPIO28_FDO
2K CS22002FB19
1U/10V_4 AD17 For AMD tuning
AC17 TSVDD
TSVSS
timing purpose

E PROJECT : Y23
Meso_S3 Quanta Computer Inc.
Size Document Number Rev
+1.8V_VGA 13,16,40,41,43
1A
+1.0V_VGA 13,16,40,43
NB5 RD TOPAZ_S3_Main
Dat e: Friday, October 17, 2014 Sheet 14 of 43
U4000E
U4000F

AA27 A3
AB24 PCIE_VSS#1 GND#1 A30 LVDS CONTROL
AB32 PCIE_VSS#2 GND#2 AA13 RECOMMENDED SETTINGS
AC24 PCIE_VSS#3 GND#3 AA16 0= DO NOT INSTALL RESISTOR
AC26 PCIE_VSS#4 GND#4 AB10 CONFIGURATION STRAPS-- SEE EACH DATABOOK FOR STRAP DETAILS 1 = INSTALL 3K RESISTOR
AC27 PCIE_VSS#5 GND#5 AB15 X = DESIGN DEPENDANT
AD25 PCIE_VSS#6 GND#6 AB6
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, NA = NOT APPLICABLE
AD32 PCIE_VSS#7 GND#7 AC9 AL15 THEY MUST NOT CONFLICT DURING RESET
AE27 PCIE_VSS#8 GND#8 AD6 NC_UPHYAB_TMDPA_TX0N AK14
AF32 PCIE_VSS#9 GND#9 AD8 NC_UPHYAB_TMDPA_TX0P
AG27 PCIE_VSS#10 GND#10 AE7 AH16 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
AH32 PCIE_VSS#11 GND#11 AG12 NC_UPHYAB_TMDPA_TX1N AJ15
K28 PCIE_VSS#12 GND#12 AH10 NC_UPHYAB_TMDPA_TX1P
K32 PCIE_VSS#13 GND#13 AH28 AL17 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING
L27 PCIE_VSS#14 GND#14 B10 NC_UPHYAB_TMDPA_TX2N AK16
PCIE_VSS#15 GND#15 NC_UPHYAB_TMDPA_TX2P 0
M32 B12 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED
N25 PCIE_VSS#16 GND#16 B14 AH18 X
N27 PCIE_VSS#17 GND#17 B16 NC_UPHYAB_TMDPA_TX3N AJ17
P25 PCIE_VSS#18 GND#18 B18 NC_UPHYAB_TMDPA_TX3P RSVD GPIO2 RESERVED 0
P32 PCIE_VSS#19 GND#19 B20 AL19 RSVD GPIO8 RESERVED 0
R27 PCIE_VSS#20 GND#20 B22 NC_TXOUT_L3P AK18
T25 PCIE_VSS#21 GND#21 B24 NC_TXOUT_L3N
T32 PCIE_VSS#22 GND#22 B26 BIF_VGA DIS GPIO9 VGA ENABLED 0
U25 PCIE_VSS#23 GND#23 B6 TMDP
U27 PCIE_VSS#24 GND#24 B8
V32 PCIE_VSS#25 GND#25 C1 AH20 RSVD GPIO21 RESERVED 0
W25 PCIE_VSS#26 GND#26 C32 NC_UPHYAB_TMDPB_TX0N AJ19
W26 PCIE_VSS#27 GND#27 E28 NC_UPHYAB_TMDPB_TX0P
W27 PCIE_VSS#28 GND#28 F10 AL21 BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM
PCIE_VSS#29 GND#29 NC_UPHYAB_TMDPB_TX1N 0
Y25 F12 AK20
Y32 PCIE_VSS#30 GND#30 F14 NC_UPHYAB_TMDPB_TX1P
PCIE_VSS#31 GND#31 F16 AH22 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT 0 01
GND#32 F18 NC_UPHYAB_TMDPB_TX2N AJ21
GND#33 F2 NC_UPHYAB_TMDPB_TX2P
GND#34 F20 AL23 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS (Removed on Seymour/Whistler) 0
M6 GND#35 F22 NC_UPHYAB_TMDPB_TX3N AK22
N11 GND#56 GND#36 F24 NC_UPHYAB_TMDPB_TX3P
GND#57 GND#37 F26 AK24 RSVD H2SYNC RESERVED 0
N13 GND#38 F6 NC_TXOUT_U3P AJ23
GND#58 GND#39 NC_TXOUT_U3N
N16
N18
N21
GND#59
GND#60 GND GND#40
GND#41
F8
G10
G27
AUD[1]
AUD[0]
HSYNC
VSYNC
SEE DATABOOK FOR DETAIL
SEE DATABOOK FOR DETAIL
0
0
P6 GND#61 GND#42 G31
P9 GND#62 GND#43 G8 Meso_S3
R12 GND#63 GND#44 H14 RSVD GENERICC RESERVED 0
R15 GND#64 GND#45 H17
R17 GND#65 GND#46 H2
R20 GND#66 GND#47 H20
T13 GND#67 GND#48 H6
T16 GND#68 GND#49 J27
T18 GND#69
GND#70
GND#50
GND#51
J31 NOTE1: AMD RESERVED CONFIGURATION STRAPS
T21 K11
T6 GND#71 GND#52 K2
U15 GND#72 GND#53 K22
ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL RESISTOR. IF THESE GPIOS ARE USED,
U17 GND#73 GND#54 K6 THEY MUST KEEP "LOW" AND NOT CONFLICT DURING RESET.
U20 GND#74 GND#55 T11
U9 GND#75 GND#84 R11
V13 GND#76 GND#85 GPIO21 H2SYNC GENERICC GPIO8 GPIO2
V16 GND#77
V18 GND#78
Y10 GND#79
Y15 GND#80
Y17 GND#81 A32
Y20 GND#82 VSS_MECH#1 AM1
AA11 GND#83 VSS_MECH#2 AM32
M12 GND#86 VSS_MECH#3
V11 GND#87
GND#88

Meso_S3

PROJECT : Y23
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 TOPAZ_S3_GND/LVDS/Strap
Date: Friday, October 17, 2014 Sheet 15 of 43
U4000D
PCIE_VDDR : 1.8V @ 100mA
MEM I/O AM30
PCIE_PVDD
PCIE
+1.8V_VGA
1.35V ( DDR3, MVDDQ = 1.35V@2A)
+1.35V_VGA H13 AB23
H16 VDDR1#1 NC#AB23 AC23 C4035 C4036
H19 VDDR1#2 NC#AC23 AD24 1U/10V_4 10U/6.3VS_6
C4037 C4038 C4039 C4040 C4041 C4042 J10 VDDR1#3 NC#AD24 AE24
10U/6.3VS_6 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 J23 VDDR1#4 NC#AE24 AE25
J24 VDDR1#5 NC#AE25 AE26
J9 VDDR1#6 NC#AE26 AF25
K10 VDDR1#7 NC#AF25 AG26
K23 VDDR1#8 NC#AG26
K24 VDDR1#9
K9 VDDR1#10 L23
C4033 C4034 L11 VDDR1#11 PCIE_VDDC#1 L24 +1.0V_VGA
0.1U/10V_4 0.01U/25V_4 L12 VDDR1#12 PCIE_VDDC#2 L25
VDDR1#13 PCIE_VDDC#3 PCIE_VDDC : 0.95V @ 2.5A (GEN3.0)
L13 L26
L20 VDDR1#14 PCIE_VDDC#4 M22
L21 VDDR1#15 PCIE_VDDC#5 N22
L22 VDDR1#16 PCIE_VDDC#6 N23 C4043 C4044 C4045 C4046 C4047 C4048 C4049
VDDR1#17 PCIE_VDDC#7 N24 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_6
PCIE_VDDC#8 R22
PCIE_VDDC#9 T22
LEVEL PCIE_VDDC#10 U22
+1.8V_VGA TRANSLATION PCIE_VDDC#11 V22
PCIE_VDDC#12 TDP=25W/TDC=36A/EDC=TDCx1.5=54A(1ms)/EDP=35W(sustained)/Peak=53W(1ms)
AA20 VDDC+VDDCI +VGA_CORE
AA21 VDD_CT#1
VDD_GPIO18 @13mA VDD_CT#2
0.85~1.1V(36A peak )( Ripple < 87.2mV)
AB20 AA15
AB21 VDD_CT#3 CORE VDDC#1 N15
C4058 VDD_CT#4 VDDC#2 N17
1U/10V_4 +3V_VGA VDDC#3 R13 C4050 C4051 C4052 C4053 C4054 C4055 C4056 C4057
VDDC#4
I/O R16 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4

POWER
AA17 VDDC#5 R18
VDD_GPIO33@25mA VDDR3#1 VDDC#6
AA18 Y21
AB17 VDDR3#2 VDDC#7 T12
AB18 VDDR3#3 VDDC#8 T15
C4059 VDDR3#4 VDDC#9 T17
1U/10V_4 V12 VDDC#10 T20
Y12 NC_VDDR4#1 VDDC#11 U13 C4060 C4061 C4062 C4063 C4064 C4065 C4066 C4067
U12 NC_VDDR4#2 VDDC#12 U16 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4 2.2U/6.3V_4
NC_VDDR4#3 VDDC#13 U18
VDDC#14 V21
VDDC#15 V15
VDDC#16 V17
VDDC#17 V20
VDDC#18 Y13
Memory Phase Lock Loop Power : VDDC#20

1
1.8V @ 90mA Y16
VDDC#21 Y18 +
L4001 BLM18PG181SN1D(180,1.5A)_6\S MPV18 VDDC#22 AA12 C4068 C4069 C4070 C4071 C4072 C4073 C4074
+1.8V_VGA VDDC#23 M11 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 330U_2.5V_3528
VDDC#24

2
N12
C4075 C4076 C4077 VDDC#25 U11
1U/10V_4 10U/6.3VS_6 10U/6.3VS_6 VDDC#26 AB11
VDDC/VARY_BL AB12
VDDC/DIGON AB13
VDDC/GENERICA W9
PLL VDDC/GENERICC AC11
Engine Phase Lock Loop Power : VDDC/DDC2CLK
analog power pin for engine PLL AC13
VDDC/DDC2DATA AC14
1.8V @ 75mA VDDC/HPD1 U10
L4002 HCB1608KF-121T30(120+-25%,3A) SPV18 MPV18 L8 VDDC/GPIO_1 T10
+1.8V_VGA MPLL_PVDD VDDC/GPIO_2 W10
VDDC/GPIO_18 Y9
C4078 C4079 VDDC/GPIO_14_HPD2
1U/10V_4 10U/6.3VS_6 R21 0.95V~1.1V(0.8A)
SPV18 H7 BIF_VDDC_1 U21
SPLL_PVDD BIF_VDDC_2 +1.0V_VGA
Engine Phase Lock Loop Power :
digital power pin for engine PLL M13 0.95V~1.1V(5A VDDCI)
ISOLATED VDDCI#1 M15
0.95V @ 100mA CORE I/O VDDCI#2 +VGA_CORE
M16
L4003 HCB1608KF-121T30(120+-25%,3A) +1.0V_VGA_SPV10 H8 VDDCI#3 M17
+1.0V_VGA SPLL_VDDC VDDCI#4 M18 C4080 C4081 C4082 C4083 C4084 C4085 C4086
VDDCI#5 M20 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3VS_610U/6.3VS_6
C4087 C4088 J7 VDDCI#6 M21
1U/10V_4 SPLL_PVSS VDDCI#7 N20
0.1U/10V_4 VDDCI#8
W1 R4055 *0_4 +VGA_CORE
NC#W1/FB_VDDCI W3 R4056 *0_4
NC#W3/FB_VSS
AC20 R4057 0_4
NC#FB_VDDC VGPU_CORE_SENSE 41
AD20 R4058 0_4
NC#FB_VSS VSS_GPU_SENSE 41
Meso_S3

+1.35V_VGA 17,18,40,41
+1.8V_VGA 13,14,40,41,43
+1.0V_VGA 13,40,43
+VGA_CORE 40,41,42

PROJECT : Y23
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 TOPAZ S3 Power
Date: Friday, October 17, 2014 Sheet 16 of 43
U4000C
VMA_ODT0
18 VMA_ODT0 VMA_ODT1
18 VMA_ODT1 VMA_DQ0 VMA_MA0
K27 K17
VMA_RAS0# VMA_DQ1 J29 DQA0_0 MAA0_0 J20 VMA_MA1
18 VMA_RAS0# VMA_RAS1# VMA_DQ2 DQA0_1 MAA0_1 VMA_MA2
18 VMA_RAS1# H30 H23
VMA_DQ3 H32 DQA0_2 MAA0_2 G23 VMA_MA3
VMA_CAS0# VMA_DQ4 G29 DQA0_3 MAA0_3 G24 VMA_MA4
18 VMA_CAS0# VMA_CAS1# VMA_DQ5 DQA0_4 MAA0_4 VMA_MA5
18 VMA_CAS1# F28 H24
DQA0_5 MAA0_5

From GPU
VMA_DQ6 F32 J19 VMA_MA6
VMA_WE0# VMA_DQ7 F30 DQA0_6 MAA0_6 K19 VMA_MA7
18 VMA_WE0# VMA_WE1# VMA_DQ8 DQA0_7 MAA0_7 VMA_MA13
18 VMA_WE1# C30 G20 25mm (max) 5mm (max) 25mm (max)
VMA_DQ9 F27 DQA0_8 MAA0_8 L17 VMA_MA15
VMA_CSA0#_0 VMA_DQ10 A28 DQA0_9 MAA0_9
18 VMA_CSA0#_0 VMA_DQ11 DQA0_10 VMA_MA8 DRAM_RST_C

MEMORY INTERFACE
C28 J14 R4059 10/F_4 DRAM_RST_M 18
VMA_CSA1#_0 VMA_DQ12 E27 DQA0_11 MAA1_0 K14 VMA_MA9 R4060 51_4
18 VMA_CSA1#_0 VMA_DQ13 DQA0_12 MAA1_1 VMA_MA10
G26 J11
VMA_CKE0 VMA_DQ14 D26 DQA0_13 MAA1_2 J13 VMA_MA11
18 VMA_CKE0 VMA_CKE1 VMA_DQ15 DQA0_14 MAA1_3 VMA_MA12
18 VMA_CKE1 F25 H11 R4061 C4089
VMA_DQ16 A25 DQA0_15 MAA1_4 G11 VMA_BA2
VMA_CLK0 VMA_DQ17 C25 DQA0_16 MAA1_5 J16 VMA_BA0 4.99K/F_4 120P/50V_4
18 VMA_CLK0 VMA_CLK0# VMA_DQ18 DQA0_17 MAA1_6 VMA_BA1
18 VMA_CLK0# E25 L15
VMA_DQ19 D24 DQA0_18 MAA1_7 G14 VMA_MA14
VMA_CLK1 VMA_DQ20 E23 DQA0_19 MMA1_8 L16
18 VMA_CLK1 VMA_CLK1# VMA_DQ21 DQA0_20 MAA1_9
18 VMA_CLK1# F23
VMA_DQ22 D22 DQA0_21 E32 VMA_DM0
VMA_WDQS[7..0] VMA_DQ23 F21 DQA0_22 WCKA0_0 E30 VMA_DM1
18 VMA_WDQS[7..0] VMA_DQ24 DQA0_23 WCKA0B_0 VMA_DM2
E21 A21
VMA_RDQS[7..0] VMA_DQ25 DQA0_24 WCKA0_1 VMA_DM3
18 VMA_RDQS[7..0] VMA_DQ26
D20
DQA0_25 WCKA0B_1
C21
VMA_DM4
Place all these components very close to GPU (Within
F19 E13
VMA_DM[7..0] VMA_DQ27 A19 DQA0_26 WCKA1_0 D12 VMA_DM5 25mm) and keep all component close to each Other (within
18 VMA_DM[7..0] VMA_DQ28 D18 DQA0_27 WCKA1B_0 E3 VMA_DM6 5mm) except Rser2
VMA_DQ[63..0] VMA_DQ29 F17 DQA0_28 WCKA1_1 F4 VMA_DM7
18 VMA_DQ[63..0] VMA_DQ30 DQA0_29 WCKA1B_1
A17 This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
VMA_MA[15..0] VMA_DQ31 C17 DQA0_30 H28 VMA_RDQS0
18 VMA_MA[15..0] DQA0_31 EDCA0_0
Capacitors and Resistor values are an example only. The Series R and
VMA_DQ32 E17 C27 VMA_RDQS1 || Cap values will depend on the DRAM load and will have to be
VMA_DQ33 D16 DQA1_0 EDCA0_1 A23 VMA_RDQS2
VMA_BA0 VMA_DQ34 DQA1_1 EDCA0_2 VMA_RDQS3
calculated for different Memory ,DRAM Load and board to pass Reset
18 VMA_BA0 F15 E19 Signal Spec.
VMA_BA1 VMA_DQ35 A15 DQA1_2 EDCA0_3 E15 VMA_RDQS4
18 VMA_BA1 VMA_BA2 VMA_DQ36 DQA1_3 EDCA1_0 VMA_RDQS5
D14 D10
18 VMA_BA2 VMA_DQ37 DQA1_4 EDCA1_1 VMA_RDQS6
F13 D6
VMA_DQ38 A13 DQA1_5 EDCA1_2 G5 VMA_RDQS7
VMA_DQ39 DQA1_6 EDCA1_3
support 1Gbit C13
VMA_DQ40 E11 DQA1_7 H27 VMA_WDQS0
VRAM ( 64M X 16 ) DQA1_8 DDBIA0_0
VMA_DQ41 A11 A27 VMA_WDQS1
VMA_DQ42 C11 DQA1_9 DDBIA0_1 C23 VMA_WDQS2
VMA_DQ43 F11 DQA1_10 DDBIA0_2 C19 VMA_WDQS3
VMA_DQ44 A9 DQA1_11 DDBIA0_3 C15 VMA_WDQS4
VMA_DQ45 C9 DQA1_12 DDBIA1_0 E9 VMA_WDQS5
VMA_DQ46 F9 DQA1_13 DDBIA1_1 C5 VMA_WDQS6
VMA_DQ47 D8 DQA1_14 DDBIA1_2 H4 VMA_WDQS7
VMA_DQ48 E7 DQA1_15 DDBIA1_3
VMA_DQ49 A7 DQA1_16 L18 VMA_ODT0
VMA_DQ50 C7 DQA1_17 ADBIAO K16 VMA_ODT1
VMA_DQ51 F7 DQA1_18 ADBIA1
VMA_DQ52 A5 DQA1_19 H26 VMA_CLK0
VMA_DQ53 E5 DQA1_20 CLKA0 H25 VMA_CLK0#
VMA_DQ54 C3 DQA1_21 CLKA0B
VMA_DQ55 E1 DQA1_22 G9 VMA_CLK1
VMA_DQ56 G7 DQA1_23 CLKA1 H9 VMA_CLK1#
+1.35V_VGA VMA_DQ57 G6 DQA1_24 CLKA1B
VMA_DQ58 G1 DQA1_25 G22 VMA_RAS0#
VMA_DQ59 G3 DQA1_26 RASA0B G17 VMA_RAS1#
VMA_DQ60 J6 DQA1_27 RASA1B
R4064 VMA_DQ61 J1 DQA1_28 G19 VMA_CAS0#
VMA_DQ62 J3 DQA1_29 CASA0B G16 VMA_CAS1#
40.2/F_4 VMA_DQ63 J5 DQA1_30 CASA1B
DQA1_31 H22 VMA_CSA0#_0
MVREFD K26 CSA0B_0 J22
J26 MVREFDA CSA0B_1
+1.35V_VGA MVREFSA G13 VMA_CSA1#_0
J25 CSA1B_0 K13
C4090 R4066 Rd R4067 120/F_4 K25 NC CSA1B_1
MEM_CALRP0 K20 VMA_CKE0
1U/10V_4 100/F_4 R4068 CKEA0 J17 VMA_CKE1
CKEA1
40.2/F_4 G25 VMA_WE0#
DRAM_RST_C L10 WEA0B H10 VMA_WE1#
MVREFS DRAM_RST WEA1B
CLKTESTA K8
CLKTESTB L7 CLKTESTA
CLKTESTB
C4091 R4070
Meso_S3
1U/10V_4 100/F_4
C4092 C4093
*0.1U/10V_4 *0.1U/10V_4

R4071 R4072
*51.1/F_4 *51.1/F_4

+1.35V_VGA 16,18,40,41 route 50ohms


single-ended/100ohms diff
and keep short
PROJECT : Y23
Quanta Computer Inc.
Size Document Number Rev
1A
NB5 TPOAZ_S3_MEM_Interface
Date: Friday, October 17, 2014 Sheet 17 o f 43
5 4 3 2 1

VMA_MA[15..0]

1G/2G DDR3L
17 VMA_MA[15..0] 17 VMA_DQ[63..0]
17 VMA_DM[7..0] 17 VMA_WDQS[7..0]
17 VMA_RDQS[7..0]
U4003 U4004 U4005 U4006
VREFC_VMA1 M8 E3 VMA_DQ19 VREFC_VMA2 M8 E3 VMA_DQ7 VREFC_VMA3 M8 E3 VMA_DQ60 VREFC_VMA4 M8 E3 VMA_DQ53
VREFD_VMA1 H1 VREFCA DQL0 F7 VMA_DQ18 VREFD_VMA2 H1 VREFCA DQL0 F7 VMA_DQ5 VREFD_VMA3 H1 VREFCA DQL0 F7 VMA_DQ58 VREFD_VMA4 H1 VREFCA DQL0 F7 VMA_DQ54
VREFDQ DQL1 F2 VMA_DQ23 VREFDQ DQL1 F2 VMA_DQ3 VREFDQ DQL1 F2 VMA_DQ62 VREFDQ DQL1 F2 VMA_DQ49
VMA_MA0 N3 DQL2 F8 VMA_DQ17 VMA_MA0 N3 DQL2 F8 VMA_DQ2 VMA_MA0 N3 DQL2 F8 VMA_DQ57 VMA_MA0 N3 DQL2 F8 VMA_DQ55
VMA_MA1 P7 A0 DQL3 H3 VMA_DQ22 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ6 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ61 VMA_MA1 P7 A0 DQL3 H3 VMA_DQ50
VMA_MA2 P3 A1 DQL4 H8 VMA_DQ20 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ0 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ56 VMA_MA2 P3 A1 DQL4 H8 VMA_DQ51
VMA_MA3 N2 A2 DQL5 G2 VMA_DQ21 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ4 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ63 VMA_MA3 N2 A2 DQL5 G2 VMA_DQ48
VMA_MA4 P8 A3 DQL6 H7 VMA_DQ16 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ1 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ59 VMA_MA4 P8 A3 DQL6 H7 VMA_DQ52
VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7 VMA_MA5 P2 A4 DQL7
D VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5 VMA_MA6 R8 A5 D
VMA_MA7 R2 A6 D7 VMA_DQ11 VMA_MA7 R2 A6 D7 VMA_DQ28 VMA_MA7 R2 A6 D7 VMA_DQ43 VMA_MA7 R2 A6 D7 VMA_DQ37
VMA_MA8 T8 A7 DQU0 C3 VMA_DQ14 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ29 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ46 VMA_MA8 T8 A7 DQU0 C3 VMA_DQ32
VMA_MA9 R3 A8 DQU1 C8 VMA_DQ9 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ30 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ40 VMA_MA9 R3 A8 DQU1 C8 VMA_DQ38
VMA_MA10 L7 A9 DQU2 C2 VMA_DQ13 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ24 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ47 VMA_MA10 L7 A9 DQU2 C2 VMA_DQ33
VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ10 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ27 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ41 VMA_MA11 R7 A10/AP DQU3 A7 VMA_DQ36
VMA_MA12 N7 A11 DQU4 A2 VMA_DQ15 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ26 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ45 VMA_MA12 N7 A11 DQU4 A2 VMA_DQ34
VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ8 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ31 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ42 VMA_MA13 T3 A12/BC DQU5 B8 VMA_DQ39
VMA_MA14 T7 A13 DQU6 A3 VMA_DQ12 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ25 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ44 VMA_MA14 T7 A13 DQU6 A3 VMA_DQ35
VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7 VMA_MA15 M7 A14 DQU7
A15 +1.35V_VGA A15 +1.35V_VGA A15 +1.35V_VGA A15 +1.35V_VGA

M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2 VMA_BA0 M2 B2


17 VMA_BA0 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9 VMA_BA1 N8 BA0 VDD#B2 D9
17 VMA_BA1 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9 VMA_BA2 BA1 VDD#D9
M3 G7 M3 G7 M3 G7 M3 G7
17 VMA_BA2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
J7 VDD#N1 N9 VMA_CLK0 J7 VDD#N1 N9 J7 VDD#N1 N9 VMA_CLK1 J7 VDD#N1 N9
17 VMA_CLK0 CK VDD#N9 VMA_CLK0# CK VDD#N9 17 VMA_CLK1 CK VDD#N9 VMA_CLK1# CK VDD#N9
K7 R1 K7 R1 K7 R1 K7 R1
17 VMA_CLK0# K9 CK VDD#R1 R9 VMA_CKE0 K9 CK VDD#R1 R9 17 VMA_CLK1# K9 CK VDD#R1 R9 VMA_CKE1 K9 CK VDD#R1 R9
17 VMA_CKE0 CKE VDD#R9 +1.35V_VGA CKE VDD#R9 +1.35V_VGA 17 VMA_CKE1 CKE VDD#R9 +1.35V_VGA CKE VDD#R9 +1.35V_VGA

K1 A1 VMA_ODT0 K1 A1 K1 A1 VMA_ODT1 K1 A1
17 VMA_ODT0 ODT VDDQ#A1 VMA_CSA0#_0 ODT VDDQ#A1 17 VMA_ODT1 ODT VDDQ#A1 VMA_CSA1#_0 ODT VDDQ#A1
L2 A8 L2 A8 L2 A8 L2 A8
17 VMA_CSA0#_0 J3 CS VDDQ#A8 C1 VMA_RAS0# J3 CS VDDQ#A8 C1 17 VMA_CSA1#_0 J3 CS VDDQ#A8 C1 VMA_RAS1# J3 CS VDDQ#A8 C1
17 VMA_RAS0# RAS VDDQ#C1 VMA_CAS0# RAS VDDQ#C1 17 VMA_RAS1# RAS VDDQ#C1 VMA_CAS1# RAS VDDQ#C1
K3 C9 K3 C9 K3 C9 K3 C9
17 VMA_CAS0# CAS VDDQ#C9 VMA_WE0# CAS VDDQ#C9 17 VMA_CAS1# CAS VDDQ#C9 VMA_WE1# CAS VDDQ#C9
L3 D2 L3 D2 L3 D2 L3 D2
17 VMA_WE0# WE VDDQ#D2 WE VDDQ#D2 17 VMA_WE1# WE VDDQ#D2 WE VDDQ#D2
E9 E9 E9 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
VMA_RDQS2 F3 VDDQ#F1 H2 VMA_RDQS0 F3 VDDQ#F1 H2 VMA_RDQS7 F3 VDDQ#F1 H2 VMA_RDQS6 F3 VDDQ#F1 H2
VMA_WDQS2 G3 DQSL VDDQ#H2 H9 VMA_WDQS0 G3 DQSL VDDQ#H2 H9 VMA_WDQS7 G3 DQSL VDDQ#H2 H9 VMA_WDQS6 G3 DQSL VDDQ#H2 H9
C DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 DQSL VDDQ#H9 C

VMA_DM2 E7 A9 VMA_DM0 E7 A9 VMA_DM7 E7 A9 VMA_DM6 E7 A9


VMA_DM1 D3 DML VSS#A9 B3 VMA_DM3 D3 DML VSS#A9 B3 VMA_DM5 D3 DML VSS#A9 B3 VMA_DM4 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
VMA_RDQS1 C7 VSS#G8 J2 VMA_RDQS3 C7 VSS#G8 J2 VMA_RDQS5 C7 VSS#G8 J2 VMA_RDQS4 C7 VSS#G8 J2
VMA_WDQS1 B7 DQSU VSS#J2 J8 VMA_WDQS3 B7 DQSU VSS#J2 J8 VMA_WDQS5 B7 DQSU VSS#J2 J8 VMA_WDQS4 B7 DQSU VSS#J2 J8
DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1 DQSU VSS#J8 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9 DRAM_RST_M T2 VSS#P1 P9
17 DRAM_RST_M RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
VMA_ZQ1 L8 VSS#T1 T9 VMA_ZQ2 L8 VSS#T1 T9 VMA_ZQ3 L8 VSS#T1 T9 VMA_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9
Should be 240 Should be 240 Should be 240 Should be 240
Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1 Ohms +-1% B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R4077 VSSQ#B9 D1 R4078 VSSQ#B9 D1 R4079 VSSQ#B9 D1 R4080 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
243/F_4 VSSQ#D8 243/F_4 VSSQ#D8 243/F_4 VSSQ#D8 243/F_4 VSSQ#D8
E2 E2 E2 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 INT SDRAM DDR3 SDRAM DDR3
K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A

+1.35V_VGA +1.35V_VGA +1.35V_VGA +1.35V_VGA +1.35V_VGA +1.35V_VGA +1.35V_VGA +1.35V_VGA


B B

R4085 R4086 R4087 R4088 R4089 R4090 R4091 R4092


4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4 4.99K/F_4

VREFC_VMA1 VREFD_VMA1 VREFC_VMA2 VREFD_VMA2 VREFC_VMA3 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4

R4093 R4094 R4095 R4096 R4097 R4098 R4099 R4100


4.99K/F_4 C4094 4.99K/F_4 C4095 4.99K/F_4 C4096 4.99K/F_4 C4097 4.99K/F_4 C4098 4.99K/F_4 C4099 4.99K/F_4 C4100 4.99K/F_4 C4101
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
+1.35V_VGA 16,17,40,41

VMA_CLK0 +1.35V_VGA +1.35V_VGA

R4101

40.2/F_4 C4102 C4103 C4104 C4105 C4106 C4107 C4108 C4109 C4110 C4111 C4112 C4113 C4114 C4115 C4116 C4117
C4118
VMA_CLK0_COMM
1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 1U/6.3V_4 QBCON PN TOP BSQ

R4102 0.01U/25V_4 +1.35V_VGA +1.35V_VGA


Hynix 2G AKD5PZDTW02 AKD5PZDTW01
40.2/F_4 Micron 2G AKD5PZSTL01 AKD5PZSTL00
VMA_CLK0#
VMA_CLK1 9/4: Dual Rank : 80.6 ohm
A
Single Rank : 40.2 ohm
C4119
1U/6.3V_4
C4120
1U/6.3V_4
C4121
1U/6.3V_4
C4122
1U/6.3V_4
C4123
1U/6.3V_4
C4124
1U/6.3V_4
C4125
1U/6.3V_4
C4126
1U/6.3V_4
C4127
1U/6.3V_4
C4128
1U/6.3V_4
C4129
1U/6.3V_4
C4130
1U/6.3V_4
C4131
1U/6.3V_4
C4132
1U/6.3V_4
C4133
1U/6.3V_4
C4134
1U/6.3V_4
SAMSUNG 2G AKD5PGDT501 AKD5PGDT500 A

R4103

40.2/F_4 +1.35V_VGA +1.35V_VGA


C4135

PROJECT : Y23
VMA_CLK1_COMM

R4104 0.01U/25V_4 C4136 C4137 C4138 C4139 C4140 C4141 C4142 C4143 C4144 C4145 C4146 C4147
Quanta Computer Inc.
10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6 10U/6.3VS_6
40.2/F_4 Size Document Number Rev
Custom
Sun S3 VRAM(DDR3 BGA96P) 1A
VMA_CLK1#
NB5 Date: Friday, October 17, 2014 Sheet 18 of 43
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

PROJECT : Y23
Quanta Computer Inc.
Size Document Number Rev
Custom
Sun S3 VRAM(DDR3 BGA96P) 1A
NB5 Date: Friday, October 17, 2014 Sheet 19 of 43
5 4 3 2 1
5 4 3 2 1

14” & 15” only eDP panel SKU , 17” have both LVDS & eDP SKU
+TRAVIS3.3V_A +3V +3V

+TRAVIS1.2V
Pine 18: keep 80 Mile Trace
+TRAVIS3.3V
EC6001 EC6000
RTD2136 Dual Channel only *0.1U/10V_4 *0.1U/10V_4 keep 80 Mile Trace
+3V +TRAVIS3.3V +TRAVIS3.3V
SCA_SCL_CFG1 Pine 15/17: keep 20 Mile Trace
+3V R6004 *4.7K_4 L6001 CLOSE TO Pin22
+SWR_LX
D SCA_SDA_CFG0 reserve for EMI D
R6005 *4.7K_4 *PBY160808T-600Y-N(60,3A)
USING 60R 1A C6009 C6010 C6011 C6004 C6005

R6006 R6007 *10U/6.3VS_6 *0.1U/10V_4 *0.1U/10V_4 *22U/6.3VS_6


R6001 *100k/F_4 *0.1U/10V_4

17

15
43

18
11

22
U6000

PVCC
VCCK

DP_V33
SWR_LX

DP_V12

SWR_VDD
SWR_VCCK
*4.7K_4 *4.7K_4 EDP_HPD_2136 42 TXOOUT0-_2136 Close to Pin18
TXO0- 41 TXOOUT0+_2136
TXO0+
within 200-mil
TXOOUT1-_2136
Reserve 1
DP_HPD TXO1-
40
TXOOUT1+_2136
2 39
eDP_AUXN_2136 3 TESTMODE TXO1+ 38 TXOOUT2-_2136
eDP_AUXP_2136 4 AUX-CH_N TXO2- 37 TXOOUT2+_2136
AUX-CH_P TXO2+ 36 TXOCLKOUT- +3V +TRAVIS3.3V_A Close to Pin5
LANE0P 7 TXOC- 35 TXOCLKOUT+ L6002
LANE0N 8 LANE0P TXOC+ 34
LANE1P 9 LANE0N TXO3- 33 *PBY160808T-600Y-N(60,3A)
LANE1N 10 LANE1P TXO3+ 32 C6007 C6008
*0_4 R6010 SMB_RUN_CLK 5,11,12 APU(use this for LVDS) LANE1N TXE0-
TXE0+
31 TXEOUT0-
TXEOUT0+
21
21
C6006
SCL1_2136
RTD2136N TXE1-
30
TXEOUT1- 21
*10U/6.3VS_6 *0.1U/10V_4 *0.1U/10V_4
13 29
SDA1_2136 14 CIICSCL1 TXE1+ 28 TXEOUT1+ 21
SCL1_2136 MBCLK2 4,12,30 CIICSDA1 TXE2- 27 TXEOUT2- 21
R6011 *0_4
EDIDDATA_2136 TXE2+ TXEOUT2+ 21
45 26
MIICSDA1 TXEC- TXECLKOUT- 21
SDA1_2136
EC SMBUS EDIDCLK_2136
SCA_SDA_CFG0
46
47 MIICSCL1 TXEC+
25
24 TXECLKOUT+ 21
R6012 *0_4

PANEL_VCC
MBDATA2 4,12,30 SCA_SCL_CFG1 48 MIICSDA0 TXE3- 23

DP_REXT

PWMOUT
MIICSCL0 TXE3+

DP_GND

PWMIN
44 LVDS_BLON_2136
LVDS_BLON_2136 21

GND
*0_4 R6013 49 BL_EN
C SMB_RUN_DAT 5,11,12 APU(use this for LVDS) GND +SWR_LX L6000 +TRAVIS1.2V C
*4.7UH20%,0.76A,LVF303010-4R7M-N Close to Pin11

12

20
16

19

21
IC 底底底 底底底底
底底 底 GND VI A * 9
Pine 20: keep 80 Mile Trace C6000
C6001 C6002 C6003
R6000 DISP_ON_2136 R6008 *0_8 *0.1U/10V_4
DPST_PWM_2136 DISP_ON_2136 21
*10U/6.3VS_6 *0.1U/10V_4 *0.1U/10V_4
DPST_PWM_2136 21
R6052 0_4
APU_DPST_PWM 4
*12K/F_4
EDP_HPD R6002 *1K/F_4EDP_HPD_2136 Close to Pin17 Close to Pin43
4,21 EDP_HPD DPST_PWM 21
R6009
*100K/F_4 SWR: Stuff L6000
R6000 use 1% LDO: Stuff R6008 (default pop this)
R7048
100K/F_4
L6000: need use CV-4709MN00 for Vendor suggestion
2nd CV-4708MN03

INT_eDP_TXP0 C6026 *0.1U/10V_4 LANE0P TXOOUT0+_2136 R6042 *0_4


4 INT_eDP_TXP0 TXLOUT0+ 21
INT_eDP_TXN0 C6029 *0.1U/10V_4 LANE0N To 2136 TXOOUT0-_2136 R6044 *0_4
4 INT_eDP_TXN0 TXLOUT0- 21
R6036 0_4 eDP_TXP0 eDP_TXP1 C6034 0.1U/10V_4
B B
From CPU eDP_TXN0 eDP_TXN1
R6035 0_4 C6033 0.1U/10V_4
Close to LVDS CONN
INT_eDP_TXP1 C6024 *0.1U/10V_4 LANE1P TXOOUT1+_2136 R6039 *0_4
4 INT_eDP_TXP1 TXLOUT1+ 21
INT_eDP_TXN1 C6025 *0.1U/10V_4 LANE1N To 2136 TXOOUT1-_2136 R6040 *0_4
4 INT_eDP_TXN1 TXLOUT1- 21
R6032 0_4 eDP_TXP1 eDP_TXP0 C6031 0.1U/10V_4

R6031 0_4 eDP_TXN1 eDP_TXN0 C6030 0.1U/10V_4

TXOOUT2+_2136 R6048 *0_4 TXLOUT2+_R 21


TXOOUT2-_2136 R6049 *0_4
TXLOUT2-_R 21

For EDP Only: stuf f Resi st or


For LVDS only stuf f Cap
TXOCLKOUT+ R6050 *0_4
TXLCLKOUT+_R 21
TXOCLKOUT- R6051 *0_4
TXLCLKOUT-_R 21

R6034 *1M/F_4
A A
INT_eDP_AUXN C6027 *0.1U/10V_4 eDP_AUXN_2136 EDIDDATA_2136 R6043 *0_4
4 INT_eDP_AUXN EDIDDATA_R 21 4,5,6,7,11,12,21,22,23,24,27,28,29,30,36,38,40 +3V
INT_eDP_AUXP C6028 *0.1U/10V_4 eDP_AUXP_2136 To 2136 EDIDCLK_2136 R6041 *0_4
4 INT_eDP_AUXP EDIDCLK_R 21
R6037 *1M/F_4 R6033 0_4 eDP_AUXN eDP_AUXN C6035 0.1U/10V_4
+3V
R6038 0_4 eDP_AUXP eDP_AUXP C6032 0.1U/10V_4
PROJECT : X21
Quanta Computer Inc.
For EDP Only: stuf f Cap Size Document Number Rev
For LVDS only stuf f Resi st or NB5
Custom LVDS converter RTD2136 1A

Date: Friday, October 17, 2014 Sheet 20 of 43


5 4 3 2 1
1 2 3 4 5 6 7 8

For LVDS
LVDS conn. +3V

14” & 15” onlyeDP panel S KU , 17” have bot LVDS


h & eDPSKU +3V
+3V_CAM R47
R48
*4.7K_4
*4.7K_4
EDIDCLK_R
EDIDDATA_R

C648 22P/50V_4

30 EMU_LID R66 0_4 PN_BLON BLON_CON C546 C641


C651
*10P/50V_4
C652
*10P/50V_4
RF
D6 RB500V-40 R67 100K/F_4 *0.01U/50V_4 *4.7U/6.3V_4

LVDS_BLON1 R58 1K/F_4


A
+3VLCD_CON A
CN2
R61 TXLOUT0+

*0.047U/10V_4

*0.047U/10V_4
20 TXLOUT0+

G_1
100K/F_4 TXLOUT0-
20 TXLOUT0- 40
TXLOUT1+ R51 0_6 39
20 TXLOUT1+ +3V EDIDCLK_R 38
20 TXLOUT1- TXLOUT1-
EDIDDATA_R 37

2
C640
TXLOUT2+_R TXLOUT0- 36
20 TXLOUT2+_R TXLOUT2-_R 35
1000P/50V_4TXLOUT0+

C646

C647
20 TXLOUT2-_R 34

1
TXLCLKOUT+_R TXLOUT1- 33
20 TXLCLKOUT+_R TXLCLKOUT-_R 32
20 TXLCLKOUT-_R TXLOUT1+
31
+3VLCD_CON EDIDDATA_R TXLOUT2-_R 30
For LVDS Only 20 EDIDDATA_R EDIDCLK_R TXLOUT2+_R 29

20 DISP_ON_2136 R70 *0_8 80 mile trace 20 EDIDCLK_R 28


TXLCLKOUT-_R 27
TXLCLKOUT+_R 26
25
R519 C650 TXEOUT0- 24
*100K/F_4 *4.7U/6.3V_4 TXEOUT0+ 23
TXEOUT0- 22
20 TXEOUT0- 21
20 TXEOUT0+ TXEOUT0+ TXEOUT1-
TXEOUT1- TXEOUT1+ 20
20 TXEOUT1-
TXEOUT1+
Rc 19
20 TXEOUT1+
TXEOUT2-
For LVDS Only: Stuf f Rc R2 *0_4
18
20 TXEOUT2-
TXEOUT2+
For EDP Only: Stuf f Rd R1 0_4 EDP_HPD_R
TXEOUT2-
TXEOUT2+ 17
20 TXEOUT2+ 4,20 EDP_HPD 16
For EDP Only +3V 20
20
TXECLKOUT-
TXECLKOUT+
TXECLKOUT-
TXECLKOUT+ Rd TXECLKOUT- 15
B C654 U1 +3VLCD_CON TXECLKOUT+ 14 B
1U/6.3V_4 13
5 1 L11 0_6 +3V_CAM 12
IN OUT USBP4-_R 11
4 2 USBP4+_R 10
IN GND 9
1

1
DISP_ON 3 C649 C653 C645 L3 FCM1005KF-301T03 DIGITAL_CLK_L 8
ON/OFF 23 DIGITAL_CLK DIGITAL_D1_R 7
0.01U/50V_4 0.1U/10V_4 10U/6.3V_6 23 DIGITAL_D1 L2 FCM1005KF-301T03
6
2

2 VADJ1
R63 IC(5P) G5243AT11U BLON_CON 5
100K/F_4 C642 C643 4
3
AL005243001 GMT:G5243AT11U
AL002821000 BCD:AP2821KTR-G1 For EDP Only(DG show AUX don't require PU/D) *10P/50V_4 *10P/50V_4 +VIN_BLIGHT 2
1

G_0
+3V
DFFC40FR064
R35 *100K_4 EDIDDATA_R lvds-50671-04041-001-40p-l
R34 *100K_4 EDIDCLK_R 51519-04041-001

BRIGHT R22 1K/F_4 VADJ1

+3V
R23 C644
100K/F_4 22P/50V_4 R74 *1K_4 BRIGHT
R59 *1K_4 LVDS_BLON1 1 2 USBP4+_R
6 USBP4+ USBP4-_R
4 3
6 USBP4-
L5
For LVDS Only *MCM2012B900GBE

C C
R73 *0_4 BRIGHT USBP4- R7093 0_4 USBP4-_R
+VIN_BLIGHT 20 DPST_PWM_2136 USBP4+_R
USBP4+ R7094 0_4
R64 *0_4 LVDS_BLON1
20 LVDS_BLON_2136

L4 0_8 +VIN_BLIGHT
+VIN

For EDP Only


C660 C637 0.1U/25V_4
0.1U/25V_4 R38 10/F_4 BRIGHT
20 DPST_PWM
C638 0.01U/50V_4
R60 0_4 LVDS_BLON1
4 APU_LVDS_BLON
C639 *4.7U/25V_8
R85 0_4 DISP_ON
4 APU_DISP_ON

4,5,6,7,11,12,20,22,23,24,27,28,29,30,36,38,40 +3V
25,27,31,32,33,35,37,39,40,41,42 +VIN

D D

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
LCD CONN/Camera/D-MIC
NB5 Date: Friday, October 17, 2014 Sheet 21 of 43
1 2 3 4 5 6 7 8
5 4 3 2 1

HDMI Conn.

HDMI SMBus Isolat i on +3V


CN12
D 22 D
SHELL3 20
IN_D2 1 SHELL1
Q9 4 IN_D2 D2+
R213 2.2K_4 2
+3V IN_D2# D2 Shield
5 3
4 IN_D2# IN_D1 D2-
4
HDMI_SCLK IN_D2 IN_D2# 4 IN_D1 D1+
4 3 R269 120/F_4 5
4 INT_HDMI_AUXP IN_D1# D1 Shield
6
IN_D1 IN_D1# 4 IN_D1# IN_D0 D1-
R255 120/F_4 7
4 IN_D0 D0+
2 8
IN_D0 R261 120/F_4 IN_D0# IN_D0# 9 D0 Shield
HDMI_SDATA 4 IN_D0# IN_CLK D0-
1 6 10
4 INT_HDMI_AUXN IN_CLK IN_CLK# 4 IN_CLK CK+
R230 120/F_4 11
D5 IN_CLK# 12 CK Shield
+3V 4 IN_CLK# CK-
R221 2.2K_4 BAT54AW-L 13
2N7002KDW 2 5V_HSMBCK R581 2.2K_4 14 CE Remote
5V_HSMBDT HDMI_SCLK 15 NC
Close to HDMI connector +5V
3
R193 2.2K_4
HDMI_SDATA 16 DDC CLK
DDC DATA
C254 *10P/50V_4 17
1 C261 *10P/50V_4 18 GND
19 +5V
+5VCRT HP DET 21
+3V SHELL2 23
HDMI_HPD HDMI_DET_C SHELL4
+5V L19 0_6
Check list recommend 604 ohm C249 HDMI CONN_4 pin GND
R191 VC1 DFHD19MR249
DGPU_CL_HDMIP R271 499/F_4 IN_D2 *AVLC 5S_4 hdmi-2he1655-001111f-19p
1K/F_4
R267 499/F_4 IN_D2# R192 +5VCRT 220P/50V_4
100K/F_4
IN_D1 HDMI_HPD_Q
3

C +3V R257 499/F_4 C


IN_D1# 4 HDMI_HPD_Q
R252 499/F_4
IN_D0
40 milsF1 FUSE1A6V_POLY
2 R263 499/F_4 Q7B C259 2 1 +5VCRT
IN_D0# HDMI HPD SENSE +5V +5VCRT

6
R260 499/F_4 0.01U/50V_4
Q10 2 C260 0.1U/10V_4
2N7002K R241 499/F_4 IN_CLK
R228 499/F_4 IN_CLK# SSM14 spec is 40V 1A
1

1
2N7002KDW Q7A

3
R214 1 2 *100K/F_4
Dual HDMI_DET_R HDMI_HPD
for EMI request 4,5,6,7,11,12,20,21,23,24,27,28,29,30,36,38,40 +3V
5 R179 200K_4 4,7,23,27,28,30,31,32 +3VPCU
C268 *0.1U/10V_4 23,24,27,28,40 +5V
21,25,27,31,32,33,35,37,39,40,41,42 +VIN

4
Close to Q10 2N7002KDW
R178
23,28,32,33,34,35,36,38,40,41,43 +5VS5

Dual 100K/F_4
2KV ESD protection

B B

A A

PROJECT : X21
Quanta Computer Inc.
Size Document Number Rev
Custom 1A
LCD Connector (LVDS)
NB5 Date: Friday, October 17, 2014 Sheet 22 of 43
5 4 3 2 1
A B C D E

+5V_AVDD L1001 +5V


Close to PIN1 >40mils trace
1005KF-181T15
22,24,27,28,40 +5V
4,5,6,7,11,12,20,21,22,24,27,28,29,30,36,38,40 +3V

1
1005KF-181T15 C1001 C1002
+3V_DVDD *AZ2015-01H 7,40 +1.5V
+3V L1002 1005KF-181T15 10U/6.3VS_6 0.1U/10V_4
+3V_DVDD-IO C1003

2
+1.5V L1003

C1004 C1005 C1006


Close to PIN26
*1005KF-181T15 C581 need check!
1U/6.3V_4 10U/6.3VS_6 0.1U/10V_4 +3V L1004 AGND EC1001 1000P/50V_4
C1007 C1008 L1000 *HCB1608KF-181T15_6 +3V
0.1U/10V_4 10U/6.3VS_6
+1.5V_AVDD L1005 EC1002 1000P/50V_4
+1.5V
C1009 1005KF-181T15 EC1003 1000P/50V_4
U1001 10U/6.3VS_6
+5V EC1004 1000P/50V_4

TO Digital MIC
C1010 10P/50V_4
PV modify to short pad
1
DVDD AVDD1
26
40
AGND Close to PIN40 +5V_AVDD
U1000 EC1000 1000P/50V_4
R1020 0_4 DMIC0 2 AVDD2 5 1
21 DIGITAL_D1 GPIO0/ DMIC-DATA Vout Vin
R1002 100/F_4 DMIC_CLK_R 3 25 4
21 DIGITAL_CLK GPIO1 / DMIC-CLK AVSS1 AGND BYP
38 C1011 C1012 C1013 C1014 C1015
AVSS2

Analog
C1016 10P/50V_4 R1019 100K/F_4 *2.2U/6.3V_6 *0.1U/10V_4 2 3 0.1U/10V_4 0.047U/10V_4 1U/6.3V_4 AGND
GND EN
4
DVSS LDO1-CAP
27
39
C1017
C1019
10U/6.3VS_6
10U/6.3VS_6
AGND C1018
*1U/6.3V_4 *TPS793475DBVR Close to CODEC
ACZ_SDOUT_AUDIO 5 LDO2-CAP
5 ACZ_SDOUT_AUDIO SDATA-OUT
HPA01091DBVR place to near U24 or under U24
AGND
R1003 0_4 HD_BCLK 6 28 C1020 0.1U/10V_4 R1004 10K_4 +5V R1016 *0_8/s
5 BIT_CLK_AUDIO BCLK VREF
Close to PIN28 Vset=1.242V
Close to PIN7 10U/6.3VS_6 C1021 7
LDO3-CAP
C1022 2.2U/6.3V_6 AGND
R1005 33_4 HD_SDIN0 8 32 OUT_L
5 ACZ_SDIN0 SDATA-IN HPOUT-L (PORT I) HPOUT_L 24 AGND SHIELD
AGND
33 OUT_R
HPOUT-R (PORT I) HPOUT_R 24 AGND SHIELD
+3V_DVDD-IO 9
DVDD-IO
AGND SHIELD

5 ACZ_SYNC_AUDIO
ACZ_SYNC_AUDIO 10 LINE2-L
24
23 Close to Speaker
SYNC LINE2-R

Digital
5 ACZ_RST#_AUDIO
11
RESETB
Speaker 4 ohm: 40mils
C1023 *0.1U/10V_4 22 INT SPEAKER CONN
AMP_BEEP 12 LINE1-L (PORTC) 21 L_SPK+ L1006 PBY160808T-600Y-N(60,3A) L_SPK+_R
PCBEEP LINE1-R (PORTC) L_SPK- L1007 PBY160808T-600Y-N(60,3A) L_SPK-_R 4
C1024 2.2U/6.3V_6 34 R_SPK- L1008 PBY160808T-600Y-N(60,3A) R_SPK-_R 3
CPVEE 20 R_SPK+ L1009 PBY160808T-600Y-N(60,3A) R_SPK+_R 2
MIC1-R (PORTB) 19 1
CAP- 35 MIC1-L (PORTB) CN1001
C1026 CBN 31
2.2U/6.3V_6 37 MIC1-VREFO-L 30 MUTE_LED_CNTL_L R1022 0_4 C1025 C1027 C1028 C1029
CBP MIC1-VREFO-R MUTE_LED_CNTL 28
CAP+
36 1000P/50V_4 1000P/50V_4
+3V_DVDD CPVDD 18 MIC_R1*4.7U/6.3V_6 C1030 1000P/50V_4 1000P/50V_4
+3V_DVDD MIC2-R (PORTF) MIC_L14.7U/6.3V_4 EXT_MIC_L
17 C1031 R1007 1K/F_4
4.7U/6.3V_4 C1032 MIC2-L (PORTF)
L_SPK+ 42
SPK-L+ 29 VREFOUT_C R1018 2.2K_4 EXT_MIC_L +5V_AVDD
L_SPK- MIC2-VREFO EXT_MIC_L 24

SPDIF-OUT/GPIO2
Close to Pin 34,35,36 43
SPK-L- 16
R_SPK- 44 MONO-OUT C1045
TO Internal Speakers SPK-R- *1U/6.3V_4 R1008
R_SPK+ 45 10K_4

SenseB
SenseA
PVDD1

PVDD2

SPK-R+

JDREF
PDB

AGND C1000 check value C1033


NC

0.1U/10V_4 0.1U/10V_4
ALC3227 x QFN48 AMP_BEEP AMP_BEEP_L R1009 100K/F_4 AMP_BEEP_R2
49

13

14
41

46

47

48

15
+5V_DVDD Q34

3
L1010 +5V_DVDD R509 20K/F_4 3 1 R502 0_4 SENSE_A
+5V
R1010
1005KF-181T15 0.1U/10V_4 C1035 Close to Pin 41 R1011 20K/F_4
2N7002K C1034
0.01U/50V_4
10K_4 2 ACZ_SPKR 5
AGND EXT_MIC_L 2N7002

2
1
10U/6.3VS_6 C1036
SENSE_A_1 R1012 39.2K/F_4 SENSE_A
R327 22K/F_4 Check layout Q1001 1

+5V_DVDD
SENSE_A 24
mount location

1
0.1U/10V_4 C1037
Close to Pin 46 Close to codec C447 R325
4.7U/6.3V_4 22K/F_4 AGND
10U/6.3VS_6 C1038 AGND

PD# AGND CN10 Card LAN 55P