An Efficient SQRT Architecture of Carry Select

Adder Design by Common Boolean Logic.

Ms. S.Manjui, Mr. V. Sornagopae
I
pG Scholar, Department of ECE, 2Assistant Professor,
1,2
Abdul Hakeem College of Engineering and Technology, Melvishram, Vellore.
I
Smanjul102@gmail.com

Ahstract- Carry Select adder (CSLA) is known to be the fastest of the proposed architecture is that which replaces the BEC by
adder among the Conventional adder structures. This work uses Common Boolean Logic.
an efficient Carry select adder by sharing the Common Boolean In this paper, an area-efficient carry select adder by
logic (CLB) term. After a logic simplification, we only need one
sharing the common Boolean logic term is proposed. After
OR gate and one inverter gate for carry and summation
Boolean simplification, it can remove the duplicated adder
operation. Through the multiplexer, we can select the correct
cells in the conventional carry select adder. It generates a
output according to the logic states of the carry in signal. Based
on this modification Square root CSLA (SQRT CSLA) duplicate sum and Carry-out signal by using NOT and OR
architecture have been developed and compared with the regular gate and select value with the help of multiplexer. The
and Modified SQRT CSLA architecture. The Modified CSLA multiplexer is used to select the correct output according to its
architecture has been developed using Binary to Excess -I previous carry-out signal [3].
converter (BEC). This paper proposes an efficient method which This paper is organized as follows; Section IT and
replaces a BEC using common Boolean logic. The result analysis section TIT explains the regular and modified CSLA and detail
shows that the proposed architecture achieves the three folded
structure of BEC respectively. A section IV deals with
advantages in terms of area, delay and power.
Common Boolean Logic (CBL) and section V explain about
the proposed architecture. Comparisons of area, power and
Key word - Carry Select Adder, Area-Efficient, BEC, Boolean
Logic delay Results are analyzed in the section VI. Section VII
concludes.
I .INTRODUCTION
IT. BASIC STRUCTURE OF REGULAR SQRT CSLA.
Addition usually impacts widely the overall
performance of digital systems and an arithmetic function. In The basic square root Carry select adder has a dual
electronic applications adders are most widely used. ripple carry adder with 2: 1 multiplexer the main disadvantage
Applications where these are used are multipliers, DSP to of regular CSLA is the large area due to the multiple pairs of
execute various algorithms like FFT, FIR and ITR. In ripple carry adder. The regular 16-bit Carry select adder is
microprocessors, millions of instructions per second are shown in Fig. 1.[7]. It is divided into five groups with
performed. So, speed of operation is the most important different bit size RCA. From the structure of Regular CSLA,
constraint. In digital adders, the speed of addition is limited by there is scope for reducing area and power consumption. The
the time required to propagate a carry through the adder. The carry out calculated from the last stage i.e. least significant bit
sum for each bit position in an elementary adder is generated stage is used to select the actual calculated values of the
sequentially only after the previous bit position has been output carry and sum. The selection is done by using a
summed and a carry propagated into the next position. multiplexer [I ]. Internal structure of the group 3 of regular 16-
The CSLA is used in many computational systems to bit CSLA is shown Fig.2.By manually counting the number of
alleviate the problem of carry propagation delay by gates used for group 3 is 87 (full adder, half adder, and
independently generating multiple carries and then select a multiplexer) and 13ns delay. One input to the mux goes from
carry to generate the sum. However, the CSLA is not area the RCA with Cin=O and other input from the RCA with
efficient because it uses multiple pairs of Ripple Carry Adders Cin=1.
(RCA) to generate partial sum and carry by considering carry
input Cin=O and Cin=I , then the final sum and carry are
selected by the multiplexers (mux).
The existing modified SQRT CSLA is to use Binary
to Excess-I Converter (BEe) instead of RCA with Cin=1 in
the regular CSLA to achieve lower area and power
consumption with slightly increase in the delay. The basic idea

978-1-4673-5301-4/13/$31.00 ©2013 IEEE

 different bit size RCA and BEC. The group 3 of the modified
16-bit CSLA is shown Fig. 6. By manually counting the
number of gates used for group 3 is 61 (full adder, half adder,
multiplexer, BEC) and the delay is 16ns. The parallel RCA
with Cin=1 is replaced with BEC. One input to the multiplexer
goes from the RCA with Cin=O and other input from the BEC.

Cout S111[ll:1l1

Fig.I.Regular 16-bit SQRT CSLA.

a b a b

Fig. 5 ModifIed 16-b SQRT CSLA.

06 s6 805 s4

\ �' :�'-:I
'! I-�'"
Comparing the group 3 of both regular and modified CSLA, it
is clear that BEC structure reduces the area and power. But the
disadvantage of BEC method is that the delay is increasing
� sumo liu.m5 sum4
[13] [13] [13] [13] than the regular CSLA [I ].

Fig.2: Delay and area evaluation for group3 b

TTT. MODIFIED SQRT CSLA USING BEC

The modified Carry select adder has a single ripple 4-b:il. BEC

carry adder with Binary to Excess-I converter, which replace

the ripple carry adder with Cin=l, in order to reduce the area � :1i13= .-.4

and power consumption of the regular CSLA. To replace the

n-bit RCA, an n+ I -bit BEC is required [2].A structure and the
:i� ,�r: �l A-e�I.'3l
. .

function table of a 4-b BEC is shown in Table I, respectively. co

1161
�r.;I.Tl6
116)
�HT1:"i
(,16)
�1-1"1114
rH'.jo')

The Boolean expressions of the 4-bit BEC is listed as (note the

functional symbols � NOT, & AND, I\XOR). Fig .6.Group 3 for ModifIed SQRT CSLA

TABLE T FUNCTION TABLE OF THE 4-b BEe. IV. COMMON BOOLEAN LOGIC

Binaryr3:0] Excess-l r3:0] In proposed work, an area-efficient carry select adder

0000 0001 by sharing the common Boolean logic term to remove the
0001 0010 duplicated adder cells in the conventional carry select adder.
I I In this way, it save many transistor counts and achieve a low
I I Power. Through analyzing the truth table of a single-bit full­
I I adder, To find out that the output of summation signal as
1110 1111 carry-in signal is logic "0" is the inverse signal of itself as
1111 0000 carry-in signal is logic "I ". As illustrated as two dotted circles
in the truth table of Fig. 7 [3].
By sharing the common Boolean logic term in
XO=�BO summation generation, a proposed carry select adder design is
XI =BO 1\ BI
illustrated in Fig. 8. To share the common Boolean logic term,
X2=B2 1\ (BO & BI )
it only needs to implement one OR gate with one INV gate to
X3=B3 1\ (BO & BI & B2). generate the Carry signal and summation signal pair. Once the
carry-in signal is ready, then select the correct carry-out output
The modified16-bit CSLA usmg BEC is shown according to the logic state of carry-in signal.
inFig.5. The structure is again divided into five groups with
 The Summation and carry signal for FA which has Cin=l,
Cin A B SO CO Generate by INV and OR gate. Through the multiplexer, we
--,
0 0 0 • 0 can select the correct output result according to the logic state
• O·
0 0 1 •
• 0 of carry-in signal.
1.
0 1 0 •
• 0 Internal structure of the group 3 of Proposed CSLA is
• 1
. shown Fig. 10. By manually counting the number of gates
0 1 1 • 1
o·
- used for group 3 is 36 (full adder, half adder, and multiplexer,
1 0 0 • 0
• 1 : not, or gate). One input to the mux goes from the RCA block
1 0 1 • 1
O' with Cin=O and other input from the CBL.
• •
1 1 0 1
• O. B[l] A[l] B[4] .'1.[4]
B[61 1\[6]
1 1 1 1
•
• 1 : + + +
---

Figure 7: The truth table of single-bit full-adder and single bit FA with FA FA HA
common Boolean logic

B A
A B

- CinCO)
FA
co

FA - Cin=O

--0

\' SUM[64]
Fig.! O. Group 3 using CBL.

\'(
CARRY SUM
Previous adder
cell carry signal
The Group 3 performed a three bit addition which are
A [4] with B [4] , A[S]with B[S] and A[6]with B[6]. This is

CMI)' �jgrntJ. for 1 done by I half adder (RA) and two full adder (FA). The CBL

FigureS. Single bit FA with Common Boolean Logic
As compared with the Modified Carry Select adder,
the proposed CSLA is little bit faster, but the speed is nearly
equal to the Regular CSLA. The delay time in our proposed
adder design is also proportional to the bit number N;
however, the delay time of multiplexer is shorter than that of
full adder. The Proposed CSLA is Area efficient & low power,
but the speed equal to the Regular CSLA.
V. PROPOSED CSLA ARCHITECTURE
This method replaces the BEC add one circuit by
Common Boolean Logic. The output waveform of full adder
for carry in signal is 'I ' is generate summation and carry
signal by just using an TNV and OR gate. It is shown in fig. 9
Cil
Fig 9. The Proposed 16-bit SQRT CSLA using CBL.
block has a 4:2 multiplexer to select the appropriate carryout
and summation signal for Carry-in signal 'I '. Through 2: I
multiplexer the carry signal is propagate to the next adder cell.
The 6:3 multiplexer and 4:2 multiplexer is the combination of
2: I multiplexer.
VI. COMP ARSTONS OF ADDERS
The 8-bit CSLA is done by the same structure of 16-
bit CSLA except group 4 and group S. The 8th bit inputs are
directly given to the full adder to complete the 8-bit sum and
carry. The 32-bit CSLA is done by cascading two 16-bit
CSLA and 64-bit CSLA is done by cascading two 32-bit
CSLA [4]. Table V exhibits the delay, area and power of
regular, modified and proposed CSLA Simulation is carried
out using Xilinx simulation tool and Spartan 3E as the target
device. The major disadvantage of modified CSLA using BEC
is the increasing delay. This disadvantage is overcome in
proposed architecture which reduces the delay, area and power
than the regular and modified CSLA.
The results depicted in Fig. I I shows that the
proposed CSLA has higher speed when compared to regular
and modified CSLA. Fig 12 compares the adder circuit for
area comparison. When compared to regular and modified
CSLA the proposed circuit occupies less area. Tn addition to
realization of higher speed and lesser area as discussed above,
Fig. 13 depicted that the proposed architecture consumes less
power when compared to the regular and modified CSLA.
 TABLE V Comparison of Adders for Delay, Area and Power
1000
Word Adder Area(No. of Delay Power • Regular(dual RCA)
Size Gate count) (ns) (mw)
800 • Modified(with BEC)
Regular 144 11.92 193
8-bit (dual RCA) • Proposed(with CBL)
600
SQRT Modified 132 13.69 180
CSLA (with BEC)
400
Proposed 111 11.15 119
(with CBL)
200
Regular 348 16.15 315
16-bit (dual RCA)
o
SQRT Modified 291 18.77 268
CSLA (with BEC)
Proposed 276 15.48 177 Fig. 13.comparison of adders for power
(with CBL)
Regular 698 28.97 553 VII. CONCLUSION.
32-bit (dual RCA)
SQRT Modified 762 34.44 448 A simple approach is proposed in this paper to reduce
CSLA (with BEC) the area, power and delay of SQRT CSLA architecture. The
Proposed 552 26.23 321 reduced number of gates of this work offers the great
(with CBL) advantage in the reduction of area, total power and also
Regular 1592 52.82 860 reduces the delay. A regular CSLA uses two copies of the
64-bit (dual RCA) carry evaluation blocks, one with block carry input is zero and
SQRT Modified 1498 64.61 745 other one with block carry input is one. The Regular SQRT
CSLA (with BEC) CSLA has the disadvantage of more power consumptions and
Proposed 1104 47.74 555 occupying more chip area. The modified SQRT CSLA
(with CBL) reduces the area and power when compared to regular CSLA
with increase in delay by the use of Binary to Excess-I
converter. This paper proposes a scheme which reduces the
80 delay, area and power than regular and modified CSLA by the
• Regular(dual RCA) use of Common Boolean Logic. It would be interesting to test the
60 • Modified(with BEC) design of the proposed 128-b SQRT CSLA.

• Proposed(with CBL) REFERENCES

40
[I] B.Ramkumar, . and Harish M Kittur, (2012) 'Low Power and
20 Area Efficient Can), Select Adder', IEEE Transactions on
Vel), Large Scale Integration (VLSI) Systems, pp.I-S.
[2] B. Ramkumar, H.M. Kittur, and P. M. Kannan, "ASIC
o
implementation of modified faster carry save adder," Eur. J
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[3] I-Chyn Wey, Cheng-Chen Ho, Yi-Sheng Lin, and Chien­
Fig.1 1 Comparison of adders for delay.
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by Sharing the Common Boolean Logic Term' Proceeding on
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• Regular(dual RCA)
[4] Y. He, C. H. Chang, and 1. Gu, "An area efficient 64-bit square
1500 • Modified(with BEC) root can),-select adder for lowpower applications," in Proc.
• Proposed(with CBL) IEEE Int. Symp. Circuits Syst., 2005, vol. 4, pp. 4082-4085.

1000 [5] Y. Kim and L. -S. Kim, "64-bit carry-select adder with reduced
area,"Electron. Lett. vol. 37, no. 10, pp. 614-615, May 2001.
[6] J. M. Rabaey, Digtal Integrated Circuits-A Design
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Fig.12. Comparison of adders for area.

Manju.S was born on February 11. 1990 in Ranipet. Sornagopal.V received the B. E degree in Electronics and
Tamilnadu. India. She has received the B. E degree in Communication Engineering from Thanthai Periyar Government
Electronics and Communication Engineering from Ranippettai Institute of Technology (TPGIT). Madras University. Tamilnadu.
Engineering College. Anna University. Vellore. Tamilnadu. India and M. E degree in Applied Electronics from C.Abdul
India. in May 2011. She is currently pursuing her M. E degree Hakeem College of Engineering and Technology. Anna
in Applied Electronics from C. Abdul Hakeem College of University. Tamilnadu. India in 2000 and 2009 respectively. He
Engineering and Technology. Anna University. Vellore. worked as lecturer in S. B. C. Engineering College. Tamilnadu.
Tamilnadu. India from 2011 to 2013. She has published a India. He is currently working as Assistant Professor in C.Abdul
paper in National conference conducted by C. Abdul Hakeem Hakeem College of Engineering and Technology. Tamilnadu.
College of Engineering and Technology on March 5. 2011. Her India. He has published 8 papers in both International and
areas of interest include low power VLSI and Digital National conferences. His research interests include Image and
Electronics. video processing applications. Microwave engineering. analog
devices & circuits. Digital Electronics and Electronic Circuits.