11/16/2017 DIGITAL BASIC - 1.

3 : LOGIC GATES (Part - b) |VLSI Concepts

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Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

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Thursday, December 12, 2013

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DIGITAL BASIC - 1.3 : LOGIC GATES (Part - b) 3Ps (Passion, Pati

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Chapter1 Chapter2 Chapter3 Chapter4
suggest to students/ca
Index Digital CMOS
Semiconductor Background
Background Processing

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1.1 1.2 1.3a 1.3b 1.4 1.5 1.6
Number Digital Logic Logic Combinational Multiplex
System Arithmetic Gates Gates Circuits (MUX) Be the first of your f

In the previous post we have discussed about the basics of Logic gates (Logic levels , Different types of gates, their truth table, Boolean
expression and important points/notes about gates).
As I have mentioned that NAND and NOR gates are Universal gates and we can realize any basic gates using these Universal gates. So below is
the table which will help you to understand how we can use NAND/NOR gates to realize the basic gates.

Realization of Basic gates using NAND and NOR gates:

Gate Using NAND Using NOR

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NOR

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The minimum number of NAND gates required to realize X NOR is five.
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The minimum number of NOR gates required to realize X – OR gate is five.
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AND, OR, NAND and NOR gates can be used to control the passage of an input logic signal through to the output.
When a logic signal is applied to one of the input of the logic gates, the output of the gate is decided by the other input "Timing Paths" : Sta
Timing Analysis (ST
which is known as control input B. basic (Part 1)
The logic level at this control input will determine whether the input signal is “enable to each the output” or “inhibited
Basic of Timing
from reaching the output”. Analysis in Physical
Design

"Setup and Hold Tim

: Static Timing Analy
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Violation" : Static
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Delay - "Wire Load

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"Examples Of Setup
and Hold time" : Sta
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Delay - "Interconnec
Delay Models" : Sta
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basic (Part 4b)

"Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)

5 Steps to Crack VL
A bubbled NAND gate is equivalent to OR gate. Interview

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and HOLD violation
Static Timing Analys
(STA) Basic (Part-8)

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