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A Seven Level Packed U Cell (Puc) Multilevel Inverter For Photovoltaic System View project
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Abstract—This Paper presents a 15 level Asymmetrical one DC source. Clamping capacitors and diodes are not used
Cascaded H bridge multilevel inverter Topology for Photovoltaic here[5]. In CHBMLI Topology, depending upon DC source it
system. In this system Symmetrical and Asymmetrical Multilevel consists of two types, 1.Single DC source and 2.Multiple DC
inverter (MLI) is utilized. In Symmetrical MLI, the DC source source[4]-[3].In Single DC source the CHBMLI are connected
magnitude are equal ie., 50Vdc, 50Vdc & 50Vdc., where as in in parallel and to the output of each H Bridge the low
Asymmetrical MLI the DC source Magnitude are unequal and it frequency transformer is connected .To increases the “n”
is designed with binary form of voltage such as 50Vdc, 100Vdc & number of levels the Transformer is increased for each H
200Vdc.Comparing both the MLI , Asymmetrical MLI generates Bridge inverter, so that the efficiency of system will become
a number of output voltage level with same number of Power
less. In multiple DC Source the CHBMLI are connected in
semiconductor switches. The phase Disposition Pulse Width
Modulation (PD-PWM) technique is used for controlling the
series.To increase the “n” number of output voltage levels the
Power semiconductor switches in MLI. The results are verified in several H-Bridge and DC source are used. To reduce the
both MATLAB and PROTEUS. switches in this topology the Symmetrical and Asymmetrical
CHBMLI are utilized.[1]-[2].
Keywords—Photo voltaic system(PV), Symmetrical MLI ,
Asymmetrical MLI, PD-PWM,PIC16F877A,IR112.
I. INTRODUCTION
In recent years, countries all over the world has its
attention towards global warming. One of the cause is
conventional fossil fuel based power generating sources and it
has become a serious concern. Among the usage of renewable
energy resources like wind , solar, geothermal etc.,
photovoltaic (PV) system is very important source of energy
and it has acquired a lot of attention due to the research and
development in the fabrication of solar cell. Power electronic
converter technology is required for generation of solar power,
which reduces the cost and enhances the system efficiency
[6]-[7].
Multilevel Inverter (MLI)has more advantages than
conventional inverter because of less switching losses, less
voltage stress across switch and less Electromagnetic
Interference (EMI).Generally there are three basic types of
MLI they are Neutral point Clamped (NPC MLI),Flying
Capacitor (FC MLI) and Cascaded H-Bridge (CHB MLI).The
Figure 1 shows the classification of MLI. In NPCMLI it Fig. 1. Classifications of Multilevel Inverter
consists of clamping diodes which increases the voltage levels.
The capacitor are connected in series for voltage balancing.
This makes a huge problem for devices. In FCMLI more
number of clamping capacitors are connected, so the voltage
balancing is difficult. CHBMLI is suitable for high voltage
applications because, each H bridge consists of 4 switch and
A. Symmetrical Cascaded H Bridge Multielvel Inverter The ‘n’ Represents the number of MOSFET in
Symmetrical unit Circuit.
B. Asymmetrical Cascaded H Bridge Multielvel Inverter
Figure 3 represents the Asymmetrical Cascaded H Bridge
Inverter (ASCHB-MLI) topology. In this Inverter the DC
source magnitude are unequal. The DC source magnitude are
designed with binary form of voltage such as 25VDC, 50VDC ,
100VDC respectively. Both the inverter consists of same
number of Power semiconductor switches but the voltage level
varies. In SCHBMLI the output voltage is 9level, where as in
ASCHBMLI the output voltage is 15 level and they are
15Vdc, 30Vdc, 45Vdc, 60Vdc,75Vdc,90Vdc,105Vdc,0Vdc,-15Vdc,
-30Vdc,-45Vdc,-60Vdc,-75Vdc,-90Vdc,-105Vdc respectively.[8]
Fig. 5. Output Voltage level Vab = 6Vdc/7to generate the Switching Sequence
E. Mode 5: Positive output voltage (3Vdc/7): G. Mode 7: Positive output voltage (Vdc/7):
When MOSFET Switch S1,S2&S4 is turned ON and When MOSFET switch S1 & S4 is turned ON and
MOSFET Switch S3 is turned OFF the current flows via Diode MOSFET Switch S2 &S3 is turned OFF the current flows via
D3.So that the positive voltage 3Vdc/7 is united to the (+ve) Diode D2 &D3.So that the positive voltage 1Vdc/7 is united to
terminal (a) of the load. When the MOSFET Switch S5 is the (+ve) terminal (a) of the load.When the MOSFET switch
turned ON , the (-ve) terminal (b) of the load is united to the S5 is turned ON , the (-ve) terminal (b) of the load is united to
ground and remaining all the switches are in OFF condition. the ground and remaining all the switches are in OFF
The current flows through the load from ‘a’ to ‘b’, so that the condition. The current flows through the load from ‘a’ to ‘b’,
voltage brought to bear across the load is +3Vdc/7 as shown in so that the voltage brought to bear across the load is + 1Vdc/7
as shown in figure 10.
figure 8.
Fig. 10. Output Voltage level Vab=Vdc/7to generate the Switching Sequence
F. Mode 6: Positive output voltage (2Vdc/7): The Zero Output voltage level is produced by turning
ON MOSFET Switch S7&S5orS4&S6 and remaining controlled
When MOSFET switch S2 &S4 is turned ON and Switch switches are in off condition. When MOSFET switch S7 &S5
S1& S3 is turned OFF the current flows via Diode D1& D3.So or S4 &S6 is turned on , the output voltage across the load is
that the positive voltage 2Vdc/7 is united to the (+ve) terminal zero as shown in the figure 11
(a) of the load. When the MOSFET switch S5 is turned ON ,
the (-ve) terminal (b) of the load is united to the ground and
remaining all the switches are in OFF condition. The current
flows through the load from ‘a’ to ‘b’, so that the voltage
brought to bear across the load is + 2Vdc/7 as shown in figure
9.
Fig. 11. Output Voltage level Vab = 0Vdc to generate the Switching Sequence
When MOSFET Switch S1&S6 is turned ON and MOSFET When MOSFET Switch S1,S2&S6 is turned ON and
Switch S2 & S3 is turned OFF the Current flows via Diode D2 MOSFET Switch S3 is turned OFF the Current flows via
& D3, So that the Positive voltage Vdc/7 is united to the (-ve) Diode D3 , So that the Positive voltage 3Vdc/7 is united to the
terminal (b) of the load. When the MOSFET switch S7 is (-ve) terminal (b) of the load. When the MOSFET S7 is
turned ON , the (+ve) terminal (a) of the load is united to the turned ON , the (+ve) terminal (a) of the load is united to the
ground and remaining all the switches are in OFF condition. ground and remaining all the switches are in OFF condition.
The current flows through the load from ‘b’ to ‘a’, so that the The current flows through the load from ‘b’ to ‘a’, so that the
voltage brought to bear across the load is -1Vdc/7 as shown in voltage brought to bear across the load is -3Vdc/7 as shown in
figure 12. figure 14.
Fig. 12. Output Voltage level Vab = -Vdc/7to generate the Switching Sequence
Fig. 13. Output Voltage level Vab = -2Vdc/7to generate the Switching Sequence
2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
Fig. 15. Output Voltage level Vab = -4Vdc/7to generate the Switching Sequence
Fig. 16. Output Voltage level Vab = -5Vdc/7to generate the Switching Sequence
Vo S1 S2 S3 S4 S5 S6 S7
Vdc 1 1 1 1 1 0 0
6Vdc/7 0 1 1 1 1 0 0
5Vdc/7 1 0 1 1 1 0 0
4Vdc/7 0 0 1 1 1 0 0
3Vdc/7 1 1 0 1 1 0 0
2Vdc/7 0 1 0 1 1 0 0
Vdc/7 1 0 0 1 1 0 0
0Vdc 0 0 0 1 0 1 0 Fig. 20. PD-PWM Switching signal Generation
Fig. 19. Modulation Technique for Inverter Fig. 22. switches Pulse for S1,S2 &S3
2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
Fig. 25. THD Analysis for Asymmetric 15 level CHB Inverter using pulse Fig. 28. Output Voltage for 15 level ASCHB Inverter using PD-PWM
Fig. 27. PWM signals for S4,S5,S6 &S7 Fig. 29. THD Analysis for 15 level ASCHB Inverter using PD-PWM
2016 International Conference on Circuit, Power and Computing Technologies [ICCPCT]
Figure 33 shows the Asymmetrical Cascaded H Bridge with fewer number of components for high-voltage levels in IET Power
Electronics 2013
Multilevel inverter ouput voltage waveform.The output
voltage levels of inverter are 8Vdc, 16Vdc, 24Vdc, 32Vdc, 40Vdc,
[9] Euzeli Cipriano dos Santos, Jr., Member, IEEE, October 2011, Cursino
48Vdc,56Vdc,0Vdc,-8Vdc,-16Vdc, -24Vdc, -32Vdc, -40Vdc, Brandão Jacobina, Senior Member, IEEE “Component Minimized AC–
-48Vdc, -54Vdc respectively. DC–AC Single-Phase to Three-Phase Four-Wire Converters”, IEEE
Transactions on Industrial Electronics, Vol. 58, No. 10.
VI. CONCLUSION [10] J. Lai and FZ. Peng, Aug. 2002, “Multilevel converters: a survey of
topologies, controls, and applications”, IEEE TransIndustrial
A symmetrical Cascaded H bridge Multil level Application, vol. 49(4), pp. 724–738.
inverter(SCHBMLI) and Asymmetrical Cascaded H bridge
Multilevel Inverer(ASCHBMLI) has been analysed in this [11] . Wu, P. G Song, 2004, "Comprehensive Analysis of Multi-Megawatt
paper. Both the Inverter consist of the same power Variable Frequency Drives", Transaction of China Electromechanical
Society, Vol.19, No. 8, pp.42-50.
semiconductor switches but the output voltage levels are
different. In SCHBMLI the ouput voltage is 9 level , while [12] -R.Lin and H.-H.Lu, July 1999, “Multilevel AC/DC/AC converter for
ASCHBMLI the ouput voltage levels are 15 level. The THD AC drives”, IEE Proc.-Electr Power Appl., Vol. 146, No. 4.
analysis for ACHBMLI using the switching technique of
high switching frequency (2KHz) PD-PWM is 6.03% and the [13] Ceglia, Victor Guzman, Carlos Sanchez, Fernando Ibanez,
switching technique of low switching frequency(50Hz) is JulioWalter, and Maria I. Gimenez Sep. 2006, “A New Simplified
Multilevel Inverter Topology for DC-AC Conversion,” IEEE Trans.
10.26%. In this system the THD is very less by using PD- Power Electron vol. 21, no. 5, pp. 1311-1319,
PWM technique.This type of system is used for high power
applications for photovoltaic system bec it reduce the overall
cost and size of the system.
References
[1] G. Eason, B. Noble, and I.N. Sneddon, “On certain integrals of Javier
pereda, and juan dixon, “cascaded multilevel converters: optimal
asymmetries and floating capacitor control” ieee transactions on
industrial electronics, vol. 60, no. 11, november 2013.
[2] M. Mohamad fathi mohamad elias, nasrudin abd. Rahim, hew wooi
ping, and mohammad nasir uddin, asymmetrical cascaded multilevel
inverter based on transistor-clamped h-bridge power cell ieee
transactions on industry applications, vol. 50, no. 6, november/december
2014.
[5] Javier pereda, student member, ieee, and juan dixon, senior
member,high-frequency link: a solution for using only one dc source in
asymmetric cascaded multilevel inverters ieee ieee transactions on
industrial electronics, vol. 58, no. 9, september 2011.