AXI4 Overview

- Benefits of Adopting AXI4

- Protocol Overview

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 AMBA® AXI4TM - Advanced Extensible Interface

ƒ Latest version of AMBA - Industry standard on-chip communication

ƒ Enables higher performance vs. existing bus architectures
ƒ Supports FPGA designs

AMBA 3.0

APB AHB AXI

AMBA 4.0 AXI4 AXI4

AXI4
Stream Lite

ARM and Xilinx partnered to develop AXI4 standard

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Broader IP Availability- ARM Connected Community

Over 400 ARM partners for IPs and Tools on the market
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Increased Productivity – AXI4 supports Memory
Mapped, Control and Streaming Applications
AXI4 AXI DDR3
AXI4
Memory
AXI4 Memory
Controller
AXI
MBDEBUG
Interconnect AXI4
MDM AXI4
Block BRAM
AXI4
AXI – PLB46
Bridge

MicroBlaze
D-LMB AXI4-Lite DMA
AXI4-Stream TEMAC Ethernet
BRAM
I-LMB

AXI4-Lite
GPIO Switches
AXI4-Lite
AXI4-Lite
UARTLITE RS232
AXI
Interconnect AXI4-Lite
Block Timer

AXI4-Lite Interrupt
Controller

Single Interconnect Standard for IP across All Domains

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AXI4 is an Interface Specification

PLBv46
“Shared Access” Bus “Interconnect”
Processor
Part of the spec Provided by Xilinx
PLB AXI Slaves

AXI AXI
Peripherals AXI4 defines a point to AXI AXI

point, master/slave
PLB interface
AXI AXI AXI AXI
AXI

PLB

AXI4 interconnect IP AXI AXI

AXI

•Xilinx provided
PLB
•Many companies build and sell
Arrows indicate Master/Slave Relationship
“AXI Interconnect IP” not direction of data flow

Master Slave
Arbiter

PLBv46 is a Bus Spec / AXI is an Interface Spec

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AXI4 Memory Interface vs. Multi Port Memory
Controller with Local Link
AXI4 allows a
different clock Only
32, 64,128, supports 32- Only one clock
domain for each bit interface
256-bit interface domain allowed
to interconnect master / slave pair to switch
(simplified
illustration)
D D Write
Write DDR3 @
A DDR3 @ A
300 MHz 300 MHz
T T
32-bit 32-bit
A A Read
Read
External External
Memory Memory

MicroBlaze MicroBlaze
AXI4-based
Interconnect
Block + AXI
MIG
Memory
Controller AXI4 MPMC MPMC

AXI4 provides more flexibility in interface widths and clocking

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AXI4 Benefits

• Over 400 ARM partners for IPs and Tools on the market
Availability • Xilinx and ARM connected communities developing IPs for FPGAs
• Helps You to invest with confidence

• Single interconnect standard for

• ALL domains
Productivity • ALL Xilinx and Partner IPs
• Only one standard to learn
• Reduces time spent to integrate IPs within the design
• Provides higher performance (bandwidth) over PLBv46

• Configure the interconnect to meet system goals:

Flexibility Performance, Area, Power
• Enables ASIC verification methodology

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 AXI4 Overview
- Benefits of Adopting AXI4
- Protocol Overview
- ISE Design Suite AXI4 Support
- Design Migration

Page 8 Xilinx Confidential – Internal

© Copyright 2012 Xilinx
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AXI4 - Advanced Extensible Interface
Standard Overview

ƒ AXI4
– Three flavors: AXI4, AXI4-Lite,
AXI4-Stream
– All three share same handshake
rules and signal naming

AXI4 AXI4-Lite AXI4-Stream

high-performance register-style interfaces non-address
Dedicated for and memory (area efficient based IP
mapped systems implementation) (PCIe, Filters, etc.)
Burst up to 256 1 Unlimited
(data beta)
Data width 32 to 1024 bits 32 or 64 bits any number of bytes
Applications Embedded, memory Small footprint DSP, video,
(examples) control logic communication
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 AXI Fundamental Vocabulary

ƒ Channel
– Independent collection of AXI signals associated to a VALID signal

ƒ Interface
– Collection of one or more channels that expose an IP core’s function, connecting a
master to a slave
– Each IP core may have multiple interfaces.
– Also: AXI4, AXI4-Lite, AXI4-Stream

ƒ Bus
– Multiple-bit signal (not an interface or channel)

ƒ Transfer
– Single clock cycle where information is communicated, qualified by a VALID handshake.
Data beat.

ƒ Transaction
– Complete communication operation across a channel, composed of a one or more
transfers

ƒ Burst
– Transaction that consists of more than one transfer
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Basic AXI4 Handshaking

ƒ Master asserts and holds VALID when data is available

ƒ Slave asserts READY if able to accept data

ƒ DATA and other signals transferred when VALID and READY = 1

ƒ Master sends next DATA/other signals or deasserts VALID

ƒ Slave deasserts READY if no longer able to accept data
DATA
AXI AXI
VALID
Master READY
Slave
ACLK

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Basic AXI4 Signaling
5 Channels, Point to Point

Read Address Channel

MASTER

SLAVE
Read Data Channel

Write Address Channel

MASTER

SLAVE
Write Data Channel

Write Response Channel

AXI4, AXI4-Lite, AXI4-Stream are all simple variants of these 5 channels

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The AXI Interface—AXI4

ƒ Single address

MASTER
AXI4

SLAVE
multiple data Read
– Burst up to 256
data beats

ƒ Data Width
parameterizable
MASTER

– 32, 64, 128, 256,

SLAVE
512, 1024 bits AXI4
Write

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Example Transaction: AXI4 Write Burst

ƒ Four data writes

ƒ Length and size of data write specified by Write Address Channel
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Example Transaction: AXI4 Read Burst
(Pipelined address)

ƒ Pipelined read address A and B

ƒ Length and size of data read specified by Read Address Channel

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 The AXI Interface—AX4-Lite

ƒ No burst

MASTER
AXI4-Lite

SLAVE
Read
ƒ Data width 32

ƒ Very small footprint

ƒ Bridging to AXI4
handled automatically
MASTER

by AXI_Interconnect

SLAVE
(if needed) AXI4-Lite
Write

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 AXI4/AXI4-Lite
5 Channels

Master Slave

Write Address Write Data Channel Read Address Read Data Channel
Channel ƒ WVALID Channel ƒ RID[m:0]
ƒ AWID[m:0] ƒ WREADY ƒ ARID[m:0] ƒ RVALID
ƒ AWVALID ƒ WDATA[n-1:0] ƒ ARVALID ƒ RREADY
ƒ AWREADY ƒ WSTRB[n/8-1:0] ƒ ARREADY ƒ RDATA[n-1:0]
ƒ AWADDR[31:0] ƒ WLAST ƒ ARADDR[31:0] ƒ RRESP[1:0]
ƒ AWLEN[7:0] ƒ ARLEN[7:0] ƒ RLAST
ƒ AWSIZE[2:0] Write Response ƒ ARSIZE[2:0]
ƒ AWPROT[2:0] Channel ƒ ARBURST[1:0]
ƒ AWBURST[1:0] ƒ BID[m:0] ƒ ARPROT[2:0] ACLK
ƒ AWLOCK ƒ BVALID ƒ ARLOCK ARESETn
ƒ AWCACHE[3:0] ƒ BREADY ƒ ARCACHE[3:0]
ƒ AWREGION[3:0] ƒ BRESP[1:0] ƒ ARREGION[3:0]
ƒ AWQOS[3:0] ƒ ARQOS[3:0] AXI4-Lite signals bolded
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 The AXI Interface—AXI4-Stream

ƒ No address channel, no read and

write, always just master to slave AXI4-Stream Transfer
– Effectively an AXI4 “write data”
channel

ƒ Unlimited burst length

MASTER

SLAVE
– AXI4 max 256
– AXI4-Lite does not burst

ƒ Virtually same signaling as AXI4

Data Channels
– Protocol allows merging, packing,
width conversion
– Supports sparse, continuous, aligned,
unaligned streams

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