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TABLE LINKS
ORTC Tables
FOCUS A Tables
FOCUS B Tables
FOCUS C Tables
FOCUS D Tables
FOCUS E Tables
FOCUS F Tables
CROSS CUT A Tables
CROSS CUT B Tables
2009 ITRS Table Listing
2009 ITRS Chapter Page
Table ERD8
Table ERD9
Table ERD10
Table ERD11
Table ERD12
Table ERD13
Table ERD14
Table ERD15
rch Devices
Emerging Research Devices Difficult Challenges
Memory Taxonomy
Current Baseline and Prototypical Memory Technologies
Transition Table for Emerging Research Memory Devices
Emerging Research Resistance-based Memory Devices—Demonstrated and Projected Parameters
Transition Table for Emerging Research Logic Devices
MOSFETS:Extending the channel to the End of the Roadmap
Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based information carrier devices
Alternative Information Processing Devices
Research and Technology Development Schedule proposed for Carbon-based Nanoelectronics to impact the
Industry's Timetable for Scaling Information Processing Technologies.
Prototypical criteria for emerging device architectures
Summary of the attributes of several emerging research devices and projections for their application spaces.
Challenges in Existing Memory Systems
Opportunities for Emerging Memory Devices
Hardware requirements for the three basic approaches to probabilistic inference
Potential Evaluation for Emerging Research Memory Devices
Potential Evaluation for Emerging Research Logic and Alternate Information Processsing Devices
rch Materials
Emerging Research Material Technologies Difficult Challenges
Applications of Emerging Research Materials
Challenges for ERM in Alternate Channel Applications
Alternate Channel Material Properties -- Protected Sheet NEED PASSWORD
Spin Material Properties
ERM Memory Material Challenges
Challenges for Lithography Materials
FEP / PIDS Challenges for Self Assembly
Interconnect Material Challenges
Nanomaterial Interconnect Material Properties
Assemby & Package ERM Challenges
ITWG Earliest Potential ERM Insertion Opportunity Matrix
Table ERD1 Emerging Research Devices Difficult Challenges
Identify the most promising technical approach(es) to obtain electrically accessible, high-speed,
high-density, low-power, (preferably) embeddable volatile and non-volatile RAM
The desired material/device properties must be maintained through and after high temperature
and corrosive chemical processing
Reliability issues should be identified & addressed early in the technology development
Develop means to control the variability of critical dimensions and statistical distributions (e.g.,
gate length, channel thickness, S/D doping concentrations, etc.)
Extend ultimately scaled CMOS as a platform technology into new Discover and reduce to practice new device technologies and a primitive-level architecture to
domains of application. provide special purpose optimized functional cores heterogeneously integrable with silicon
CMOS.
Continue functional scaling of information processing technology
substantially beyond that attainable by ultimately scaled CMOS. Invent and develop a new information processing technology eventually to replace CMOS
Ensure that a new information processing technology is compatible with the new memory
technology discussed above; i.e., the logic technology must also provide the access function in
a new memory technology.
Bridge a knowledge gap that exists between materials behaviors and device functions.
Reliability issues should be identified & addressed early in the technology development
Reversibly
Remnant
Magnetizatio changing
Inter-locked Charge polarization
n of amorphous
Storage Mechanism Charge on a capacitor state of logic Charge on floating gate trapped in on a
ferromagnetic and
gates gate insulator ferroelectric
layer crystalline
capacitor
phases
Spin-polarized
Write has a
potential to
Multiple-bit Multiple-bit Multiple-bit Destructive Multiple-bit
Comments potential potential potential read-out
lower write
potential
current density
and energy
[O],
[B] Estimated as E~0.5*CV2 for C=25fF, Vc=0.60 Volts (in 2009) and Vc=0.35 Volts in 2024 (energy to refresh is not included).
[C] See the Embedded Memory Requirements table in the System Drivers chapter.
[E] Embedded applications (see the Embedded Memory Requirements table in the System Drivers chapter).
[G] Trapping charge memories in PIDS chapter include SONOS, and a number of engineered barrier concepts, some of which are described in Table ERD5a.
[H] J-Y. Wu et al. “A Single-Sided PHINES SONOS Memory Featuring High-Speed And Low-Power Applications.” IEEE Electr. Dev. Lett. 27 (2006) 127.
[I] K. R. Udayakumar et al. “Full-Bit Functional, High-Density 8 Mbit One Transistor-One Capacitor Ferroelectric Random Access Memory Embedded Within A Low-
Power 130 nm Logic Process.” Jap. J. Appl. Phys. 46 (2007) 2180-2183.
[J] “Nanoelectronics and Information Technology.” Ed. Rainer Waser. Wiley-VCH, 2003, 568-569.
[K] H. Kohlstedt et al. “Current Status And Challenges Of Ferroelectric Memory Devices.” Microelectronic Eng. 80 (2005) 296-304.
[L] Estimated as E~0.5*q*A*V for q=13.5 mC/cm2, A=0.33mm2, Vc=1.5 Volts (in 2009) and q=30 mC/cm2, A=0.069mm2, Vc=0.7 Volts (in 2024).
[M] N. Sakimura et. al. “MRAM Cell Technology For Over 500-MHz SOC.” IEEE J. Solid-State Circ. 42 (2007) 830-838.
[N] H. W. Schumacher. “Ballistic bit addressing in a magnetic memory cell array.” Appl. Phys. Lett. v. 87 , no. 4 (2005) 42504.
[O] Y. Jiang, T. Nozaki, S. Abe, T. Ochiai, A. Hirohata, N. Tezuka, K. Inomata. “Substantial Reduction Of Critical Current For Magnetization Switching In An Exchange-
Biased Spin Valve.” Nature Materials, v. 3, June 2004, 361-364.
[P] W. Y. Cho, B-H Cho, B-G. Choi, H-R Oh, S. Kang, K-S. Kim, K-H. Kim, D-E. Kim, C-K. Kwak, H-G. Byun, Y. Hwang, S. J. Ahn, G-H. Koh, G. Jeong. H. Jeong, and
K. Kim.“A 0.18-mm 3.0-V 64-Mb Nonvolatile Phase-Transition Random Access Memory (PRAM).” IEEE J
[Q] Estimated as E~0.5*I2R*tw for I=202 mA, R=6 kOhm, tw=50 ns (in 2009) and I=12mA, R=45 kOhm, <50 ns (in 2024).
Capacitance-
Resistance-based
based
Ferroelectric FET Nanomechanical Spin Torque Nanothermal Electronic Effects Macromolecular
Nanoionic Memory Molecular Memories
memory Memory Ttransfer Memory Memory Memory Memory
Cell Elements 1T 1T1R or 1D1R 1T1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R 1T1R or 1D1R
1) nanobridge/ 1) Fuse/Antifuse
1) cation migration 1) Charge trapping
cantilever Memory
Magnetization
FET with FE gate
Device Types 2) telescoping CNT change by spin 2) nanowire PCM 2) anion migration 2) Mott transition M-I-M (nc)-I-M Bi-stable switch
insulator
transfer torque
3) Nanoparticle 3) FE barrier effects
Min. required <65 nm <65 nm <65 nm <65 nm <65 nm <65 nm <65 nm <65 nm
Feature size F Best projected 22 nm [A1] 5-10 nm [B1] 7-10 nm 5-10 nm 5-10 nm 5-10 nm 5-10 nm 5 nm [H1]
Demonstrated ~2 mm [A2] 180 nm [B2] 50 nm [C1] 180 nm [D1] 90 nm [E1] 1 mm [F1] 250 nm [G1] 30 nm [H2]
Min. required 8F2/4F2 [A3] 10F2 10 F2 10 F2 10 F2 10 F2 10 F2 10 F2
Cell Area Best projected 8F2/4F2 [A3] 5F2 6F2 [C2] 8/5F2 [D2] 8/5F2 [D2] 8/5F2 [D2] 8/5F2 [D2] 5F2
Demonstrated Data not available Data not available 16F2 [C3] Data not available 8F2 [E1] Data not available Data not available Data not available
Min. required <15 ns <15 ns <15 ns <15 ns <15 ns <15 ns <15 ns <15 ns
Read Time Best projected 2.5 ns <3 ns <10 ns <10 ns <10 ns <10 ns <10 ns <10 ns [H1]
Demonstrated 20 ns [A4] 3 ns [B3] ~40ns[C3] Data not available <50 ns [E1] Data not available ~10 ns [G2] Data not available
Application Application Application Application Application Application Application Application
Min. required
dependent dependent dependent dependent dependent dependent dependent dependent
W/E time
Best projected 2.5 ns [A1] <1 ns [B1,B2] <2 ns <10 ns <20 ns [E2] <20 ns [F2] <10 ns <40 ns [H1]
Demonstrated 20 ns [A5] 3 ns [B3] 2ns [C4] 10 ns/5 ns [D3] 5 ns/5 ns [E3,E4] 100 ns [F2] 10 ns [G2] 0.2 s [H3]
Min. required >10 y >10 y >10 y >10 y >10 y >10 y >10 y >10 y
Retention Time Best projected >10 y [A5] >10 y >10 y >10 y >10 y >10 y Not known Not known
Demonstrated >30 days [A5] ~days [B1] >10 y[C1] >8 months [D1] >10 y [E5] 1 y [F3] 6 month [G4] 2 months [H4]
Min. required >1E5 >1E5 >1E5 >1E5 >1E5 >1E5 >1E5 >1E5
Write Cycles Best projected >1E16 >1E16 >1E16 >1E16 >1E16 >1E16 >1E16 >1E16
Demonstrated 1.00E+12 >1E9 [B1] >1E12 [C4] >1E6 [D1] >1E9 [E6] >1E3 [F4] >1E6 [G2] >2E3 [H2]
Application Application Application Application Application Application Application Application
Min. required
dependent dependent dependent dependent dependent dependent dependent dependent
Write operating
voltage (V) Best projected <0.9 V [A1] Not known [B4] <1 V 0.5/1 <0.5 V [E7] <3 V <1 V [G1] 80 mV[H5]
Demonstrated ±4[A5] 1.5 V [B1] ~±1.0 [C4] 0.5/1 [D1] 0.6/-0.2 [E1] 3-5 V [F1,F2] ~±2 [G2] ~±1.5 V [H2]
Min. required 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5
Read operating
Best projected 0.7 0.7 <0.5 <0.5 <0.2 V [E7] 0.7 0.7 0.3 [H1]
voltage (V)
Demonstrated 2.5 [A4] 1.5 V [B1] 0.7 [C3] 0.4 [D1] 0.15 V[E1] 0.7 V [F1] 1 V [G2] 0.5 V [H2]
Application Application Application Application Application Application Application Application
Min. required
dependent dependent dependent dependent dependent dependent dependent dependent
Write energy (J/bit)
Best projected 2E-15 [A6] Not known [B4] <1E-13 Not known 1E-15 [E8] <1E-10 Not known 2E-19 [H6]
Demonstrated Data not available Data not available 4E-12 [C4] 1E-12 [D4] 5E-14 [E9] 1E- 9 [F5] 1E-13 [G3] Data not available
CNT—carbon nanotube
[A1] Fitsilis M, Mustafa Y, Waser R, Scaling the ferroelectric field effect transistor, INTEGRATED FERROELECTRICS 70: 29-44 2005
[A2] M. Takashashi and S. Sakai, “Self-aligned-gate Metal/Ferroelectric/Insulator/Semiconductor field-effect transistors with long memory retention”, Jap. J. Appl. Phys. 44 (2005)
L800-L802
[A3] 4F2 is for NAND or multiple bit storage, see e.g. Y Tabuchi, S. Hasegawa, T. Tamura, H. Hoko, K. Kato, Y. Arimoto, H. Ishiwara, “Multi-bit programming for 1T-FeRAM by
local polarization method”, 2005 SSDM, pp. 1038-1039
[A4] H. Ishiwara, “Application of Bismuth-layered perovskite thin films to FET-type ferroelectric memories”, Integrated Ferroelectrics 79 (2006) 3-13
[A5] H. Ishiwara, "Current status of ferroelectric-gate Si transistors and challenge to ferroelectric-gate CNT transistors", Curr. Appl. Phys. 9 (2009) S2-S6
[A6] Calculated based on the parameters of scaled FE capacitor projected in Ref. [A1]
[B1] T. Rueckes et al. “Carbon nanotube-Based Nonvolatile Random Access Memory for Molecular Computing.” Science 289 (2000): 94-97.
[B2] J. W. Ward, M. Meinhold, B. M. Segal, J. Berg, R. Sen, R. Sivarajan, D. K. Brock, and T. Rueckes. “A Non-Volatile Nanoelectromechanical Memory Element Utilizing A Fabric
Of Carbon Nanotubes.” Non-Volatile Memory Technology Symposium, 15-17 Nov. 2004,
[B3] www.nantero.com
[B4] The projections for WRITE voltage and WRITE energy depend on the length of nanoelectromechanical element. For very small length, the operating voltage might be too high for
practical use, as follows from theoretical analysis in: M. Dequesnes et al. “
[C1] T. Kishi, et al. "Lower-current and Fast switching of A Perpendicular TMR for High Speed and High density Spin-Transfer-Torque MRAM" Electron Devices Meeting, 2008.
IEDM 2008. IEEE International (2008).
[C2] U.K. Klostermann, et al. "A Perpendicular Spin Torque Switching based MRAM for the 28 nm Technology Node" Electron Devices Meeting, 2007. IEDM 2007. IEEE
International (2007).
[C3] T. Kawahara, et al. "2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read" 2007 ISSCC Technical
Digest, 480 (2007).
[C4] M. Hosomi, et al. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching:Spin-RAM" 2005 IEDM Technical Digest, 459 (2005).
[D1] G. Baek, et al. "Highly Scalable Nonvolatile Resistive Memory Using Simple Binary Oxide Driven By Asymmetric Unipolar Voltage Pulses.” 2004 International Electron Devices
Meeting, San Francisco, CA, USA, 13/12/2004-15/12/2004, 587-90.
[D2] 8F2 for 1T1R, 5F2 for 1R cells.
[D3] K. Tsunoda, et al. "Low power and high speed switching of Ti-doped NiO ReRAM under the unipolar voltage source of less than 3V", IEDM 2007, 767-770
[D4] Estimated based on experimental data reported in Ref. [D1]: E~0.5*V*I*tw , for V=1 Volt, I=0.5mA , tw=10 ns
[E1] S. Dietrich, M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, M. Markert, R. Symanczyk, S. Bournat, and Gerhard Mueller.” A Nonvolatile 20Mbit
CBRAM Memory Core Featuring Advanced Read And Program Control.” IEEE J. Solid-State Ci
[E2] S. Liu, et al. “Electro-resistive Memory Effect in Colossal Magnetoresistive Films and Performance Enhancement by Post-annealing.” Mat. Res. Soc. Symp. Proc. vol. 648 (2001)
P3.26.1-8.
[E3] H. Y. Lee et al, "Lowpower and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM", IEDM 2008 , 297-300
[E4] C. Yoshida et al. "High speed resistive switching in Pt/TiO2/TiN film for nonvolatile memory application", Appl. Phys. Lett. 91 (2007) 223510
[E5] Obtained in ref. [G] from elevated temperature accelerated data retention measurements over 30 h.
[E6] Z. Wei et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism", IEDM 2008, 293-296
[E7] Electrochemical cell potentials control the write voltage. In appropriate combinations, 0.5 V will leave some safety margin. Read voltages will be significantly smaller.
[E9] Estimated based on experimental data reported in Ref. [E1]: E~0.5*V*I*t w , for V=0.6 Volt, I=10m A , tw=50 ns.
[F1] M. Fujimoto et al. “Resistivity and Resistive Switching Properties of Pr 0.7 Ca0.3 MnO3 thin Films.” Appl. Phys. Lett. 89 (2006) 243504.
[F2] S. T. Hsu, T. Li and N. Awaya. “Resistance Random Access Memory Switching Mechanism.” J. Appl. Phys. 101 (2007) 0245517.
[F3] Y. Watanabe, J.G. Bednorz, A. Bietsch, Ch. Gerber, D. Widmer, A. Beck, S. J. Wind. “Current-driven Insulator-conductor Transition and Non-volatile Memory in Chromium-
doped SrTiO3 Single Crystals.” Appl. Phys. Lett. 78, 2001, 3738.
[F4] C. Papagianni, Y. B. Nian, Y. Q. Wang, N. J. Wu, A. Igmatiev, “Impedance Study of Reproducible Switching Memory effect.” Non-Volatile Memory Technology Symposium, 15-
17 Nov. 2004, pp. 125-128.
[F5] S. Liu, et al. “Electro-resistive Memory Effect in Colossal Magnetoresistive Films and Performance Enhancement by Post-annealing.” Mat. Res. Soc. Symp. Proc. vol. 648 (2001)
P3.26.1-8.
[G1] R. Muller, S. De Jonge, K. Myny, D. J. Wouters, J. Genoe, and P. Heremans. “Organic CuTCNQ integrated in complementary metal oxide semiconductor copper back end-of-
line for nonvolatile memory.” Appl. Phys. Lett. 89 (2006) 223501.
[G2] L. P. Ma, J. Liu, and Y. Yang. “Organic electrical bistable devices and rewritable memory cells” Appl. Phys. Lett. v. 80, no. 16 (2002) 2997-2999.
[G3] Estimated based on experimental data reported in Ref. [S]: E~0.5*V*I*t w , for , for V=2 Volts, I=10mA , tw=10 ns.
[G4]Ma, L. P., Q. Xu, and Y. Yang. “Organic non-volatile memory by controlling the dynamic copper-ion concentration within organic layer”, Appl. Phys. Lett. 84.24 (2004) 4908–
4910.
[H1] A. DeHon, S. C. Goldstein, P. J. Kuekes, P. Lincoln. “Nonphotolithographic nanoscale memory density prospects.” IEEE Trans. Nanotechnol. v. 4, no. 2 (2005) 215-228.
[H2] W. Wu, G-Y. Jung, D. L. Olynick, J. Straznicky, Z. Li, X. Li, D. A. A. Ohlberg, Y. Chen, S-Y. Wang, J. A. Liddle, W. M. Tong, and R. S. Williams, “One-kilobit cross-bar molecular
memory circuits at 30-nm half-pitch fabricated by nanoimprint lithograp
[H3] J. E. Green, J. W. Choi, A. Boukai, Y. Bunimovich, E. Johnston-Halperin, E. Delonno, Y. Luo, B. A. Sheriff, K. Xu, Y. S. Shin, H-R. Tseng, J. F. Stoddart, and J. R. Heath. “A 160-
kilobit molecular electronic memory patterned at 1011 bits per square c
[H4] Chen Y., Ohlberg D.A.A., Li XM, Stewart D.R., Williams R.S., Jeppesen J.O., Nielsen K.A., Stoddart J.F., Olynick D.L., Anderson E.. “Nanoscale Molecular-switch Devices
Fabricated by Imprint Lithography.” Appl. Phys. Lett 82 (2003) 1610.
[H5] V. Meunier, S. V. Kalinin, and B. G. Sumpter, “Nonvolatile memory elements based on the intercalation of organic molecules inside carbon nanotubes.” Phys. Rev. Lett. 98
(2007) 056401.
[I1] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2005–7/1/2007.
Simulation results showing very low sub Reliability, low voltage operation remain an
threshold slopes indicate potential for low issue. Included in previous edition transition
Impact Ionization MOS IN power operation table
Potential to utilize gate modulated interband Low drive current still an issue. Included in
Tunnel FET IN tunneling to reduce subthreshold slope previous edition transition table
Included as a category of “1D devices” in
Carbon Nanotube FET IN previous version
Device
FET [A]
Typical example devices Si CMOS CNT FET Graphene Nanowire III-V FETs Ge FETs Unconventional
Nanoribbon FET geometries FinFET
Tri-gate FET
GAA FET
Local SOI
Cell Size Projected 100 nm [C] 100 nm [D] 100 nm 30 nm 15 nm 15nm 100 nm [C]
(spatial pitch) [B] Demonstrated 590 nm ~1.5 mm [E] 1.5 µ [J] ~1 µ [K] 40nm [R] 26nm [U] 300 nm [Y]
Density Projected 1.00E+10 4.50E+09 4.50E+09 1.00E+11 1.00E+11 1.00E+11 1E10 [C]
(device/cm2) Demonstrated 2.80E+08 4.00E+07 4.00E+07 1.00E+08 1.5E10 [S] 3E10 [V] 4.7E9[Z]
Projected 12 THz 6.3 THz [F] Not known 6.5 THz [L] Not known Not known 12 THz [C]
Switch Speed Demonstrated 1.5 THz 4GHz [G] 26 GHz[ I] 250 GHz [M] 2THz [T] 290GHz [W] > 200 GHz[A1]
Projected 61 GHz 61 GHz [D] 61 GHz [J] 100 GHz [N] Not known Not known 61GHz [C]
Circuit Speed Demonstrated 5.6 GHz 220 Hz [H] 22 kHz[J] 11.7 MHz [O] Not known Not known 8 GHz[A2]
Projected 3.00E-18 3.00E-18 3.00E-18 4E-20 [P] Not known Not known 3.00E-18
Switching Energy, J Demonstrated 1.00E-16 1E-11 [H] Not known 6.0 E-16 [Q] Not known 4.0E-15 [X] Not known
Binary Throughput, Projected 238 238 61 1.00E-04 Not known Not known 238
GBit/ns/cm2 Demonstrated 1.6 1.00E-08 Not known 1.20E-04 Not known Not known Not known
Operational Temperature RT RT RT RT RT RT RT
[A] For Si CMOS entry, parameters for high performance MPU are used: “Projected” (2022), “Demonstrated” (2007).
[B] The effective dimension that one transistor occupies on the MPU chip floor space. For CMOS MPU chips, the relation between cell size and Lg holds approximately constant by scaling: cell size =20Lg.
[C] Lg=5 nm.
[D] Size and circuit speed scaling of these structures is the same as the scaling of MOSFETs.
[E] J. Appenzeller, Y.-M. Lin, J. Knoch, P. Avouris. “Band-to-band Tunneling in Carbon Nanotube Field-Effect Transistors.” Phys. Rev. Lett., v. 93, no. 19 (2003) 196805.
[F] P. J. Burke. “AC Performance of Nanoelectronics: Towards a Ballistic THz Nanotube Transistor.” Solid-State Electron. v. 48 (2004) 1981-1986.
[G] A. Le Louarn, F. Kapche, J.-M. Bethoux, H. Happy, G. Dambrine V. Derycke, P. Chenevier, N. Izard, M. F. Goffman, and J.-P. Bourgoin, “Intrinsic current gain cutoff frequency of 30 GHz with carbon
nanotube transistors”, Appl. Phys. Lett. 90, 233108, (2007)..
[H] A. Javey, Q. Wang, A. Ural, Y.M. Li, H.J. Dai. “Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators.” Nano Lett. v. 2, no. 9 (2002) 929–932.
[I] Roman Sordan, Floriano Traversi, Valeria Russo, “ Logic gates with a single graphene transistor”, Appl. Phys. Lett. v. 94, no. 7, 073305 (2009).
[J]Yu-Ming Lin, Keith A. Jenkins, Alberto Valdes-Garcia, Joshua P. Small, Damon B. Farmer, and Phaedon Avouris, “Operation of Graphene Transistors at Gigahertz Frequencies”, Nano Letters, vol. 9 , no. 1,
[K] Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K.-H. Kim, and C. M. Lieber, “Logic gates and computation from assembled nanowire building blocks,” Science, v. 294, pp. 1313-1317, 9 Nov. 2001.
[L] Y. Li and C.-H. Hwang, “DC baseband and high-frequency characteristics of a silicon nanowire field effect transistor circuit,” Semicond. Sci. Technol., vol. 24, 045004, 2009.
[M] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan, and C. M. Lieber, “Ge/Si nanowire heterostructures as high-performance field-effect transistors,” Nature, vol. 441, pp. 489-493, 2006.
[N] R. Wang, J. Zhuge, R. Huang, Y. Tian, H. Xiao, L. Zhang, C. Li, X. Zhang, and Y. Wang, “Analog/RF performance of Si nanowire MOSFETs and the impact of process variation,” IEEE Trans. Elect. Dev., vol.
[O] R. S. Friedman, M. C. McAlpine, D. S. Ricketts, D. Ham, and C. M. Lieber, “High-speed integrated nanowire circuits,” Nature, vol. 434, no. 7037, p. 1085, Apr. 2005.
[P] J. Knoch, W. Riess, and J. Appenzeller, “Outperforming the conventional scaling rules in the quantum-capacitance limit,” IEEE Elect. Dev. Lett., vol. 29, no. 4, Apr. 2008.
[Q] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, and M. Radosavljevic, “Benchmarking nanotechnology for high-performance and low-power logic transistor
applications,” IEEE Trans. on Nanotechnology, vol. 4, no. 2, Mar. 2005
[R] D.-H. Kim et al., “Logic Performance of 40nm InAs HEMTs,” Tech. Dig. of IEDM, p629, 2007.
[S] 1/(80nm*80nm)
[V] Based on the gate length of 26nm, the pitch is assumed to be 52nm. The density is calculated with the pitch of 52nm (1/(52nm*52nm)).
[W] J. Mitard et al., “Impact of EOT scaling down to 0.85nm on 70nm Ge-pFETs technology with STI,” VLSI Tech Dig., p82, 2009. Id=1mA/um@1.2V, Lg=70nm, EOT=0.85nm, CV/I = 3.4ps = 290GHz
[Y] FinFET with Lg = 15 nm has been reported, and Cell size of 20Lg is employed for Unconventional Geometories.
[Z] Kawasaki H et al.: IEDM Tech. Dig. (2008) 237-280. 0.128 m2 6T FinFET SRAM has been achieved, therefore, the dedicated mean area for one transistor should be 0.128 / 6 = 0.0213 m2
[A1] Kaneko A et al.: IEDM Tech Dig. (2006) 893-896. Sub-5 ps ring oscillator operation has been reported with Dopant-Segregated Schottky S/D FinFET.
[A2] Wanbacq P et al.: ESSDERC Tech. Dig. (2006) 53-56. Tunable oscillator with 45 nm FinFET has been reported with operating frequency of about 8 GHz.
[A3] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2007–7/1/2009.
~1mm (channel
Demonstrated: 70 nm,
Demonstrated 590 nm Not known length) ~200 nm [P,Q] 900 nm
100nm [B,C]
2000 nm for Spin FET[M]
Not known: ~1E10
channel length 1E10[same as
Projected 1.00E+10 1.00E+10 6.00E+10 1.00E+10
Density (device/cm2) scalable down to CMOS] [I] for spin MOSFET [L]
20nm [D]
Demonstrated 2.80E+08 ~1E10 2.50E+07 Not known
Not known - Limited Not known ~2E9 1 /cm**2 W2
Identical to by the ferroelectric ~10 THz or less
Projected 12 THz Not known CMOSFET- with Ge, response time, for spin MOSFET 10 THz [R] 1 GHz [Y]
SiGe [E],[F],[G] depends on the [N]]
Switch Speed Si/Ge/InAs tunneling ferroelectric material
30GHz
source:
Demonstrated 1.5 THz Not known Not known 2 THz [S] 0.18 GHz [Z]
1GHz/1THz/3THz
for Spin FET[M]
[A] Not know - Limited
Identical to by the ferroelectric ~10GHz or less
Projected 61 GHz Not known CMOSFET- with Ge, response time, for spin MOSFET 2 GHz [O] 1 GHz
SiGe [E],[F],[G] depends on the [M]
Circuit Speed ferroelectric material
Not known:
Demonstrated 5.6 GHz will depend on the Not known Not known Not known 1 MHz [T] .18 GHz
source material used
Identical to 1E-17-1E-18 1×10–18 [O]
Projected 3.00E-18 Not known CMOSFET- with Ge, Not known for spin MOSFET 5E -17 J [A1,A2]
SiGe [E],[F],[G] [>1.5×10–17 ] [U]
[M]]
Si/Ge/InAs tunneling
Switching Energy, J 8×10–17 [V]
source:
Demonstrated 1.00E-16 90/90/3000E-18 Not known Not known Not known [>1.3×10–14] [W]
J/um at VDD=0.5V,
L=20nm [A]
Binary Throughput,
Projected 238 Not known Not known Not known ~200 10 10
GBit/ns/cm2
Research Activity [A4] 55 23 2 83 67 47
[B]: W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. King Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, Aug. 2007,
pp. 743–745.
[C]: T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, “Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With Record High Drive Currents and 60mV/dec Subthreshold Slope”,
Tech. Dig. IEEE IEDM, 2008, pp. 947-949.
[D]: K. Boucart and A. M. Ionescu, Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric, Solid-State Electronics, Volume 51, Issues 11-12, November-December 2007, pp. 1500-1507.
[E] K. Gopalakrishnan, P.B. Griffin and J. Plummer,”I-MOS: A Novel Semiconductor Device with a Subthreshold Slope lower than kT/q”, IEEE International Electron Devices Meeting, p. 289-292,
December 2002.
[F]F. Mayer, C. Le Royer, J.-F. Damlencourt, K. Romanjek, F. Andrieu, C. Tabone, B.Previtali, and S. Deleonibus, “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible Tunnel FET
performance”, IEDM 2008, San Francisco, Dec 15-17, 2008. Digital Object Identifier 10.1109/IEDM.2008.4796641.
[G]F. Mayer, C. Le Royer, G. Le Carval, L. Clavelier and S.Deleonibus, ”Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit”, IEEE Transaction On Electron
Devices, Vol.53, Issue 8, p. 1852-1857, August 2006.
[H]: S. Salahuddin and S. Datta, “Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices, ” Nanoletters, Vol. 8, No. 2, 2008, pp. 405-410.
[I]: G.A. Salvatore, D. Bouvet, A.M. Ionescu, “Demonstration of subthrehold swing smaller than 60mV/decade in Fe-FET with P(VDF-TrFE)/SiO2 gate stack, ” Techn. Digest of IEDM 2008.
[J] S. Mathews, et.al, "Ferroelectric Field Effect Transistor based on Epitaqxial Perovskite, Science, vol 276, No 5310, P 238-240, April 1997
[K] The evaluations of spin FET in this table are limited for Datta-Das spin FET, although various type of spin FET has been proposed.
[L] The basic structure of spin MOSFET is the same as metal S/D MOSFETs. The same scalability as MOSFETs is expected for spin MOSFET.
[M] S. Bandyopadhyay and M. Cahay, “Reexamination of some spintronic field-effect device concepts”, Appl. Phys. Lett. 85, 1433 (2004)
[N] Device/circuit performance of spin MOSFTE is expected to be the same as Si CMOS devices, when the magnetization configuration of the source and drain is parallel. However, the device/circuit
performance depends on magnetization configurations of the source and drain. In the antiparallel magnetization configuration, the current drive capability is reduced and thus circuit performance degrades.
Note that this magnetization-configuration-dependent output characteristics is essential for reconfigurable logic and nonvolatile logic circuits.
O] For SET logic circuits, device size/density, circuit speed, switching energy and operational temperature are interdependent. The values in the table were derived for a complex circuit operating at 1 GHz:
R. H. Chen, A. N. Korotkov, and K. K. Likharev. “Single-electron Transistor Logic.” Appl. Phys. Lett. v. 68, no 14 (1996) 1954.
[P] M.C. Lin, Aravind K., Wu C.S., et al. “Cyclotron Localization in a Sub-10-nm Silicon Quantum Dot Single Electron Transistor.” Appl. Phys. Lett. 90 (3): Art. No. 032106 JAN 15 2007
[Q] M. Hofheinz, Jehl X., Sanquer M., et al. "Simple and controlled Single Electron Transistor Based on Doping Modulation in Silicon Nanowires." Appl. Phys. Lett. 89 (14): Art. No. 143504 OCT 2 2006.
[R]For SET logic circuits, device size/density, circuit speed, switching energy and operational temperature are interdependent. The values in the table were derived for a complex circuit operating at 1 GHz:
R. H. Chen, A. N. Korotkov, and K. K. Likharev. “Single-electron Transistor Logic.” Appl. Phys. Lett. v. 68, no 14 (1996) 1954.
[P] C. Hof, et al. “Manipulating Single Electrons with a Seven-Junction Pump.” IEEE Trans. Instr. Measur. 54 (2005)
[S]] In notation [Q] above, the reported number of 2 THz for “intrinsic speed” of an experimental SET was derived from capacitance measurements, and not from time-dependent ones. Experimentally, GHz
operation was reported in A. Fujiwara et al. “Nanoampere charge pump by single-electron ratchet using silicon nanowire metal-oxide-semiconductor field-effect transistor”, Appl. Phys. Lett. 92 042102
(2008).
[T]C. Hof, et al. “Manipulating Single Electrons with a Seven-Junction Pump.” IEEE Trans. Instr. Measur. 54 (2005) 670-672.
[U]The value in the [ ] is the value that includes cooling energy. If an ideal Carnot refrigerator is used for cooling to the operation temperature Tc, the total switching energy ccswTEE300⋅>, where Ec is the
net switching energy, when cooling energy is not taken into account.
[V] M. Kobayashi, Hiramoto T. "Large Coulomb-blockade Oscillations and Negative Differential Conductance in Silicon Single-Electron Transistors with [100]- and [110]-Directed Channels at Room
Temperature." Jap. J. Appl. Phys. Pt 1- 46 (1): 24-27 JAN 2007.
[W] C. Dubuc, Beauvais J, Drouin D. "Single-electron Transistors with Wide Operating Temperature Range." Applied Physics Letters 90 (11): Art. No. 113104 MAR 12 2007.
[X] Jang et al., “Fabrication and characterization of a nanoelectromechanical switch with 15-nm-thick suspension air gap,” Appl. Phys. Lett. 92, 103110 (2008).
[Y] Kinaret et al., “A carbon-nanotube-based nanorelay,” Appl. Phys. Lett. 82, 1287-1289 (2003).
Z] Kaul et al., “Electromechanical carbon nanotube switches for high- frequency applications,” Nano Lett. 6, 942-947 (2006).
[A1] Pruvost et al., “Design optimization of NEMS switches for suspended- gate single-electron transistor applications,” IEEE Trans. Nanotechnology, 8, 174-184 (2009).
[A2] Yousif et al., “CMOS considerations in nanoelectromechanical carbon nanotube-based switches,” Nanotechnology 19, 285204 (2008).
[A4] The number of referred articles in technical journals that appeared in the Science Citation Index database for 7/1/2007–7/1/2009.
Collective spin devices Moving Domain wall Atomic switch Molecular Pseudospintronc Nano magnetic
First Year of IC Production 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
CMOS Extension Devices
CNT and Graphine Devices
Controlled growth
Chirality of CNTs
Semiconducting vs metallic
n/p Doping Control
Diameter of CNTs
Direction of CNTs
Wall thickness - Single wall
Graphene Epitaxy
Edge Control of Graphene
Bandgap Control of Graphene
Ohmic contacts
Hi-K Gate dielectric & gate metal
Heterobandgap junction structures
NEMS
Molecular Electronics
Graphine Devices
Veselago Electron Lens
Pseudospintronics Narrow Options
Quantum Interference
Quantum Hall Effect
Bi-layer structures
This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.
Research Required
Development Underway
Qualification / Pre-Production
Continuous Improvement
Nanomagnetic Logic (MQCA) Collective Spin CMOS compatible, natural memory interface to Logically complete, systolic/streaming
MRAM architectures
Interband-Tunneling FETs Charge CMOS compatible, low power, fast, scaling limitation Drop-in replacement for CMOS devices
Single Electron Transistors Charge Power/voltage/time efficient Supports Binary Decision Diagram architectures
Challenge Issues
Cost per bit must go down dramatically for solid state disk to succeed
Cost
rotating media
DRAM and Flash processes too complex to create an integrated SOC
device
Fill factor (% of memory chip in memory core) too low
Energy Optimized Memory Hierarchy Minimize average energy/access from register file to disk
Demonstration of high mobility n and p channel alternate channel materials co-integrated with high κ dielectric
Demonstration of high mobility n and p channel carbon (graphene or carbon nanotubes) FETs with high on-off ratio
Integration of alternate channel materials with co-integrated with high κ dielectric and low resistance contacts
high performance Selective growth of alternate channel materials in desired locations with controlled properties and directions on
silicon wafers (III-V, Graphene, Carbon nanotubes and semiconductor nanowires)
Achieving low contact resistance to sub 16nm scale structures (graphene and carbon nanotubes)
Growth of high κ dielectrics with unpinned Fermi Level in the alternate channel material
Ability to pattern sub 16nm structures in resist or other manufacturing related patterning materials (resist, imprint, self
assembled materials, etc.)
Control of CNT properties, bandgap distribution and metallic fraction
Data and models that enable quantitative structure-property correlations and a robust nanomaterials-by-design
capability
Placement of nanostructures, such as CNTs, nanowires, or quantum dots, in precise locations for devices,
interconnects, and other electronically useful components
Controlled assembly of nanostructures
Control of line width of self-assembled patterning materials
Control of registration and defects in self-assembled materials
Correlation of the interface structure, electronic and spin properties at interfaces with low-dimensional materials
Characterization of low atomic weight structures and defects (e.g., carbon nanotubes, graphitic structures, etc.)
Characterization of nanostructure-property
correlations
Characterization of spin concentration in materials
Characterization of vacancy concentration and its effect on the properties of complex oxides
Materials ERD Memory ERD Logic Lithography FEP Interconnects Assembly and Package
Inorganic-organic hybrid
Selective depositions
resist
Enhanced dimensional
Self Assembled Materials Selective deposition Selective deposition High performance capacitors
control
Self Assembled Molecule
Deterministic doping
Barriers
Spin FET
STT MRAM Ferromagnetic Spin MOSFET
Spin Materials
layers Collective Spin Device Spin Transport Local
Moving Domain Wall Interconnects TBD
Nanomagnetic MQCA
Magnetoelectric materials
1T Fe FET
(Spin materials)
EUV Inorganic-Organic
High performance capacitors
STT MRAM tunnel barrier & Hybrid Resist
magnetic pinning layer Novel phase change
Charge Trapping Passivation dielectrics
Complex Metal Oxides &
Transition Metal Oxides
Mott Transition Memory
Material & Earliest Potenial Insertion Potential Material Value Key Challenges Target/Goal Status
High electron mobility(InGaAs, InSb) Achieving low defect density in selective deposition on silicon Free of dislocations, twins, phase Dislocations have been reduced but other
Strained III-V Higher Hole Mobility separation defects need attention
(Scott UF)
Integration of high κ dielectric with unpinned III-V Fermi level Dit<1E12/( eV-cm) GdO: Interface control has been achieved
by III-V surface passivation and by
interface layers
High electron & hole mobility devices Hole mobility >3000cm2/V-sec
III-V Semiconductors Quasi Ballistic Velocity > Electron mobility >10,000cm2/V-sec [A]
Low contact resistance Contact Resistivity <1 e-8 W-cm2
Satisfactory gate control has been achieved
with standard III-V contact metallurgies
Control of stress in process and assembly and packaging No mobility degradation after
assembly & packaging Stress effects have not been measured yet
Adequate hole mobility (~3000cm2/V- Integration of high κ dielectric with unpinned Ge Fermi level Dit<1E12/( eV-cm) Fermi level pinning causes are still an open
sec)* issue
High hole and electron mobility in a device Electron Mobility >10,000
cm2/V-sec
Ge Hole mobility
>3000cm2/V-sec Quasi Ballistic
Velocity >
Low contact resistance Contact Resistivity <1 e-8 W-cm2 Metal Schottky S/D contacts need to be
investigated
High electron and hole mobility Activating Ge dopants requires higher temperature than III-V Meet 400C implant activation for Co-implant with He may reduce activation
processing Ge drive-in energy
Forming low resistance contacts to Ge and III-V compounds Explore new Schottky barrier S/D
contacts and low-T processing Process compatible Schottky S/D contact
metallurgies need to be investigated
Co-integration of III-V and Ge Conductivity must not degrade when embedded in a dielectric New scattering effects must be
understood in nanoscale channels Work on phonon and interface scattering
just beginning
Low contact resistance Contact Resistivity <1 e-8 W-cm 2
Material & Earliest Potenial Insertion Potential Material Value Key Challenges Target/Goal Status
High gate control of leakage current and Ability to grow nanowires in desired locations and directions Selectively deposit NW's in either Initial NW deposition in controlled
possibly low surface surface scattering vertical or horizontal locations locations has been demonstrated but not for
monolithic processing
Catalyst compatible with CMOS processing Metal catalysts cannot introduce Initial NW deposition in controlled
deep level defects into the locations has been demonstrated but not for
channels and S/D's monolithic processing
Ability dope nanowire channel and S/D regions Demonstrate conrolled doping of
NW's wirh atomically sharp
Si or Ge Nanowires boundaries Initial co-linear and surround NW doped
sructures have been grown by CVD on a
one-ff basis but not monolithically
Ability to achieve high electron and hole mobility on silicon Identify and understand mobility
Mobilities of 50% of bulk values have been
degradation processes in NW's
achieved in Si and Ge NW's
[A] M. K. Hudait, G. Dewey, S. Datta, J. M. Fastenau*, J. Kavalieros, W. K. Liu*, D. Lubyshev*, R. Pillarisetty, W. Rachmady, M. Radosavljevic, T. Rakshit and Robert Chau. Heterogeneous Integration of Enhancement Mode
In0.7Ga0.3As Quantum Well Transistor on Silicon Substrate using Thin (=2um) Composite Buffer Architecture for High-Speed and Low-Voltage (0.5V) Logic Applications,” International Electron Devices Meeting (IEDM) Technical
Digest, 2007, pp. 625-628.
[B] S. Kim,_J. Nah, I. Jo, D. Shahrjerdi, L. Colombo, Z. Yao, E. Tutuc, and S.K. Banerjee. “Realization of a high mobility dual-gated graphene field-effect transistor with Al2O3 dielectric.” Applied Physics Letters, vol. 94, pp. 062107,
2009.
Application Requirements Ferromagnetic Metal Half Metals Compound Ferromagnetic Dilute Magnetic Wide Bandgap
Metals Semiconductor Magnetic
Semiconductors
Ferromagnetic Spin Injector High Remnant Magnetization Co, Fe, Ni and alloys >50% LSMO Tc=350 Cu2MnAl, Cu2MnSi, etc. Ga(Mn(As) Tc TiO2: Co, SnO2:Co,
(>400K) RM 400K 195K
etc.
High injection efficiency Acceptable through Schottky Excellent below Tc Excellent below Tc Unknown: Low
Barrier and tunnel dielectric Carrier Mobility
[B] Y. Huai, F. Albert, P. Nguyen, M. Pakala, and T. Valet. "Observation of spin-transfer switching in deep submicron-sized
and low-resistance magnetic tunnel junctions." Appl. Phys. Lett., vol. 84, pp. 3118, 2004.
[C] Y. Ishii, H. Yamada, H. Sato, and H. Akoh, M. Kawasaki, Y. Tokura. "Perovskite manganite magnetic tunnel junctions with enhanced coercivity
contrast." Appl. Phys. Lett., vol. 87, pp. 022509, 2005.
[D] N. Nepal, M. Oliver Luen, J.M. Zavada, S.M. Bedair, P. Frajtag, and N. A. El-Masry. "Electric field control of room temperature ferromagnetism in III-N dilute magnetic semiconductor films.", Appl. Phys. Lett.,
vol. 94, pp. 132505, 2009.
[E] L.W. Martin, Y.-H. Chu, M.B. Holcomb, M. Huijben, P. Yu, S.-J. Han, D. Lee, S.X. Wang, and R. Ramesh. "Nanoscale Control of Exchange Bias with BiFeO3 Thin Films." Nano Letters, vol. 8, pp. 2050-2055,
2008.
[F] B. Huang, D.J. Monsma, I. Appelbaum. "Experimental realization of a silicon spin field-effect transistor." Appl. Phys. Lett., vol. 91, pp. 072501, 2007.
[G] N. Tombros, C. Jozsa, M. Popinciuc, H.T. Jonkman, and B.J. van Wees. "Electronic spin transport and spin precession in single graphene layers at room temperature.", Nature, vol. 448, pp. 571-574, 2007.
[H] K. Tsukagoshi, B.W. Alphenaar, and H. Ago, "Coherent transport of electron spin in a ferromagnetically contacted carbon nanotube." Nature, vol. 401, pp. 572, 1999.
ITWG
INDEX
Carbon Nanotubes or patterned High on/off ratio Stiction required for a stable state requires high voltage for
thin film structures switching. Operation below 1V
Contact reliability due to frictional wear in switching Cycling endurance 1E5
Nanoelectromechanical Memory write >1E9 cycles
Scalability
Reliable operation Nonhermetic packaging
Ferromagnetic Metal: Co-Fe High remnant Scaling the etch process to small dimensions without shorting the
magnetization tunnel barrier TBD
STT MRAM Tunnel Barrier: MgO High spin selectivity Identifying a tunnel barrier with higher spin selectivity TMR>1000% MgO~70%
Pinning Layer: Complex Metal Low leakage passivation of tunnel barrier: stable through 1E5 Write <10% increase in
Oxide Cycles 1E5cycles 1E12 cycles
Macromolecular Memory Polymer Low Cost Reliable switching mechanism 1E5 Cycles >1E6 cycles
Metallic Nanoparticles Determine the scalability of charge storage with nanoparticle size
Molecules High Density Reliable switching mechanism 1E5 Cycles ~2E3 cycles
Molecular Memories Contact metal Deposition of the top electrode without changing the molecule
TBD
Contacts that don't migrate in the applied fields No metal migration
Complex Metal Oxides and Scalability and Determining whether the electronic transition can reversibly occur
Transition Metal Oxides: e.g. Nd1- nonvolatility with or without the first order structural phase transition.
Determining the thermal control required for reverisible operation
Mott Effect Memory SrxMnO3 and VO2
x
Nanothermal Memory Transition metal oxides Scalability and Determine the relationship between the material-related process Cycling endurance 1E5 >1E9 cycles [A]
nonvolatility (e.g. deposition, etching processes) and the reliablity of the write Retention >10 yrs
memory performance (e.g. endurance, retention) at 85°C
[A] Z. Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S. Mitani, S. Fujii, K.Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa,
H. Sugaya, and T. Takagi, R. Yasuhara, K.Horiba, H. Kumigashira, and M. Oshima. “Highly Reliable TaOx ReRAM and Direct Evidence of Redox Reaction Mechanism.”Tech. Dig. Int. Electron Devices Meet., 2008,
pp.293-296, 2008.
Positive Non Chemically Amplified Resist Potential decoupling of resolution & LER Requires a high intinsity image and need to improve etch E0<50mJ/cm2[a]
resistance and pattern collapse margin
Negative Tone Resist Reduce LER with high resoution Poor performance with phase shift mask, microbridging, and 50nm L/S process margin close to positive resist[b]
pattern collapse margin
193nm Pitch Division Spacer Patterning Use Conventional Materials Multiple process steps and lithography steps required. No ERM
Pattern collapse margin
Double Exposure Resist Single Track Double Exposure Identifying a two exposure molecule (D2) that reverts to the Modified tethered bromo-anthracene system showed evidence of D2
initial state without the second exposure and integrating in a behavior in solution, and apparent reversibility without acid release[d]: Need
resist in the required timeframe and pattern collapse margin* to demonstrate in resist
EUV Resist Positive Chemically Amplified Resist Evolutionary Solution Ability to simultaneously achieve (resolution, sensitivity, line No ERM
edge roughness and pattern collapse margin*
Negative Tone Cationic Resist Reduced Sensitivity to Flare Microbridging and pattern collapse margin* Molecular Glass(MG) Fullerene achieved 20nm hp with LER 2.5-4.5nm with
e-beam (11μC/cm2)[e], MG-Epoxide achieved 25nm hp with low LER e-
beam (38 to 22 μC/cm2)[f]
Negative Tone Non Chemically Amplified Resist Reduced outgassing Achieving resolution, senstivity, LER, etch resistance without Resolved 60nm isolated lines with EUV exposure of 5-6 mJ/cm 2 with lower
microbridging, and pattern collapse margin* outgassing than SELETE Std.[g]
Inorganic and Inorganic-Organic Hybrid Resist High contrast and resistance to pattern collapse Achieving resolution, senstivity, LER,, and potential HSQ printed 20nm hp and LER<2nm with EUV interference [h]
defectivity issues with inorganic materials Zr and Hf based resist printed 36nm hp LER <2nm and RIE etch resistance
7X higher than thermal SiO2 [i]
Non Chemically Amplified Resist Reduced outgassing Achieving required sensitivity, resolution, etch resistance, Resolution of 35nm L/S[j]
and pattern collapse margin*
Best Reported
Directed Self Assembly Lithography Extension 1. Neutral Surface Layer >Higher density features than lithography >Reduced >Ability to generate required features at a minimum of 2× Minimum Feature Size: 7 nm (lamellar pattern)[k]
2. Assembly Control line edge roughness higher density than achievable by best direct lithographic
-Graphoepitaxy methods LER: 2.2 nm (on 24 nm linewidth lamellar pattern)[l]
-Surface Chemical Pattern >Ability to achieve low defect density
-Hybrid Resist >Annealing times of a few minutes for all patterns Defect Density: 1 part in 10000 (sparse chemical patterning of hexagonal
3. Supramolecular Options >Reducing process array of cylinders) [m]
-Di or Tri Block Co-polymers complexity Minimum Annealing Time: 1 minute (dense chemical patterning of lamellar
-Di or Tri Block-co-polymer/monomer mixtures >Ability to align features to previous structures structure [n]
4. Fast Annealing Options >Etch selectivity Patterns Demonstrated (Y/N)
-Above Tg Double Density Lines Y [o]
-Solvent Annealing Double Density Square Contacts N
Isolated Lines Y [o]
Isolated Contacts Y [p]
*Pattern collapse solutions need to be simple to implement or use existing process base
[b] T. Ando, S. Abe, R. Takasu, J. Iwashita, S. Matsumaru, R. Watababe, K. Hirahara, Y. Suzuki, M. Tsukano and T. Iwai. ”Topcoat-free ArF Negative Tone Resist.” SPIE, vol. 7273, pp.
727308, 2009.
[c] S. Tarutani, T. Hideaki, and S. Kamimura. “Development of materials and processes for negative tone development toward 32-nm node 193-nm immersion double-patterning process.”
SPIE, vol. 7273, pp. 72730C, 2009.
[d] R. Bristol, D. Shykind, S. Kim, Y. Borodovsky, E. Schwartz, C. Turner, G. Masson, K. Min, K. Esswein, J.M. Blackwell, N. Suetin. “Double-Exposure Materials for Pitch Division with
193nm Lithography: Requirements, Results.” Proc. SPIE, vol. 7273, pp. 727307, 2009.
[e] J. Manyam, M. Manickam, J.A. Preece, R.E. Palmer, A.P.G. Robinson. “Low Activation Energy Fullerene Molecular Resist.” SPIE, vol. 7273, pp. 72733D, 2009.
[f] R.A. Lawson, L.M. Tolbert, T.R. Younkin, C.L. Henderson, “Negative-Tone Molecular Resists Based on Cationic Polymerization.” SPIE, vol. 7273, pp. 72733E, 2009.
[g] M. Shirai, K. Maki, H. Okamura, K. Kaneyama, T. Itani. “Non-Chemically Amplified Negative Resist for EUV Lithography.” SPIE, vol. 7273, pp. 72731N, 2009.
[h] Y. Ekinci, H.H. Solak, C. Padeste, J. Gobrecht, M.P. Stoykovich, P.F. Nealey. “20 nm Line/space patterns in HSQ fabricated by EUV interference lithography.” Microelectronic
Engineering, vol. 84, pp. 700, 2007.
[i] J. Stowers, D.A. Keszler. “High resolution, high sensitivity inorganic resists.” Microelectronic Engineering, vol. 86, pp. 730-733, 2009.
[j] A.K. Whittaker, I. Blakey, J. Blinco, K.S. Jack, K. Lawrie, H. Liu, A. Yu, M. Leeson, W. Yeuh, T. Younkin. “Development of Polymers for Non-CAR Resists for EUV Lithography.”
SPIE, vol. 7273, pp. 727321, 2009.
[k] "Patterning sub-10 nm line patterns from a block copolymer hybrid", Sang-Min Park, Oun-Ho Park, Joy Y Cheng, Charles T Rettner and Ho-Cheol Kim, Nanotechnology 19 455304
(2008).
[l] "Pattern transfer using poly(styrene-block-methyl methacrylate) copolymerfilms and reactive ion etching" Chi-Chun Liu , Paul F. Nealey, Yuk-Hong Ting and Amy E. Wendt, J. Vac.
Sci. Technol. B 25 1963 (2007).
[m] "Density Multiplication and Improved Lithography by Directed Block Copolymer Assembly", Ricardo Ruiz,Huiman Kang, François A. Detcheverry, Elizabeth Dobisz,Dan S. Kercher,
Thomas R. Albrecht, Juan J. de Pablo and Paul F. Nealey, Science 321, 936 (2008)
[n] Rapid Directed Assembly of Block Copolymer Films at Elevated Temperatures" Adam M. Welander, Huiman Kang, Karl O. Stuen, Harun H. Solak, Marcus Müller, Juan J. de Pablo
and Paul F. Nealey, Macromolecules 41, 2759 (2008) :
[o] Directed Self-Assembly of Block Copolymers for Nanolithography: Fabrication of Isolated Features and Essential Integrated Circuit Geometries, Mark P. Stoykovich, Huiman Kang,
Kostas Ch. Daoulas, Guoliang Liu, Chi-Chun Liu, Juan J. de Pablo,
Marcus Müller and Paul F. Nealey, ACS Nano, 1, 168 (2007).
[p] Creation of sub-20-nm contact using diblock copolymer on a 300 mm wafer for complementary metal oxide semiconductor applications, Wai-kin Li and Sam Yang, J. Vac Sci Tch B 25
1982 (2007)
Ability to selectively protect materials during etch Ability to design polymer brushes to selectively coat
Selective Etch
or cleaning operations and protect new materials against chemical etches
TBD
Low defect density
Clean and Surface Prep Compatility with existing cleans
Easy removal
Uniformity
Contacts Lower contact resistivity
compatibility with silicon CMOS Materials TBD
Application Requirements Carbon Nanotubes Carbon Nanotubes Carbon Nanotubes (Multiwalled) Carbon Nanotubes
(Single Walled) (Single Walled) Challenges (Multiwalled)
Challenges Status Status
1E14 metallic tubes/cm2 inter- No data available on the density Need of 5-10E12 tubes/cm2, tube Ability to grow in-situ and integrate 1E12
tube distance: 0.68 nm; tube diameter <5-3 nm vertically aligned tubes/cm2 in 150 nm vias with
diameter < 1.1 nm. repeatable yield[A]
High density in small vias Need to develop new catalytic
systems.
Need reliable and reproducible Pd to date is the best metal to contact Need to produce direct metallic Pd to date is the best metal to contact nanotubes.
ohmic contacts. nanotubes.[B] contacts to all the shells to [B]
Contacting SWCNTs with minimize risks of resistance, local
Defect-free metal contacts diameter <1.5 nm needs to be heating, and electromigration.
improved.
Need to increase metallic content. No Data Availiable. Must achieve a high density of Resistances down to 0.6 Ohm in 2 µm diameter
Need to MWNTs and a low contact vias filled with MWCNTs have been reported;
understand how defects, structure resistance between CNTs and lowest documented resistance for an array of
and dielectric interface affect metal contacts. MWCNTs in a 2.8 µm (60 nm high) via is 0.05
Effective Resistivity nanotube resistance. Ohm.[C]
Vias
Need a process and catalyst to Only purification in liquid to date. [D] Not an Issue: All MWCNTs Not Applicable, all MWCNTs are metallic
grow dense arrays of metallic behavior is metallic.
SWCNTs with diameter < 1.1 nm.
Needs experiments to determine No Data Availiable. Need to increase density of No Data Availiable
thermal conductivity of CNT vias. Intrinsic CNT thermal resistance is low. MWNTs. Intrinsic CNT thermal resistance is low.
Reduce Need to decrease thermal
Thermal behavior thermal interface resistance. Thermal interface resistance may limit resistance between CNTs and Thermal interface resistance may limit
performance contacts performance
Application Requirements Carbon Nanotubes Carbon Nanotubes Carbon Nanotubes (Multiwalled) Carbon Nanotubes
(Single Walled) (Single Walled) Challenges (Multiwalled)
Challenges Status Status
Need to achieve same densities of CNTs can be grown in specific locations Need to achieve same densities of CNTs can be grown in specific locations with
metallic SWCNTs as with vertical with patterned catalyst[E] MWCNTs as per vertical vias. patterned catalyst. [E]
vias. CNTs have been grown horizontally in The big issue is growing them in predefined
templating materials (e.g. zeolites, etc.)[F] directions.
Ability to grow in controlled
locations The big issue is growing them in predefined
directions.
Over long distances (> 20 µm) Growth in a zeolite template may be most Need to achieve same high Directional growth of a bundles of MWNTs is
alignment <200 arcsec is required. compatible with interconnects, but has a densities of MWCNTs as per reported. Need higher growth rate. [I]
very low maturity.[F] vertical vias to achieve a bundle
Other options: growth.
Growth in electrical field: Low accuracy Need to increase the growth
[G] speed of MWNTs at a low CVD
Ability to grow in controlled
Growth along quartz crystal steps: may be growth temperature..
directions
difficult to apply to interconnects. [H]
Need faster CNT growth rate.
Interconnects
Same as for the vias, but more No progress reported Same as for vias, but more No progress reported
Defect-free metal contacts difficult with horizontal difficult with horizontal
interconnects. interconnects.
Same as for vias Progress reported in liquid purification, but Not an Issue All MWCNTs are metallic
Control of chirality requires ex-situ assembly [D]
Thermal behaviour Same as for vias No progress reported Same as for vias No progress reported
Need to achieve nanotube No progress reported Need to achieve same densities of No progress reported
densities in same orders of MWCNTs as with vertical vias.
magnitude as for vias. Need to improve the quality of
Effective resistivity CNTs to achieve longer ballistic
length.
Application Requirements Carbon Nanotubes Carbon Nanotubes Carbon Nanotubes (Multiwalled) Carbon Nanotubes
(Single Walled) (Single Walled) Challenges (Multiwalled)
Challenges Status Status
[B] W. Kim, A. Javey, R. Tu, J. Cao, Q. Wang, and H. Dai. “Electrical contacts to carbon nanotubes down to 1 nm in diameter.” Appl. Phys. Lett., vol. 87, pp. 173101, 2005.
[C] D. Yokoyama, T. Iwasaki, T. Yoshida, H. Kawarada. “Low temperature grown carbon nanotube interconnects using inner shells by chemical mechanical polishing.” Appl.
Phys. Lett., vol. 91, pp. 263101, 2007.
[D] M.S. Arnold, A.A. Green, J.F. Hulvat, S.I. Stupp, and M.C. Hersam. “Sorting carbon nanotubes by electronic structure using density differentiation.” Nature
Nanotechnology, vol. 1, pp. 60-65, 2006.
[E] A. Javi and H. Dai. "Regular Arrays of 2 nm Metal Nanoparticles for Deterministic Synthesis of Nanomaterials." Journal of the American Chemical Society, vol. 127, pp.
11942-11943, 2005.
[F] N. Wang, Z. K. Tang, G. D. Li and J. S. Chen. “Single-walled 4 Å carbon nanotube arrays.” Nature, vol. 408, pp. 50, 2000.
[G] A. Ural, Y. Li, and H. Dai. “Electric-field-aligned growth of single-walled carbon nanotubes on surfaces.” Appl. Phys. Lett., vol. 81, pp. 3464, 2002.
[H] K. Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H. S. P. Wong, and C. Zhou. “CMOS-Analogous Wafer-Scale Nanotube-on-Insulator
Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes.” Nano Letters, vol. 9, pp. 189, 2009.
[I] Y. Awano, “Carbon Nanotube Technologies for LSI via Interconnects ”, IEICE Transactions on Electronics E89-C(11), pp.1499-1503, 2006 or M. Nihei, D. Kondo, A.
Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti and Y. Awano, “Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner
shells”, IEEE 2005 International Interconnect Technology Conference, pp.234-6, 2005.
ITWG
INDEX
Table ERM11 Assemby and Packaging ERM Challenges
Application ERM Important Properties Key Challenges Target/Goal Status
Need to avoid cracking in bending Using nanoparticles, low CTEs can be achieved, but
stresses with thin silicon, CTE the viscosity goes up upon addition of nanoparticles
between silicon and the flexible and their dispersion is difficult to control at high
Mold Compound Next generation MC substrate and high adhesion to IC loadings. In order to achieve high toughness [to Control dispersion, dispensability of Some progress seen for oxide based
materials. Flow compatible with flip withstand bending stress], filler-matrix adhesion nanoparticle based composites at nanoparticles but for limited set of
chip underfill to enable one step (UF needs to be strong (Improved Moisture high loading; tailor filler-matrix filler-matrix systems; not seen
and Mold). Performance) interface to improve toughness specifically for UF or mold
(Improved Moisture Performance) compound
Novel Macromolecules
other Metal Nanotubes
Metal Nanoparticles
Nanowires
Graphene
Ge & III-V
Ni, etc.)
Application
Process Materials
Lithography
Device: Logic
Interconnect
Packaging
LEGEND
Earliest Potential Insertion Current Apps 3-5 yrs 5-10 yrs 10-15 yrs 15+ yrs Not on the Roadmap