METODO MAPAS DE KARNAUGH

Proteus.
F1
F2
f3

QII.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( A,B,C,D,E : in STD_LOGIC;
F1,F2,F3 : out STD_LOGIC);
end RLHG;

architecture Behavioral of RLHG is

SIGNAL UNO : STD_LOGIC_VECTOR (3 DOWNTO 0);

SIGNAL DOS : STD_LOGIC_VECTOR (4 DOWNTO 0);

begin
F1<=(A AND NOT B AND D)OR(NOT A AND C AND NOT D)OR(A AND B AND NOT C AND D)OR(NOT A AND NOT B AND C AND NOT D)OR(NOT A AND
B AND C AND D);

UNO<=A&B&C&D;
DOS<=A&B&C&D&E;

WITH UNO SELECT

F2<='1' WHEN "0001",
'1' WHEN "0100",
'1' WHEN "0101",
'1' WHEN "1000",
'1' WHEN "1011",
'1' WHEN "1101",
'0' WHEN OTHERS;
WITH DOS SELECT
F3<= '1' WHEN "00001",
 '1' WHEN "00010",
'1' WHEN "00100",
'1' WHEN "00111",
'1' WHEN "01000",
'1' WHEN "01011",
'1' WHEN "01100",
'1' WHEN "01110",
'1' WHEN "01111",
'1' WHEN "11011",
'1' WHEN "11110",
'1' WHEN "11111",
'0' WHEN OTHERS;
end Behavioral;

Diagrama de tiempos QII.

Diagrama de tiempos ISE.

WINCUPL

Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device g16v8 ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */
PIN 6 = E ; /* */

/* *************** OUTPUT PINS *********************/

PIN 13 = F1 ; /* */
PIN 14 = F2 ; /* */
PIN 15 = F3 ; /* */

F1 = (A&!B&D)#(!A&C&!D)#(A&B&!C&D)#(!A&!B&C&!D)#(!A&B&C&D);

TABLE A,B,C,D,E=> F3
{
'b'00001 => 'b'1;
'b'00010 => 'b'1;
'b'00100 => 'b' 1;
'b'00111 => 'b' 1;
'b'01000 => 'b' 1;
'b'01011 => 'b' 1;
'b'01100 => 'b' 1;
'b'01110 => 'b' 1;
'b'01111 => 'b' 1;
'b'11011 => 'b' 1;
'b'11110 => 'b' 1;
'b'11111 => 'b' 1;
}

TABLE A,B,C,D=> F2
{
'b'0000 => 'b'0;
'b'0001 => 'b'1;
'b'0010 => 'b'0;
'b'0011 => 'b' 0;
'b'0100 => 'b' 1;
'b'0101 => 'b' 1;
'b'0110 => 'b' 0;
'b'0111 => 'b' 0;
'b'1000 => 'b' 1;
'b'1001 => 'b' 0;
'b'1010 => 'b' 0;
'b'1011 => 'b' 1;
'b'1100 => 'b' 0;
'b'1101 => 'b' 1;
'b'1110 => 'b' 0;
'b'1111 => 'b' 0;
}

OREX/NOREX
QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( A : in STD_LOGIC_VECTOR (3 DOWNTO 0);
X : out STD_LOGIC;
Y : out std_logic );
end RLHG;

architecture Behavioral of RLHG is

begin
WITH A SELECT
X <= '1' when "0010",
'1' when "0100",
'1' when "0101",
'1' when "0110",
'1' when "1000",
'1' when "1100",
'1' when "1101",
'1' when "1111",
'0' when others;
With A SELECT
Y <= '1' when "0011",
'1' when "0101",
'1' when "0110",
'1' when "1001",
'1' when "1010",
'1' when "1100",
'0' when others;
end Behavioral;
Diagrama de tiempos QII.

Diagrama de tiempos ISE.

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device virtual ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */

/* *************** OUTPUT PINS *********************/

PIN 13 = F1 ; /* */
PIN 14 = F2 ; /* */

TABLE A, B, C, D => F1
{
'b'0010 => 'b'1;
'b'0100 => 'b'1;
'b'0101 => 'b'1;
'b'0110 => 'b'1;
'b'1000 => 'b'1;
'b'1100 => 'b'1;
'b'1101 => 'b'1;
'b'1111 => 'b'1;
}
TABLE A, B, C, D => F2
{
'b'0011 => 'b'1;
'b'0101 => 'b'1;
'b'0110 => 'b'1;
'b'1001 => 'b'1;
'b'1010 => 'b'1;
'b'1100 => 'b'1;
}
QUINE McCLUSKEY

Proteus.

QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( A,B,C,D,E : in STD_LOGIC;
F1,F2,F3 : out STD_LOGIC);
end RLHG;

architecture Behavioral of RLHG is

SIGNAL UNO: STD_LOGIC_VECTOR ( 3 DOWNTO 0);
SIGNAL DOS: STD_LOGIC_VECTOR ( 4 DOWNTO 0);
begin
UNO <= A&B&C&D;
DOS <= A&B&C&D&E;
WITH UNO SELECT
F1 <= '1' when "0000",
'1' when "0011",
'1' when "0100",
'1' when "0111",
 '1' when "1011",
'1' when "1100",
'0' when OTHERS ;
WITH DOS SELECT
F2<='1' WHEN "00001",
'1' WHEN "00000",
'1' WHEN "00010",
'1' WHEN "01111",
'1' WHEN "10000",
'1' WHEN "10011",
'1' WHEN "10111",
'0' WHEN OTHERS;
WITH UNO SELECT
F3 <= '1' when "0000",
'1' when "0001",
'1' when "0100",
'1' when "0101",
'1' when "0110",
'1' when "1000",
'1' when "1001",
'1' when "1111",
'0' when OTHERS ;
end Behavioral;
Diagrama de tiempos QII.

Diagrama de tiempos ISE.

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device virtual ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */
PIN 6= E ; /* */

/* *************** OUTPUT PINS *********************/

PIN 15 = F1 ; /* */
PIN 16 = F2 ; /* */
PIN 17 = F3 ; /* */

FIELD IN = [A,B,C,D];
TABLE IN => F1
{
'b'0000 => 'b'1;
'b'0011 => 'b'1;
'b'0100 => 'b'1;
'b'0111 => 'b'1;
'b'1011 => 'b'1;
'b'1100 => 'b'1;
}
TABLE IN => F3
{
'b'0000 => 'b'1;
'b'0001 => 'b'1;
'b'0100 => 'b'1;
'b'0101 => 'b'1;
'b'0110 => 'b'1;
'b'1000 => 'b'1;
'b'1001 => 'b'1;
'b'1111 => 'b'1;
}

TABLE A,B,C,D,E=>F2
{
'b'00000 => 'b'1;
'b'00001 => 'b'1;
'b'00010 => 'b'1;
'b'01111 => 'b'1;
'b'10000 => 'b'1;
'b'10011 => 'b'1;
'b'10111 => 'b'1;
}

b)

Proteus.
QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( A,B,C,D : in STD_LOGIC;
F1,F2,F3 : out STD_LOGIC);
end RLHGI;

architecture Behavioral of RLHG is

SIGNAL UNO : STD_LOGIC_VECTOR (3 DOWNTO 0);
begin
UNO <= A&B&C&D;
WITH UNO SELECT
F1 <= '1' when "0011",
'1' when "0101",
'1' when "0110",
'1' when "0111",
'1' when "1001",
'X' when "0000",
'X' when "0100",
'X' when "1010",
'X' when "1100",
'0' when OTHERS ;
WITH UNO SELECT
F2 <= '1' when "0000",
'1' when "0001",
'1' when "0011",
'1' when "0101",
'1' when "0110",
'1' when "1011",
'1' when "1110",
'X' when "1000",
'X' when "1100",
'X' when "1101",
'X' when "1111",
'0' when OTHERS ;
WITH UNO SELECT
F3 <= '1' when "0000",
'1' when "0001",
'1' when "0010",
'1' when "0011",
'1' when "0100",
'X' when "0101",
 'X' when "0110",
'X' when "0111",
'X' when "1000",
'X' when "1001",
'X' when "1010",
'0' when OTHERS ;
end Behavioral;

Diagrama de tiempos QII.

Diagrama de tiempos QII.

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device virtual ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */

/* *************** OUTPUT PINS *********************/

PIN 15 = F1 ; /* */
PIN 16 = F2 ; /* */
PIN 17 = F3 ; /* */

TABLE A,B,C,D=> F1
{
'b'0011 => 'b'1;
'b'0101 => 'b'1;
'b'0110 => 'b' 1;
'b'0111 => 'b' 1;
'b'1001 => 'b' 1;
'b'0000 => 'b' X;
'b'0100 => 'b' X;
'b'1000 => 'b' X;
'b'1010 => 'b' X;
'b'1100 => 'b' X;
}

TABLE A,B,C,D=> F2
{
'b'0000 => 'b'1;
'b'0001 => 'b'1;
'b'0011 => 'b' 1;
'b'0101 => 'b' 1;
'b'0110 => 'b' 1;
'b'1011 => 'b' 1;
'b'1110 => 'b' 1;
'b'0100 => 'b' X;
'b'1100 => 'b' X;
'b'1101 => 'b' X;
'b'1111 => 'b' X;
}
TABLE A,B,C,D=> F3
{
'b'0000 => 'b'1;
'b'0001 => 'b'1;
'b'0010 => 'b' 1;
'b'0011 => 'b' 1;
'b'0100 => 'b' 1;
'b'0101 => 'b' X;
'b'0110 => 'b' X;
'b'0111 => 'b' X;
'b'1000 => 'b' X;
'b'1001 => 'b' X;
'b'1010 => 'b' X;
}

VARIABLES BIFORMES

Proteus.
QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( V,W,X,Y,Z : in STD_LOGIC;
FA,FB : out STD_LOGIC);
end RLHG;

architecture Behavioral of RLHG is

SIGNAL UNO: STD_LOGIC_VECTOR ( 4 DOWNTO 0);
begin
UNO <= V&W&X&Y&Z;
WITH UNO SELECT
FA <= '1' WHEN "00000",
'1' WHEN "00001",
'1' WHEN "00100",
'1' WHEN "00111",
'1' WHEN "01001",
'1' WHEN "10000",
'1' WHEN "10100",
'1' WHEN "11000",
'1' WHEN "11101",
'1' WHEN "11111",
'0' WHEN OTHERS;

FB <= (V AND NOT W AND X AND NOT Y AND Z)OR(NOT V AND W AND NOT X AND Y AND NOT Z)OR
(NOT W AND X AND Y AND NOT Z)OR(W AND NOT X AND Y AND Z)OR(NOT W AND NOT X AND Y AND NOT Z)OR(V AND NOT W AND NOT X AND Y
AND Z);

end Behavioral;
Diagrama de tiempos QII.
 Diagrama de tiempos ISE.

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device virtual ;

/* *************** INPUT PINS *********************/

PIN 2 = V ; /* */
PIN 3 = W ; /* */
PIN 4 = X ; /* */
PIN 5 = Y ; /* */
PIN 6 = Z ; /* */

/* *************** OUTPUT PINS *********************/

PIN 13 = FA ; /* */
PIN 14 = FB ; /* */

TABLE V,W,X,Y,Z => FA

{
'b'00000 => 'b'1;
'b'00001 => 'b'1;
'b'00100 => 'b' 1;
'b'00111 => 'b' 1;
'b'01001 => 'b' 1;
'b'10000 => 'b' 1;
'b'10100 => 'b' 1;
'b'11000 => 'b' 1;
'b'11101 => 'b' 1;
'b'11111 => 'b' 1;
}
FB = (V&!W&X&!Y&Z)#(!V&W&!X&Y&!Z)#(!W&X&Y&!Z)#(W&!X&Y&Z)#(!W&!X&Y&!Z)#(V&!W&!X&Y&Z);
APLICACIÓN MAPAS DE KARNAUGH

Proteus.

QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( X : in STD_LOGIC_VECTOR (3 downto 0);
L1,L2,L3 : out STD_LOGIC);
end RLHG;

architecture Behavioral of RLHG is

SIGNAL L: STD_LOGIC_VECTOR (1 TO 3);
begin
WITH X SELECT
L <= "000" WHEN "0000",
"110" WHEN "0001",
"110" WHEN "0010",
"100" WHEN "0011",
"110" WHEN "0100",
"000" WHEN "0101",
"100" WHEN "0110",
"110" WHEN "0111",
"110" WHEN "1000",
"100" WHEN "1001",
"000" WHEN "1010",
"110" WHEN "1011",
"100" WHEN "1100",
"110" WHEN "1101",
"110" WHEN "1110",
"100" WHEN "1111",
"000" WHEN OTHERS;
L1 <= L(1);
L2 <= L(2);
L3 <= L(3);
end Behavioral;
Diagrama de tiempos QII.
 Diagrama de tiempos ISE

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 19.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device g22v10 ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */
PIN 5 = D ; /* */

/* *************** OUTPUT PINS

*********************/
PIN 14 = L1 ; /* */
PIN 15 = L2 ; /* */
PIN 16 = L3 ; /* */

TABLE A,B,C,D => L1, L2, L3

{
'b'0000 => 'b'000;
'b'0001 => 'b'110;
'b'0010 => 'b'110;
'b'0011 => 'b' 100;
'b'0100 => 'b' 110;
'b'0101 => 'b' 000;
'b'0110 => 'b' 100;
'b'0111 => 'b' 110;
'b'1000 => 'b' 110;
'b'1001 => 'b' 100;
'b'1010 => 'b' 000;
'b'1011 => 'b' 110;
'b'1100 => 'b' 100;
'b'1101 => 'b' 110;
'b'1110 => 'b' 110;
'b'1111 => 'b' 100;
}

APLICACIÓN QUINE McCLUSKEY *

Proteus.
QII.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RLHG is
Port ( E : in STD_LOGIC_VECTOR (4 downto 1);
W,X,Y : out STD_LOGIC);
end RLHG;

architecture Behavioral of RLHG is

SIGNAL F: STD_LOGIC_VECTOR (1 TO 3);
begin
WITH E SELECT
F <= "111" WHEN "0000",
"001" WHEN "0001",
"010" WHEN "0010",
"010" WHEN "0011",
"011" WHEN "0100",
"011" WHEN "0101",
"011" WHEN "0110",
"011" WHEN "0111",
"100" WHEN "1000",
"100" WHEN "1001",
"100" WHEN "1010",
"100" WHEN "1011",
"100" WHEN "1100",
"100" WHEN "1101",
"100" WHEN "1110",
"100" WHEN "1111",
"000" WHEN OTHERS;
W <= F(1);
X <= F(2);
Y <= F(3);
end Behavioral;
Diagrama de tiempos QII.
 Diagrama de tiempos ISE.

WINCUPL
Name RLHG ;
PartNo 00 ;
Date 20.09.2019 ;
Revision 01 ;
Designer Engineer ;
Company Umsa ;
Assembly None ;
Location ;
Device virtual ;

/* *************** INPUT PINS *********************/

PIN 2 = A ; /* */
PIN 3 = B ; /* */
PIN 4 = C ; /* */

/* *************** OUTPUT PINS *********************/

PIN [16..18] = [S0..S2] ; /* */

TABLE A, B, C => S0, S1, S2

{
'b'000 => 'b'010;
'b'001 => 'b'110;
'b'010 => 'b' 010;
'b'011 => 'b' 010;
'b'100 => 'b' 000;
'b'101 => 'b' 000;
'b'110 => 'b' 011;
'b'111 => 'b' 111;
}