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●● Phones
●● MP3 Players
SCL
MAX9723B 1001101 0
MAX9723C 1001100 +6 INL
OUTR
VOLUME
MAX9723D 1001101 +6 INR CONTROL
∑
DirectDrive is a registered trademark of Maxim Integrated BBR
Products, Inc. MAX9723 BassMax
SMBus is a trademark of Intel Corp.
UCSP is a trademark of Maxim Integrated Products, Inc.
Electrical Characteristics
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1μF, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load connected
between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
Timing Characteristics
(VDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = 1μF, BB_ = 0V. gain = 0dB, maximum volume, BassMax disabled. Load con-
nected between OUT_ and SGND where specified. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C, see
Timing Diagram.) (Notes 1, 3)
TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY NOISE vs. FREQUENCY NOISE vs. FREQUENCY
1 1 1
MAX9723 toc01
MAX9723 toc02
MAX9723 toc03
VDD = 2.4V VDD = 2.4V VDD = 3V
RL = 16Ω RL = 32Ω RL = 16Ω
THD+N (%)
THD+N (%)
POUT = 10mW POUT = 20mW
POUT = 10mW
0.01 0.01 0.01
MAX9723 toc05
MAX9723 toc06
VDD = 3V VDD = 2.4V VDD = 2.4V
RL = 32Ω RL = 16Ω RL = 32Ω
10 10
0.1
1 1
THD+N (%)
THD+N (%)
THD+N (%)
POUT = 10mW
fIN = 1kHz
fIN = 20Hz fIN = 1kHz
0.1 fIN = 10kHz 0.1 fIN = 10kHz
fIN = 20Hz
0.01
0.01 0.01
POUT = 30mW
0.001 0.001 0.001
10 100 1k 10k 100k 0 20 40 60 0 20 40 60
FREQUENCY (Hz) OUTPUT POWER (mW) OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS TOTAL HARMONIC DISTORTION PLUS POWER DISSIPATION
NOISE vs. OUTPUT POWER NOISE vs. OUTPUT POWER vs. OUTPUT POWER
100 100 180
MAX9723 toc07
MAX9723 toc08
MAX9723 toc09
1
THD+N (%)
100 RL = 32Ω
fIN = 1kHz
fIN = 10kHz fIN = 1kHz 80
0.1 0.1
fIN = 20Hz fIN = 10kHz 60
fIN = 20Hz
0.01 0.01 40
20
0.001 0.001 0
0 20 40 60 80 100 0 20 40 60 80 100 0 20 40 60 80
OUTPUT POWER (mW) OUTPUT POWER (mW) OUTPUT POWER (mW)
MAX9723 toc10
MAX9723 toc11
VDD = 3V VDD = 2.4V
fIN = 1kHz 70 fIN = 1kHz
250 POUT = POUTL + POUTR
RL = 16Ω
POWER DISSIPATION (mW)
OUTPUTS IN PHASE 60
30
100 THD+N = 1%
20
50
10
0 0
0 20 40 60 80 100 120 10 100 1k
OUTPUT POWER (mW) LOAD RESISTANCE (W)
MAX9723 toc13
MAX9723 toc12
VDD = 3V
90 fIN = 1kHz 90
80 80
THD+N = 10%
OUTPUT POWER (mW)
OUTPUT POWER (mW)
70 70
THD+N = 10%
60 60
50 50
THD+N = 1% 40 THD+N = 1%
40
30 30
20 20
fIN = 1kHz
10 10 RL = 16Ω
0 0
10 100 1k 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
LOAD RESISTANCE (Ω) SUPPLY VOLTAGE (V)
MAX9723 toc15
RL = 32Ω
-10
120
-20
OUTPUT POWER (mW)
100 -30
THD+N = 10% -40
PSRR (dB)
80
-50
60
-60
40 THD+N = 1% -70
-80
20 fIN = 1kHz
RL = 32Ω -90
0 -100
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 10 100 1k 10k 100k
SUPPLY VOLTAGE (V) FREQUENCY (Hz)
CROSSTALK CROSSTALK
vs. FREQUENCY vs. FREQUENCY
0 0
MAX9723 toc16
MAX9723 toc17
VIN = 1VP-P VIN = 1VP-P
-20 RL = 32Ω -20 RL = 32Ω
A = 0dB A = -10dB
-40 -40
CROSSTALK (dB)
CROSSTALK (dB)
RIGHT TO LEFT
A = 0dB RIGHT TO LEFT
-60 -60 A = -10dB
-80 -80
MAX9723 toc19
R2 = 36kΩ NO LOAD
C3 = 0.068µF R1 = 47kΩ 0
15
R2 = 22kΩ -1
10 C3 = 0.1µF
AMPLITUDE (dB)
AMPLITUDE (dB)
-2
R2 = 10kΩ
5 C3 = 0.22µF -3
-4
0
-5
BassMax DISABLED
-5
-6
-10 -7
10 100 1k 10k 100k 10 100 1k 10k 100k
FREQUENCY (Hz) FREQUENCY (Hz)
MAX9723 toc21
-70 -1.0
AMPLITUDE (dBV)
-80
-1.5
-90
-2.0
-100
-110 -2.5
-120
-3.0
-130
-140 -3.5
0 5 10 15 20 0 25 50 75 100 125 150 175 200
FREQUENCY (kHz) OUTPUT CURRENT (mA)
MAX9723 toc22
70 C1 = C2 = 2.2µF
65 C1 = C2 = 1µF VDD
OUTPUT POWER (mW)
2V/div
60
55
C1 = C2 = 0.68µF
50
VOUT
45
VDD = 3V 10mV/div
40 fIN = 1kHz
THD+N = 1%
35
10 20 30 40 50 20ms/div
LOAD RESISTANCE (Ω)
VSHDN
2V/div VSHDN
2V/div
VOUT_ VOUT_
200mV/div 200mV/div
40µs/div 20µs/div
MAX9723 toc27
7
4.0
SHUTDOWN CURRENT (µA)
6
SUPPLY CURRENT (mA)
3.5 5
4
3.0 3
2
2.5
NO LOAD 1 NO LOAD
INPUTS GROUNDED INPUTS GROUNDED
2.0 0
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
Pin Description
PIN BUMP
NAME FUNCTION
THIN QFN UCSP
1 D1 VDD Power-Supply Input. Bypass VDD to PGND with a 1µF capacitor.
2 C1 C1P Charge-Pump Flying Capacitor Positive Terminal
3 B1 PGND Power Ground. Connect to SGND.
4 A1 C1N Charge-Pump Flying Capacitor Negative Terminal
5 B2 SCL Serial Clock Input. Connect a 10kI pullup resistor from SCL to VDD.
6 A2 PVSS Charge-Pump Output. Connect to SVSS. Bypass PVSS with a 1µF capacitor to PGND.
7 A3 SDA Serial-Data Input. Connect a 10kΩ pullup resistor from SDA to VDD.
Shutdown. Drive SHDN low to disable the MAX9723. Connect SHDN to VDD while bit 7
8 B3 SHDN
is high for normal operation (see the Command Register section).
9 A4 SGND Signal Ground. Connect to PGND.
10 B4 INL Left-Channel Input
11 C4 INR Right-Channel Input
12 D4 SVSS Headphone Amplifier Negative Power-Supply Input. Connect to PVSS.
Right BassMax Input. Connect an external lowpass filter between OUTR and BBR to
13 C3 BBR apply bass boost to the right-channel output. Connect BBR to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
14 D3 OUTR Right Headphone Output
15 D2 OUTL Left Headphone Output
Left BassMax Input. Connect an external lowpass filter between OUTL and BBL to
16 C2 BBL apply bass boost to the left-channel output. Connect BBL to SGND if BassMax is not
used (see the BassMax (Bass Boost) section).
EP — EP Exposed Paddle. Connect EP to SVSS or leave unconnected.
Click-and-Pop Suppression
The output-coupling capacitor is a major contributor of
audible clicks and pops in conventional single-supply
MAX9723
headphone amplifiers. The amplifier charges the coupling R
capacitor to its output bias voltage at startup. During shut-
down the capacitor is discharged. This charging and dis- R
charging results in a DC shift across the capacitor, which AUDIO
INPUT OUT_
appears as an audible transient at the speaker. Since the
MAX9723 headphone amplifier does not require output-
coupling capacitors, no audible transients occur. R1
BB_
Additionally, the MAX9723 features extensive click-and-
pop suppression that eliminates any audible transient BassMax
ENABLE
sources internal to the device. The Power-Up/Power- R2 C3
Down Waveform in the Typical Operating Characteristics
shows that there are minimal transients at the output upon
startup or shutdown.
In most applications, the preamplifier driving the MAX9723
has a DC bias of typically half the supply. The input-coupling Figure 2. BassMax External Connections
capacitor is charged to the preamplifier’s bias voltage
through the MAX9723’s input impedance (RIN) during start- using positive feedback from OUT_ to BB_. Figure 2
up. The resulting voltage shift across the capacitor creates shows the connections needed to implement BassMax.
an audible click/pop. To avoid clicks/pops caused by the
input filter, delay the rise of SHDN by at least 4 time con- Maximum Gain Control
stants, 4 x RIN x CIN, relative to the start of the preamplifier. The MAX9723A and MAX9723B have selectable maxi-
mum gains of -5dB or 0dB (see Table 5) while the
BassMax (Bass Boost) MAX9723C and MAX9723D have selectable maximum
Typical headphones do not have a flat-frequency response. gains of +1dB or +6dB (see Table 6). Bit 5 in the command
The small physical size of the diaphragm does not allow the register selects between the two maximum gain settings.
headphone speaker to efficiently reproduce low frequen-
cies. This physical limitation results in attenuated bass Volume Control
response. The MAX9723 includes a bass boost feature The MAX9723 includes a 32-level volume control that
that compensates for the headphone’s poor bass response adjusts the gain of the output amplifiers according to
by increasing the amplifier gain at low frequencies. the code contained in the command register. Volume is
The DirectDrive output of the MAX9723 has more head- programmed through the command register bits [4:0].
room than typical single-supply headphone amplifiers. Tables 7–10 show all of the available gain settings for the
This additional headroom allows boosting the bass fre- MAX9723A–MAX9723D. The mute attenuation is typically
quencies without the output-signal clipping. better than 100dB when driving a 32Ω load.
Program the BassMax gain and cutoff frequency with Serial Interface
external components connected between OUT_ and BB_ The MAX9723 features an I2C/SMBus-compatible, 2-wire
(see the Functional Diagram/Typical Operating Circuit). serial interface consisting of a serial data line (SDA) and
Use the I2C-compatible interface to program the com- a serial clock line (SCL). SDA and SCL facilitate commu-
mand register to enable/disable the BassMax circuit. nication between the MAX9723 and the master at clock
BB_ is connected to the noninverting input of the output rates up to 400kHz. Figure 3 shows the 2-wire interface
amplifier when BassMax is enabled. BB_ is pulled to timing diagram. The MAX9723 is a receive-only slave
SGND when BassMax is disabled. The typical application device relying on the master to generate the SCL signal.
of the BassMax circuit involves feeding a lowpass version The MAX9723 cannot write to the SDA bus except to
of the output signal back to the amplifier. This is realized acknowledge the receipt of data from the master. The
SDA
tBUF
tSU, DAT tSU, STA
tHD, STA tSP
tSU, STO
tLOW tHD, DAT
SCL
tHIGH
tHD, STA
tR tF
master, typically a microcontroller, generates SCL and on SDA with SCL high. A STOP condition is a low-to-high
initiates data transfer on the bus. transition on SDA while SCL is high (Figure 4). A START
A master device communicates to the MAX9723 by trans- condition from the master signals the beginning of trans-
mitting the proper address followed by the data word. mission to the MAX9723. The master terminates trans-
Each transmit sequence is framed by a START (S) or mission and frees the bus by issuing a STOP condition.
REPEATED START (Sr) condition and a STOP (P) condi- The bus remains active if a REPEATED START condition
tion. Each word transmitted over the bus is 8 bits long and is generated instead of a STOP condition.
is always followed by an acknowledge clock pulse. Early STOP Conditions
The MAX9723 SDA line operates as both an input and an The MAX9723 recognizes a STOP condition at any point
open-drain output. A pullup resistor, greater than 500Ω, is during data transmission except if the STOP condition
required on the SDA bus. The MAX9723 SCL line oper- occurs in the same high pulse as a START condition.
ates as an input only. A pullup resistor, greater than 500Ω,
is required on SCL if there are multiple masters on the bus, Slave Address
or if the master in a single-master system has an open- The MAX9723 is available with one of two preset slave
drain SCL output. Series resistors in line with SDA and addresses (see Table 1). The address is defined as the
SCL are optional. Series resistors protect the digital inputs seven most significant bits (MSBs) followed by the Read/
of the MAX9723 from high-voltage spikes on the bus lines, Write (R/W) bit. The address is the first byte of informa-
and minimize crosstalk and undershoot of the bus signals. tion sent to the MAX9723 after the START condition. The
MAX9723 is a slave device only capable of being written
Bit Transfer to. The sent R/W bit must always be a zero when config-
One data bit is transferred during each SCL cycle. The uring the MAX9723.
data on SDA must remain stable during the high period The MAX9723 acknowledges the receipt of its address
of the SCL pulse. Changes in SDA while SCL is high are even if R/W is set to 1. However, the MAX9723 will not
control signals (see the START and STOP Conditions sec- drive SDA. Addressing the MAX9723 with R/W set to 1
tion). SDA and SCL idle high when the I2C bus is not busy. causes the master to receive all 1’s regardless of the
Start and Stop Conditions contents of the command register.
SDA and SCL idle high when the bus is not in use. A mas- Acknowledge
ter device initiates communication by issuing a START The acknowledge bit (ACK) is a clocked 9th bit that the
condition. A START condition is a high-to-low transition MAX9723 uses to handshake receipt of each byte of
NOT ACKNOWLEDGE
SDA
SDA
ACKNOWLEDGE
data (see Figure 5). The MAX9723 pulls down SDA dur- ter reads all 1’s from the MAX9723. Always reset the R/W
ing the master-generated 9th clock pulse. The SDA line bit to 0 to avoid this situation.
must remain stable and low during the high period of the
Command Register
acknowledge clock pulse. Monitoring ACK allows for detec-
tion of unsuccessful data transfers. An unsuccessful data The MAX9723 has one command register that is used to
transfer occurs if a receiving device is busy or if a system enable/disable shutdown, enable/disable BassMax, and
fault has occurred. In the event of an unsuccessful data set the maximum gain and volume. Table 2 describes the
transfer, the bus master may reattempt communication. function of the bits contained in the command register.
Reset B7 to 0 to shut down the MAX9723. The MAX9723
Write Data Format
wakes up from shutdown when B7 is set to 1 provided
A write to the MAX9723 includes transmission of a START SHDN is high. SHDN must be high and B7 must be set
condition, the slave address with the R/W bit reset to 0 to 1 for the MAX9723 to operate normally (see Table 3).
(see Table 1), one byte of data to configure the command
register, and a STOP condition. Figure 6 illustrates the Set B6 to 1 to enable BassMax (see Table 4). The output
proper format for one frame. signal’s low-frequency response will be boosted accord-
ing to the external components connected between OUT_
The MAX9723 only accepts write data, but it acknowl- and BB_. See the BassMax Gain-Setting Components
edges the receipt of its address byte with the R/W bit set section in the Applications Information section for details
high. The MAX9723 does not write to the SDA bus in the on choosing the external components.
event that the R/W bit is set high. Subsequently, the mas-
R/W ACKNOWLEDGE
FROM MAX9723
Table 6. MAX9723C and MAX9723D
Maximum Gain Control
MAXIMUM GAIN (dB) B5
+1 0
Figure 6. Write Data Format Example
+6 1
The MAX9723A and MAX9723B have a maximum temperature, or add heatsinking. Large output, supply,
gain setting of -5dB or 0dB, while the MAX9723C and and ground traces decrease θJA, allowing more heat to be
MAX9723D have a maximum gain setting of +1dB or transferred from the package to surrounding air.
+6dB. B5 in the command register programs the maxi-
mum gain (see Tables 5 and 6). Output Dynamic Range
Dynamic range is the difference between the noise
Adjust the MAX9723’s amplifier gain with the volume
floor of the system and the output level at 1% THD+N.
control bits [4:0]. The gain is adjustable to one of 32 steps
It is essential that a system’s dynamic range be known
ranging from full mute to the maximum gain programmed
before setting the maximum output gain. Output clipping
by B5. Tables 7–10 list all the possible gain settings for
will occur if the output signal is greater than the dynamic
the MAX9723. Figures 7–10 show the volume control
range of the system. The DirectDrive architecture of the
transfer functions for the MAX9723.
MAX9723 has increased dynamic range compared to
Power-On Reset other single-supply amplifiers.
The contents of the MAX9723’s command register at Use the THD+N vs. Output Power in the Typical Operating
power-on are shown in Table 11. Characteristics to identify the system’s dynamic range.
Find the output power that causes 1% THD+N for a given
Applications Information load. This point will indicate what output power causes the
Power Dissipation and Heat Sinking output to begin to clip. Use the following equation to deter-
mine the peak output voltage that causes 1% THD+N for
Linear power amplifiers can dissipate a significant amount
a given load.
of power under normal operating conditions. The maxi-
mum power dissipation for each package is given in the
Absolute Maximum Ratings section under Continuous V O U T _ (P −P ) 2 2(P O U T _1 % ×R L )
=
Power Dissipation or can be calculated by the following
equation: where POUT_1% is the output power that causes 1%
T J(M A X ) − T A THD+N, RL is the load resistance, and VOUT_(P-P) is
P D (M A X ) = the peak output voltage. After VOUT_(P-P) is identified,
θ JA determine the peak input voltage that can be amplified
without clipping:
where TJ(MAX) is +150°C, TA is the ambient temperature,
and θJA is the reciprocal of the derating factor in °C/W as V O U T _ (P −P )
specified in the Absolute Maximum Ratings section. For V IN _ (P −P ) =
A V
example, θJA for the thin QFN package is +59°C/W. 20
The MAX9723 has two power dissipation sources, the 10
charge pump and the two output amplifiers. If the power where VIN_(P-P) is the largest peak voltage that can be
dissipation exceeds the rated package dissipation, reduce amplified without clipping, and AV is the voltage gain
VDD, increase load impedance, decrease the ambient
Table 7. MAX9723A and MAX9723B Gain Table 8. MAX9723A and MAX9723B Gain
Settings (B5 = 1, Max Gain = 0dB) Settings (B5 = 0, Max Gain = -5dB)
B0 GAIN B0 GAIN
B4 B3 B2 B1 B4 B3 B2 B1
(LSB) (dB) (LSB) (dB)
1 1 1 1 1 0 1 1 1 1 1 -5
1 1 1 1 0 -0.5 1 1 1 1 0 -6
1 1 1 0 1 -1 1 1 1 0 1 -7
1 1 1 0 0 -1.5 1 1 1 0 0 -9
1 1 0 1 1 -2 1 1 0 1 1 -11
1 1 0 1 0 -2.5 1 1 0 1 0 -13
1 1 0 0 1 -3 1 1 0 0 1 -15
1 1 0 0 0 -4 1 1 0 0 0 -17
1 0 1 1 1 -5 1 0 1 1 1 -19
1 0 1 1 0 -6 1 0 1 1 0 -21
1 0 1 0 1 -7 1 0 1 0 1 -23
1 0 1 0 0 -9 1 0 1 0 0 -25
1 0 0 1 1 -11 1 0 0 1 1 -27
1 0 0 1 0 -13 1 0 0 1 0 -29
1 0 0 0 1 -15 1 0 0 0 1 -31
1 0 0 0 0 -17 1 0 0 0 0 -33
0 1 1 1 1 -19 0 1 1 1 1 -35
0 1 1 1 0 -21 0 1 1 1 0 -37
0 1 1 0 1 -23 0 1 1 0 1 -39
0 1 1 0 0 -25 0 1 1 0 0 -41
0 1 0 1 1 -27 0 1 0 1 1 -43
0 1 0 1 0 -29 0 1 0 1 0 -45
0 1 0 0 1 -31 0 1 0 0 1 -47
0 1 0 0 0 -33 0 1 0 0 0 -50
0 0 1 1 1 -35 0 0 1 1 1 -53
0 0 1 1 0 -37 0 0 1 1 0 -56
0 0 1 0 1 -39 0 0 1 0 1 -59
0 0 1 0 0 -41 0 0 1 0 0 -62
0 0 0 1 1 -43 0 0 0 1 1 -65
0 0 0 1 0 -45 0 0 0 1 0 -68
0 0 0 0 1 -47 0 0 0 0 1 -71
0 0 0 0 0 MUTE 0 0 0 0 0 MUTE
Table 9. MAX9723C and MAX9723D Gain Table 10. MAX9723C and MAX9723D Gain
Settings (B5 = 1, Max Gain = +6dB) Settings (B5 = 0, Max Gain = +1dB)
B0 GAIN B0 GAIN
B4 B3 B2 B1 B4 B3 B2 B1
(LSB) (dB) (LSB) (dB)
1 1 1 1 1 6 1 1 1 1 1 1
1 1 1 1 0 5.5 1 1 1 1 0 0
1 1 1 0 1 5 1 1 1 0 1 -1
1 1 1 0 0 4.5 1 1 1 0 0 -3
1 1 0 1 1 4 1 1 0 1 1 -5
1 1 0 1 0 3.5 1 1 0 1 0 -7
1 1 0 0 1 3 1 1 0 0 1 -9
1 1 0 0 0 2 1 1 0 0 0 -11
1 0 1 1 1 1 1 0 1 1 1 -13
1 0 1 1 0 0 1 0 1 1 0 -15
1 0 1 0 1 -1 1 0 1 0 1 -17
1 0 1 0 0 -3 1 0 1 0 0 -19
1 0 0 1 1 -5 1 0 0 1 1 -21
1 0 0 1 0 -7 1 0 0 1 0 -23
1 0 0 0 1 -9 1 0 0 0 1 -25
1 0 0 0 0 -11 1 0 0 0 0 -27
0 1 1 1 1 -13 0 1 1 1 1 -29
0 1 1 1 0 -15 0 1 1 1 0 -31
0 1 1 0 1 -17 0 1 1 0 1 -33
0 1 1 0 0 -19 0 1 1 0 0 -35
0 1 0 1 1 -21 0 1 0 1 1 -37
0 1 0 1 0 -23 0 1 0 1 0 -39
0 1 0 0 1 -25 0 1 0 0 1 -41
0 1 0 0 0 -27 0 1 0 0 0 -44
0 0 1 1 1 -29 0 0 1 1 1 -47
0 0 1 1 0 -31 0 0 1 1 0 -50
0 0 1 0 1 -33 0 0 1 0 1 -53
0 0 1 0 0 -35 0 0 1 0 0 -56
0 0 0 1 1 -37 0 0 0 1 1 -59
0 0 0 1 0 -39 0 0 0 1 0 -62
0 0 0 0 1 -41 0 0 0 0 1 -65
0 0 0 0 0 MUTE 0 0 0 0 0 MUTE
signal to an optimum DC level. The -3dB point of the high- Table 11. Initial Power-Up Command
pass filter, assuming zero-source impedance, is given by: Register Status
1 MODE B7 B6 B5 B4 B3 B2 B1 B0
f −3 d B =
2 π × R IN × C IN Power-On
1 1 1 1 1 1 1 1
Reset
MAX9723A AND MAX9723B TRANSFER FUNCTION MAX9723C AND MAX9723D TRANSFER FUNCTION
(B5 = 1) (B5 = 1)
toc 01 toc 02
10 10
0 0
-10 -10
GAIN (dB)
GAIN (dB)
-20 -20
-30 -30
-40 -40
-50 -50
0 6 12 18 24 30 0 6 12 18 24 30
CODE CODE
Figure 7. MAX9723A/MAX9723B Transfer Function with B5 = 1 Figure 9. MAX9723C/MAX9723D Transfer Function with B5 = 1
MAX9723A AND MAX9723B TRANSFER FUNCTION MAX9723C AND MAX9723D TRANSFER FUNCTION
(B5 = 0) (B5 = 0)
toc 03 toc 04
0 10
-10 0
-20 -10
-30 -20
GAIN (dB)
GAIN (dB)
-40 -30
-50 -40
-60 -50
-70 -60
-80 -70
0 6 12 18 24 30 0 6 12 18 24 30
CODE CODE
Figure 8. MAX9723A/MAX9723B Transfer Function with B5 = 0 Figure 10. MAX9723C/MAX9723D Transfer Function with B5 = 0
where RIN is a minimum of 10kΩ. Choose CIN such Charge-Pump Flying Capacitor
that f-3dB is well below the lowest frequency of interest. The charge-pump flying capacitor connected between
Setting f-3dB too high affects the amplifier’s low-frequency C1N and C1P affects the charge pump’s load regulation
response. Use capacitors with low-voltage coefficient and output impedance. Choosing a flying capacitor that
dielectrics. Film or C0G dielectric capacitors are good is too small degrades the MAX9723’s ability to provide
choices for AC-coupling capacitors. Capacitors with high- sufficient current drive and leads to a loss of output volt-
voltage coefficients, such as ceramics, can result in age. Increasing the value of the flying capacitor improves
increased distortion at low frequencies. load regulation and reduces the charge-pump output
impedance. See the Output Power vs. Charge-Pump
Capacitance and Load Resistance graph in the Typical
Operating Characteristics.
AV (dB)
OUT_ CA 5
4 MAX9723A
RA CMD REGISTER
3 CODE = 0xFF
BassMax 2 RA = 47kΩ
ENABLE RB = 22kΩ
BB_ 1 CA = 0.33mF
RB 0
0.1 1 10 100 1k 10k
FREQUENCY (Hz)
Figure 12. Using BassMax to Increase MAX9723’s Maximum Figure 13. Increasing the Maximum Gain Using BassMax
Gain
C5 R5 R6 CIN
1µF 10kΩ 10kΩ 0.47µF
SVSS R3
SVSS 47kΩ
BBR
C4
R4 0.1µF
MAX9723 22kΩ
VDD VDD
VDD BBL R2 C3
22kΩ 0.1µF
C1P
C1
C1N CHARGE PUMP
1µF
SVSS R1
R 47kΩ
SVSS
OUTL
C2 CIN
1µF 0.47µF BASS BOOST CIRCUIT TUNED
FOR +8.8dB AT 106Hz.
ANALOG INPUT
System Diagram
1.8V TO
R5 R6 C5
3.6V
10kΩ 10kΩ 1µF
VDD
SDA
I2C
MASTER SCL OUTL
CIN
R3
0.47µF
47kΩ
INL BBL
CIN MAX9723
CODEC R4
0.47µF C4
INR 22kΩ 0.1µF
OUTR
C1P
C1 R1
1µF C1N 47kΩ
BBR
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
OUTR
OUTL
TOP VIEW
BBR
BBL
1 2 3 4
+ 16 15 14 13
C1P 2 11 INR
MAX9723_
PGND 3 10 INL
B PGND SCL SHDN INL
C1N 4 9 SGND
MAX9723_
5 6 7 8
C C1P BBL BBR INR
PVSS
SHDN
SDA
SCL
THIN QFN
UCSP
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
Updated TQFN pin configuration, and corrected Typical Operating Circuit and System
2 8/08 20, 21
Diagram pin names
3 7/14 Removed automotive reference in Applications section 1
4 7/14 Updated Table 8, Table 10, and replaced Figures 7 through 10 15, 16, 17
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are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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