Cap4. Digital Systems - Combinational Logic Circuits

25-10-2010
Introduction
Basic logic gate functions will be combined in
combinational logic circuits.
Chapter 4 Simplification of logic circuits will be done using
Boolean algebra and a mapping technique.
technique
Combinational Logic Circuits Troubleshooting of combinational circuits will be introduced.

PLD and HDL control structures will be explained.
Adapted from : João Carlos Martins Ronald Tocci/Neal Widmer/Gregory

Ronald Tocci/Neal Widmer/Gregory Moss Escola Superiror de Tecnologia e Gestão Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Applications, 10e Instituto Politécnico de Beja Digital Systems: Principles and Columbus, OH 43235
Pearson Education , 2007 2009 Applications, 10e All rights reserved..
4-1 Sum-of-Products Form 4-2 Simplifying Logic Circuits

A Sum-of-products (SOP) expression will The circuits below both provide the same output, but
the lower one is clearly less complex.
appear as two or more AND terms ORed
together.
ABC + ABC
AB + ABC + C D + D
We will study simplifying logic circuits using
Boolean algebra and Karnaugh mapping
Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory
Moss Copyright ©2007 by Pearson Education, Inc. Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235 Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved.. Applications, 10e All rights reserved..
4-3 Algebraic Simplification Ex. Simplify the logic circuit

Place the expression in SOP form by applying
DeMorgan’s theorems and multiplying terms.
Check the SOP form for common factors and
perform factoring where possible.
Note that this process may involve some trial
and error to obtain the simplest result.
Ronald Tocci/Neal Widmer/Gregory

Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved..
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Ex. Simplify the logic circuit 4-4 Designing Combinational Logic Circuits
To solve any logic design problem:
Interpret the problem and set up its truth table.
Write the AND (product) term for each case where the
output
p equals
q 1.
Combine the terms in SOP form.
Simplify the output expression if possible.
Implement the circuit for the final, simplified
expression.
Ronald Tocci/Neal Widmer/Gregory Moss Copyright ©2004 by Pearson Education, Inc.

Digital Systems: Principles and Applications, 9e Upper Saddle River, New Jersey 07458
All rights reserved.
4-4 Designing Combinational Logic Circuits 4-4 Designing Combinational Logic Circuits
Example (4-8) Example (4-8)
A digital circuit is monitoring a 12 V battery using the output of an 1. Truth table 2. Product (AND) 3. Combine the
analog digital-converter. The ADC output is a binary number with terms terms in SOP form
4 bits: ABCD, corresponding to the battery potential in steps of 1V, z = ABCD + A BCD
where A is the MSB. The ADC output is fed to a digital circuit that
must give an active high (1) output whenever the electric potential + A BCD + A BCD
is bigger than 6V (610=01102). Project the digital circuit. + A BCD + ABCD
+ ABCD + ABCD
+ ABCD
4. Simplify the output
expression
z = BCD + A
Moss
Digital Systems: Principles and
Copyright ©2004 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
5. Implement the digital
Applications, 9e All rights reserved.
circuit
4-4 Using NAND Gates 4-5 Karnaugh Map Method

The NAND gates are the most available in the TTL Graphical method of simplifying logic
technology.
equations or truth tables. Also called a K map.
Convert a SOP circuit to NAND gates:
Replace every AND, OR and INVERTER by a NAND gate Theoretically can be used for any number of
(remember the alternative representation of a gate!)
Use a NAND gate to invert any variable that inputs the final OR gate
input variables, but practically useful to 5 or 6
variables maximum.
Ronald Tocci/Neal Widmer/Gregory Moss Copyright ©2007 by Pearson Education, Inc.

Digital Systems: Principles and Applications, 10e Columbus, OH 43235
All rights reserved..
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25-10-2010
4-5 Karnaugh
4-5 Karnaugh Map Method Map Method
The truth table values are placed in the K
map.
Adjacent
j K mapp square
q differ in onlyy one
variable both horizontally and vertically.
The pattern from top to bottom and left to
right must be in the form AB, AB, AB, AB
A SOP expression can be obtained by
ORing all squares that contain a 1.
Moss Copyright ©2007 by Pearson Education, Inc. Moss
Digital Systems: Principles and Columbus, OH 43235 Digital Systems: Principles and
Applications, 10e All rights reserved.. Applications, 10e
4-5 Karnaugh Map Method 4-5 Karnaugh Map Method

Looping adjacent groups of 2, 4, or 8 1s will Complete K map simplification process:
result in further simplification. Construct the K map, place 1s as indicated in the truth
table.
When the largest possible groups have been Loop 1s that are not adjacent to any other 1s.
l
looped,
d onlyl the
th common terms
t are placed
l d ini L
Loop 1s
1 that
h are in
i pairs
i
the final expression. Loop 1s in octets even if they have already been looped.
Loop quads that have one or more 1s not already looped.
Looping may also be wrapped between top, Loop any pairs necessary to include 1st not already looped.
bottom, and sides. Form the OR sum of terms generated by each loop.

4-5 Looping Illustration 4-5 Looping Illustration

Grouping Grouping
2 terms 4 terms
(duets) (quartets)
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4-5 Looping Illustration 4-5 Example

Grouping Grouping
8 terms terms with
(octets) different
number of
1s
4-5 Example 4-5 Indifferent terms

Sometimes there is more than one good There are situations where for certain input conditions
solution: the output does not matter: it can be 0 or 1
Called “don’t care” terms
Th
These terms
t can appear due
d to t different
diff t reasons:
These input conditions will never occur (we don’t have to
care about the output)
The output is not specified for these conditions.
We can consider these outputs to be 0 or 1, whatever
is more convenient.
Applications, 10e All rights reserved...
4-5 Example 4-6 Exclusive OR and Exclusive NOR Circuits

For the don’t care terms we can assume the The exclusive OR (XOR) produces a HIGH output
value for the output more convenient for the whenever the two inputs are at opposite levels.
project.
The exclusive NOR (XNOR) produces a HIGH
E
Example:
l output whenever the two inputs are at the same level.
XOR and XNOR outputs are opposite.

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4-6 Exclusive OR (XOR) truth-table and circuit 4-6 Exclusive NOR (XNOR) truth-table and
symbols circuit symbols
IEEE symbol IEEE symbol
4-7 Parity Generator and Checker 4-8 Enable/Disable Circuits

A circuit is enabled when it allows the
passage of an input signal to the output.
XOR and XNOR A circuit is disabled when it prevents the
gates are useful in
passage of an input signal to the output.
circuits for parity
generation and
Situations requiring enable/disable circuits
checking.
occur frequently in digital circuit design.

4-8 Enable/Disable Circuits 4-9 Basic Characteristics of Digital ICs

A logic gate can IC “chips” consist of resistors, diodes, and transistors
be used to fabricated on a piece of semiconductor material called a
enable/disable a substrate.
circuit output. Digital ICs may be categorized according to the number
The four basic of logic gates on the substrate:
gates can either Small-scale integration (SSI) – less than 12
enable or disable Medium-scale integration (MSI) – 12 to 99
the passage of an Large -scale integration (LSI) – 100 to 9999
input signal, A, Very large-scale integration (VLSI) – 10,000 to 99,999
under control of Ultra large-scale integration (ULSI) – 100,000 to 999,999
the logic level at Giga-scale integration (GSI) – 1,000,000 or more
control input B. Ronald Tocci/Neal Widmer/Gregory
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Circuit of a CMOS 2-input NOR gate

TTL 7400 IC – 4 NAND
4-9 Basic Characteristics of Digital ICs 4-9 Basic Characteristics of Digital ICs
Dual in Line Package (DIP). PLDs have a different numbering
Pins are numbered counter-clock
wise from the identification
mark
actual silicon chip is

much smaller than the
protective package;
4-9 Basic Characteristics of Digital ICs

4-9 Basic Characteristics of Digital ICs The TTL family consists of subfamilies:
TTL sub-family Prefix Example
ICs are also categorized by the type of components Standard TTL 74 7404 – hex INVERTER
used in their circuits. TTL Schottky 74S 74S04 – hex INVERTER
Bipolar ICs use NPN and PNP transistors TTL Schottky low power 74LS 74LS04 – hex INVERTER
Unipolar ICs use FET transistors
transistors. TTL Advanced Schottky 74AS 74AS04 – hex INVERTER
The transistor-transistor logic (TTL) and the TTL Advanced Schottky low power 74ALS 74ALS04 – hex INVERTER
The 74 series devices are all part of the standard TTL series.
complementary metal-oxide semiconductor (CMOS) The 74LS series devices are all part of the low power Schottky
families will both be examined. TTL series.
The differences between devices is limited to electrical
characteristics like power dissipation and switching speed. The
pin layout and logic operations are the same.
Moss
Digital Systems: Principles and
Copyright ©2007 by Pearson Education, Inc.
Columbus, OH 43235
The 7404, 74S04, 74LS04, and 74ALS04 are all hex (six to a
chip) inverters.
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4-9 Basic Characteristics of Digital ICs

The CMOS family consists of several series, some of which 4-9 Basic Characteristics of Digital ICs
are:
CMOS sub-family Prefix Example
CMOS metal-gate 40 4001- quad NOR Power (referred to as VCC) and ground
CMOS metal-gate; TTL pin- compatible 74C 74C02 - quad NOR
connections are required for chip operation.
CMOS silicon-gate; High-speed; TTL pin-
74HC 74HC02 - quad NOR
p
compatible VCC for TTL devices is normally +5 V.V
CMOS advanced; high-speed; TTL pin-
74HCT 74HCT02 - quad NOR
compatible; TTL electric-incompatible VDD for CMOS devices can be from +3 to
CMOS advanced; TTL pin-incompatible; TTL
electric-incompatible
74AC 74AC02 - quad NOR +18V.
CMOS advanced; TTL pin-incompatible; TTL
74ACT 74ACT02 - quad NOR
electric-compatible
CMOS devices perform the same function as, but are not
necessarily pin for pin compatible with TTL devices. Ronald Tocci/Neal Widmer/Gregory
4-9 Basic Characteristics of Digital ICs 4-9 Basic Characteristics of Digital ICs
Voltages that fall in the indeterminate range will Inputs that are not connected are said to be floating.
provide unpredictable results and should be avoided. The consequences of floating inputs differ for TTL
and CMOS.
Floating TTL input acts like a logic 1. The voltage
measurement may appear in the indeterminate range, but
the device will behave as if there is a 1 on the floating
input.
Floating CMOS inputs can cause overheating and damage
to the device. Some ICs have protection circuits built in,
but the best practice is to tie all unused inputs either high
or low.
4-10 Troubleshooting Digital Systems 4-10 Troubleshooting Digital Systems

3 basic steps The logic probe will indicate the presence or
Fault detection, determine operation to expected absence of a signal when touched to a pin as
operation. indicated below.
Fault isolation, test and measure to isolate the fault.
Fault correction, repair the fault.
Good troubleshooting skills come through
experience in actual hands-on troubleshooting.
The basic troubleshooting tools used here will be:
the logic probe, oscilloscope, and logic pulser.
The most important tool is the technician’s brain.
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4-11 Internal Digital IC Faults 4-11 Internal Digital IC Faults

Most common internal failures: Malfunction in internal circuitry
Outputs do not respond properly to inputs. Outputs are unpredictable.
Malfunction in the internal circuitry. Input internally shorted to ground or supply
The input will be stuck in LOW or HIGH state.
Inputs or outputs shorted to ground or VCC
Output internally shorted to ground or supply
Inputs or outputs open-circuited Output will be stuck in LOW or HIGH state.
Short between two pins (other than ground or Open-circuited input or output
Floating input in a TTL device will result in a HIGH output. Floating
VCC) input in a CMOS device will result in erratic or possibly destructive
output.
An open output will result in a floating indication.
Short between two pins
The signal at those pins will always be identical.
4-12 External Faults 4-12 External Faults

Open signal lines – signal is prevented from moving Shorted signal lines – the same signal will appear on
between points. Some causes: two or more pins. VCC or ground may also be
Broken wire shorted. Some causes:
Sloppy wiring
Poor connections (solder or wire-wrap)
wire wrap)
Solder bridges
Cut or crack on PC board trace
Incomplete etching
Bent or broken IC pins.
Detect visually and verify with an ohmmeter.
Faulty IC socket
Detect visually and verify with an ohmmeter.

4-12 External Faults 4-12 External Faults

Faulty power supply – ICs will not operate or will Output loading – caused by connecting too many
operate erratically. inputs to the output of an IC.
May lose regulation due to an internal fault or because Causes output voltage to fall into the indeterminate range.
circuits are drawing too much current.
current This is called loading the output.
output
Always verify that power supplies are providing the Usually a result of poor design or bad connection.
specified range of voltages and are properly grounded.
Use an oscilloscope to verify that AC signals are not
present.

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4-13 Troubleshooting Case Study 4-14 Programmable Logic Devices

Example 4-28 illustrates the process involved in PLDs allow the design process to be
troubleshooting a fairly simple circuit. automated.
The reasoning process can be applied to more
Designers identify inputs, outputs, and logical
complex digital circuits.
circuits
relationships.
Take the time to carefully study the example and use
the opportunities at the end of the chapter to practice PLDs are electronically configured to form
and develop troubleshooting skills. the defined logic circuits.

4-14 Programmable Logic Devices 4-14 Programmable Logic Devices

PLD ICs can be programmed out of system or in Logic circuits can be described using schematic
system. diagrams, logic equations, truth tables, and HDL.
For out of system programming the PLD is placed in a PLD development software can convert any of these
fixture called a programmer which is connected to a PC descriptions into 1s and 0s and loaded into the PLD.
PLD
running software that translates and loads the information.
In system programming is done by connecting directly to
Altera MAX+PLUS II is an example of development
four designated “portal” pins while the IC remains in the software that allows the user to describe circuits
system. An interface cable connects the PLD to a PC using graphic design files and timing diagrams.
running the software that loads the device.

4-14 Programmable Logic Devices 4-14 Programmable Logic Devices

Hierarchical design – small logic circuits are defined A system is built from the bottom up.
and combined with other circuits to form a large Each block is described by a design file.
section of a project. Large sections can be combined The designed block is tested
and connected for form a system. After testing
g it is compiled
p using
g development
p software.
Top-down design requires the definition of sub The compiled block is tested using a simulator for verify
sections that will make up the system, and definition correct operation.
of the individual circuits that will make up each sub A PLD is programmed to verify correct operation.
section. The flowchart in figure 4-48 summarizes the design
Each level of the hierarchy can be designed and process for each block of the system.
tested individually.
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4-15 Representing Data in HDL 4-15 Representing Data in HDL

Binary, hexadecimal, and decimal values are AHDL syntax – a name for the bit vector is followed by
the range of index designations enclosed in square
represented in HDL as shown in table 4-8. brackets. This would appear in the SUBDESIGN section.
In order to describe a port with more than one data To declare an 8 bit input port called p1:
bit we assign a name and the number of bits.
bits This is p1 [7
[7..0]
0] :INPUT; -- DEFINE AN 8-BIT
8 BIT INPUT PORT
To assign the 8 bit port p1 to a node named temp:
called a bit array or bit vector. VARIABLE temp[7..0] :NODE;
BEGIN
temp[]=p1[]
END
The empty braces mean that all bits in the array are being
connected. Individual bits could be connected by
specifying the bits inside the braces.
4-15 Representing Data in HDL 4-15 Representing Data in HDL

VHDL syntax – a name for the bit vector is followed by VHDL offers some standardized data types in
the mode, the type, and the range enclosed in parenthesis.
This would appear in the ENTITY section.
libraries.
To declare an 8 bit called p1: Libraries contain collections of VHDL code that can
PORT (p1 :IN BIT_VECTOR (7 DOWNTO 0); be used to avoid reinventingg the wheel.
To assign the 8 bit port p1 to a signal named temp:
SIGNAL temp :BIT_VECTOR (7 DOWNTO 0); Many convenient functions such as standard TTL
BEGIN device descriptions are contained in macrofunctions.
temp <=p1;
END;
Since no elements are specified, all the bits will be
connected. Individual bits could be connected by placing
bit number inside parentheses.

4-16 Truth Tables Using HDL 4-17 Decision Control Structures in HDL
Circuits can be designed directly from truth tables in IF/THEN/ELSE statements provide a framework for
HDL. making logical decisions in a system.
Figures 4-50 and 4-51 describe the syntax for AHDL IF/THEN is used when there is a choice between doing
and VHDL truth tables respectively
respectively. something and doing nothing.
nothing
IF/THEN/ELSE is used when there is a choice between
two possible actions.

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4-17 Decision Control Structures in HDL 4-17 Decision Control Structures in HDL
The IF/THEN/ELSE in AHDL: The IF/THEN/ELSE in VHDL:

4-17 Decision Control Structures in HDL 4-17 Decision Control Structures in HDL
The CASE construct determines the value of an The case construct in AHDL:
expression or object and then goes through a list of
values (cases) to determine what action to take.
This is different than the IF/ELSEIF because there is
only one action or match for a case statement.

4-17 Decision Control Structures in HDL

The case construct in VHDL:

11

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Combinational Logic Circuits  Troubleshooting of combinational circuits will be introduced.

Adapted from : João Carlos Martins Ronald Tocci/Neal Widmer/Gregory

4-1 Sum-of-Products Form 4-2 Simplifying Logic Circuits

4-3 Algebraic Simplification Ex. Simplify the logic circuit

Ronald Tocci/Neal Widmer/Gregory

Ronald Tocci/Neal Widmer/Gregory Moss Copyright ©2004 by Pearson Education, Inc.

4-4 Using NAND Gates 4-5 Karnaugh Map Method

Ronald Tocci/Neal Widmer/Gregory Moss Copyright ©2007 by Pearson Education, Inc.

4-5 Karnaugh Map Method 4-5 Karnaugh Map Method

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-5 Looping Illustration 4-5 Looping Illustration

4-5 Looping Illustration 4-5 Example

4-5 Example 4-5 Indifferent terms

4-5 Example 4-6 Exclusive OR and Exclusive NOR Circuits

Ronald Tocci/Neal Widmer/Gregory

IEEE symbol IEEE symbol

4-7 Parity Generator and Checker 4-8 Enable/Disable Circuits

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-8 Enable/Disable Circuits 4-9 Basic Characteristics of Digital ICs

Circuit of a CMOS 2-input NOR gate

 actual silicon chip is

4-9 Basic Characteristics of Digital ICs

4-9 Basic Characteristics of Digital ICs

4-10 Troubleshooting Digital Systems 4-10 Troubleshooting Digital Systems

4-11 Internal Digital IC Faults 4-11 Internal Digital IC Faults

4-12 External Faults 4-12 External Faults

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-12 External Faults 4-12 External Faults

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-13 Troubleshooting Case Study 4-14 Programmable Logic Devices

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-14 Programmable Logic Devices 4-14 Programmable Logic Devices

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-14 Programmable Logic Devices 4-14 Programmable Logic Devices

4-15 Representing Data in HDL 4-15 Representing Data in HDL

4-15 Representing Data in HDL 4-15 Representing Data in HDL

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

Ronald Tocci/Neal Widmer/Gregory Ronald Tocci/Neal Widmer/Gregory

4-17 Decision Control Structures in HDL

Ronald Tocci/Neal Widmer/Gregory

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