Presented by: Engr. Ariel V.

Nicolas
 Objectives
 Describe the basic concept of an oscillator
 Discuss the basic principles of operation of an
oscillator
 Analyze the operation of RC and LC oscillators
 Describe the operation of the basic relaxation
oscillator circuits
 Introduction
 Oscillator is an electronic circuit that generates a
periodic waveform on its output without an external
signal source. It is used to convert dc to ac.
 Oscillators are circuits that produce a continuous
signal of some type without the need of an input.
 These signals serve a variety of purposes.
 Communications systems, digital systems
(including computers), and test equipment make use
of oscillators
 Oscillators
Oscillation: an effect that repeatedly and regularly
fluctuates about the mean value

Oscillator: circuit that produces oscillation

Characteristics: wave-shape, frequency, amplitude,

distortion, stability

Ref:06103104HKN 4 EE3110 Oscillator

 Application of Oscillators
Oscillators are used to generate signals, e.g.
 Used as a local oscillator to transform the RF signals to IF
signals in a receiver;
 Used to generate RF carrier in a transmitter
 Used to generate clocks in digital systems;
 Used as sweep circuits in TV sets and CRO.

Ref:06103104HKN 5 EE3110 Oscillator

Oscillators
 Oscillators are circuits that generate periodic
signals
 An oscillator converts DC power from the power
supply into AC signal power spontaneously -
without the need for an AC input source

Figure 9.67 Repetitive ramp waveform.

 Introduction
 An oscillator is a circuit that produces a repetitive signal from
a dc voltage.
 The feedback oscillator relies on a positive feedback of the
output to maintain the oscillations.
 The relaxation oscillator makes use of an RC timing circuit to
generate a nonsinusoidal signal such as square wave
Sine wave

Square wave

Sawtooth wave
 Types of oscillators
1. RC oscillators
 Wien Bridge
 Phase-Shift
2. LC oscillators
 Hartley
 Colpitts
 Crystal
3. Unijunction / relaxation oscillators
 Linear Oscillators

Figure shows a linear oscillator is formed by connecting an amplifier and

a feedback network in a loop.
 Integrant of Linear Oscillators
+ V
Vs  Amplifier (A) Vo
+
Positive Vf Frequency-Selective
Feedback Network ()
Feedback

For sinusoidal input is connected

“Linear” because the output is approximately sinusoidal

A linear oscillator contains:

- a frequency selection feedback network
- an amplifier to maintain the loop gain at unity

Ref:06103104HKN 10 EE3110 Oscillator

 Basic Linear Oscillator
+ V
Vs  A(f) Vo
+

Vf SelectiveNetwork
(f)

Vo  AV  A(Vs  V f ) and V f  Vo

V A
 o 
Vs 1  A
If Vs = 0, the only way that Vo can be nonzero
is that loop gain A=1 which implies that

| A | 1 (Barkhausen Criterion)
A  0

Ref:06103104HKN 11 EE3110 Oscillator

 Practical Design Considerations
Usually, oscillators are designed so that the loop gain
magnitude is slightly higher than unity at the desired
frequency of oscillation
This is done because if we designed for unity loop gain
magnitude a slight reduction in gain would result in
oscillations that die to zero
The drawback is that the oscillation will be slightly
distorted (the higher gain results in oscillation that grows
up to the point that will be clipped)
 Basic principles for oscillation
 The feedback oscillator is widely used for
generation of sine wave signals.
The positive (in phase) feedback arrangement
maintains the oscillations.
The feedback gain must be kept to unity to keep the
output from distorting.
 Basic principles for oscillation

In phase

Vf Vo
Av

Noninverting
amplifier

Feedback
circuit
 1. RC Oscillators
 RC feedback oscillators are generally limited to
frequencies of 1 MHz or less.

 The types of RC oscillators that we will discuss are

the Wien-bridge and the phase-shift
 Wien-bridge Oscillator
 It is a low frequency oscillator which ranges from a
few kHz to 1 MHz.
One type of feedback Rf
C1
oscillator is called the
Wien-bridge oscillator. R1  Vout
This circuit is useful for
generating low distortion + D1
sine waves. Q1
R2 C2
Lead-lag circuit R3 R4 C3
Negative feedback with
JFET gain control
JFET bias circuit
 The lead-lag circuit in the Wien-bridge oscillator has a
maximum response at the resonant frequency given by
1
fr 
Vin The lead-lag circuit
2πRC C Rfresponse is…
1
This equation is valid when Vout
R’s and C’s in the lead-lag R1  Vout
Vout ⅓Vin
circuit are equal. +
D1
Q1
Because the attenuation is R2 C2 f
⅓ at fr, the gain of the R3 R4
fr C3
Wien bridge must set for 3.
Wien-bridge oscillator

What is the frequency of the bridge?

C1 Rf
47 nF 10 kW
The frequency is given by R1  Vout
6.8 kW
1
fr  +
D1
2πRC Q1
1 R2 C2

2π  6.8 kW  47 nF  6.8 kW 47 nF R3 R4 C3
1.0 kW 10 kW 1.0 mF
 498 Hz
Wien-Bridge oscillator output

Figure 9.75 Example of output voltage of the oscillator.

 Phase-Shift Oscillator
 The phase shift oscillator utilizes three RC circuits
to provide 180º phase shift that when coupled with
the 180º of the op-amp itself provides the necessary
feedback to sustain oscillations.
 The gain must be at least 29 to maintain the
oscillations.
 The frequency of resonance for the this type is
similar to any RC circuit oscillator:

1
fr 
2 6 RC
 Phase-Shift Oscillator

1 R2
fo   29 The gain must be at least

2 6 RC
29 to maintain the
R oscillations
 2. LC Oscillators
 Use transistors and LC tuned circuits or crystals in
their feedback network.
 For hundreds of kHz to hundreds of MHz frequency
range.
 Examine Colpitts, Hartley and crystal oscillator.
 Colpitts Oscillator
 The Colpitts oscillator is a type
of oscillator that uses an LC
circuit in the feed-back loop.
 The feedback network is made
up of a pair of tapped
capacitors (C1 and C2) and an
inductor L to produce a
feedback necessary for
oscillations.
 The output voltage is
developed across C1.
 The feedback voltage is
developed across C2.
 Hartley Oscillator
 The Hartley oscillator is
almost identical to the
Colpitts oscillator.
 The primary difference
is that the feedback
network of the Hartley
oscillator uses tapped
inductors (L1 and L2) and
a single capacitor C.
 Hartley Oscillator
 the analysis of Hartley oscillator is identical to that
Colpitts oscillator.
 the frequency of oscillation:
1
o 
L1  L2 C
 Crystal Oscillator
 Most communications and digital applications require the
use of oscillators with extremely stable output. Crystal
oscillators are invented to overcome the output fluctuation
experienced by conventional oscillators.
 Crystals used in electronic applications consist of a quartz
wafer held between two metal plates and housed in a a
package as shown in Fig. 9 (a) and (b).
 Crystal Oscillator
 Piezoelectric Effect
 The quartz crystal is made of silicon oxide (SiO2) and
exhibits a property called the piezoelectric
 When a changing an alternating voltage is applied across
the crystal, it vibrates at the frequency of the applied
voltage. In the other word, the frequency of the applied ac
voltage is equal to the natural resonant frequency of the
crystal.
 The thinner the crystal, higher its frequency of vibration.
This phenomenon is called piezoelectric effect.
 Crystal Oscillator
 Characteristic of Quartz
Crystal
R
 The crystal can have two resonant
frequencies; CM
L
 One is the series resonance frequency f1
which occurs when XL = XC. At this C
frequency, crystal offers a very low
impedance to the external circuit where
Z = R.
 The other is the parallel resonance (or
antiresonance) frequency f2 which
occurs when reactance of the series leg
equals the reactance of CM. At this
frequency, crystal offers a very high
impedance to the external circuit
 3. Unijunction Oscillator
 The unijunction transistor
can be used in what is
called a relaxation oscillator
as shown by basic circuit as
follow.
 The unijunction oscillator
provides a pulse signal
suitable for digital-circuit
applications. UJT

 Resistor RT and capacitor CT

are the timing components
that set the circuit
oscillating rate
 Unijunction Oscillator
 Sawtooth wave
appears at the emitter
of the transistor.
This wave shows the
gradual increase of
capacitor voltage
 Unijunction Oscillator
 The oscillating frequency is calculated as follows:

1
fo 
RT CT ln 1 / 1   
 where, η = the unijunction transistor intrinsic stand-
off ratio
 Typically, a unijunction transistor has a stand-off
ratio from 0.4 to 0.6
FILTERS
 Filters
Background:

. Filters may be classified as either digital or analog.

. Digital filters are implemented using a digital computer

or special purpose digital hardware.

. Analog filters may be classified as either passive or

active and are usually implemented with R, L, and C
components and operational amplifiers.
 Filters
Background:

. An active filter is one that, along with R, L, and C

components, also contains an energy source,
such as that derived from an operational amplifier.

. A passive filter is one that contains only R, L, and

C components. It is not necessary that all three be
present. L is often omitted (on purpose) from
passive filter design because of the size and cost
of inductors – and they also carry along an R that
must be included in the design.
 Filters
Background:

. Generally speaking, digital filters have become the focus

of attention in the last 40 years. The interest in digital
filters started with the advent of the digital computer,
especially the affordable PC and special purpose signal
processing boards.

. A digital filter is simply the implementation of an

equation(s) in computer software. There are no R, L,
C components as such. However, digital filters can also
be built directly into special purpose computers in
hardware form. But the execution is still in software.
 Passive Analog Filters
Background: Four types of filters - “Ideal”

lowpass highpass

bandpass bandstop
 Passive Analog Filters
Background: Realistic Filters:

lowpass highpass

bandpass bandstop
 Passive Analog Filters
Low Pass Filter Consider the circuit below.

R +
+
VI C VO
_
_

Low pass filter circuit

1
VO ( jw) jwC 1
 
Vi ( jw) R 1 1  jwRC
jwC
 Passive Analog Filters
Low Pass Filter

0 dB
-3 dB . Bode

1/RC  Passes low frequencies

Attenuates high frequencies

1
x
0.707 Linear Plot

0 1/RC 
 Passive Analog Filters
High Pass Filter Consider the circuit below.

+
C
+
Vi R
_ VO
_

High Pass Filter

VO ( jw) R jwRC
 
Vi ( jw) R
1 1  jwRC
jwC
 Passive Analog Filters
High Pass Filter

0 dB
. -3 dB
Passes high frequencies
Bode
1/RC Attenuates low frequencies

1/RC 

1
0.707 x.

Linear

0 1/RC 
 Passive Analog Filters
Bandpass Pass Filter Consider the circuit shown below:

C L +
+
Vi R VO
_
_

When studying series resonant circuit we showed that;

R
VO ( s) s
 L
Vi ( s ) s 2  R s  1
L LC
 Passive Analog Filters
Bandpass Pass Filter
We can make a bandpass from the previous equation and select
the poles where we like. In a typical case we have the following shapes.

0 dB
-3 dB
. . Bode

lo hi 
1 . .
0.707
Linear

0 lo hi 
A Bandpass Filter
 Basic Active Filters
Low pass filter
C

Rfb

+ Rin +
Vin
_ VO
_
 Basic Active Filters
High pass
Rfb

C Rin
+
Vin +
_ VO
_
 Basic Active Filters

Band pass filter

R1 C2

C1 R2 R fb
R1 R2
Ri
+
Vin
_ +
VO
_
 Active filters

A
Byfilter selectsthe
reversing certain frequencies
resistors and excludes
and capacitors others.
in the low-pass
Active
circuit, filters use op-amps
a high-pass filter is to optimize
created. thefilter
This frequency
has a gain
response. A 2-pole where
of 1 at frequencies low-pass f > filter
fc. and its response is
shown. The gain for this filter is 1 (0 dB) for f < fc.
Gain (dB)
C1
R1
 00
R1 R2 Vout 3
3
V Vin
in ++ 40 dB/decade 40 dB/decade
C1 C2
R2
C2
f
fc fc
* -40dB/decade means a 40dB decrease per 10 fold change in frequency
Integrated Circuit
Processing
 Integrated Circuit Processing
Pulling ingots
Wafers
Patterning
Fabrication cycle
Testing
Packaging
CAD design of ICs
Future issues
 Pulling Ingots
 Monocrystalline silicon
is produced from
purified polycrystalline
silicon by “pulling” an
ingot
 polysilicon is melted
using radio
frequency induction
heaters
 “seed crystal” of
monocrystalline
silicon is dipped into
melt
 silicon grows around
structure of seed as
seed is slowly
withdrawn
 Pulling Ingots (continued)
Produces an ingot of pure silicon
 400 mm - 1000 mm long (15” - 39”)
 150 mm - 200 mm in diameter (6” - 8”)
Growth is a slow process
 10 - 20 hours
Silicon is often doped as it’s grown
 Wafers
Ingot is finely shaped using abrasive belts
 flat spot added for alignment during processing
Sawed into wafers about 600 microns thick
 only a few microns are actually used for IC devices
 then etched, polished, and cleaned
 stacked in carriers
 Silicon Dioxide and Polysilicon
Silicon dioxide is created by interaction between
silicon and oxygen or water vapor
 Si + O2 = SiO2 or Si + 2H2O = SiO2 + 2H2
 protects surface from contaminants
 forms insulating layer between conductors
 form barrier to dopants during diffusion or ion
implantation
 grows above and into silicon surface 40%
Polysilicon 60%
 silicon without a single crystal structure
 created when silicon is epitaxially grown on SiO2
 also a conductor, but with much more resistance than
metal or diffused layers
 commonly used (heavily doped) for gate connections in
most MOS processes
 Patterning
Patterning creates a regular pattern on the
surface of the chip, which is used to create
features of the IC
 involves alternative lithography and etching steps
 each of several layers involves a separate pattern
Lithography
 patterns are contained on masks
 eg, chrome on glass
 surface of the wafer is covered with photoresist
 organic material sensistive to uv light or X-rays
 spin and bake
 positive resist becomes more soluable when exposed
 resist will be removed where mask is clear
 negative resist becomes less soluable when exposed
 resist will be removed where mask is opaque
 Patterning (continued)
 Lithography
(continued)
 mask placed very
close to wafer,
flooded with uv light
 solvents remove
exposed (unexposed)
resist
 Etching removes
material from wafer
surface where resist
has been removed
 isotropic etching
works at same rate in
all directions of
material
 Patterning (continued)
Etching (continued)
 anisotropic etching works faster in one direction than the
other
 wet etching uses liquid solvents to remove materials
 eg, HF for SiO2
 dry etching uses gas to remove materials
 less undercutting

 can monitor reactants during process, determine

automatically when etching is finished
Finally, remaining photoresist is removed
 organic solvents or chromic acid
 pure oxygen, to oxidize organic resist materials
 Metalization
Metalization is used to create contacts with the
silicon and to make interconnections on the chip
Desired properties are
 low resistivity
 in ohms/square

 good adhesion to silicon and insulators

 good coverage of steps in chip surface
 immunity to corrosion
 ductility (so temperature cycles don’t cause failures)
 Metalization (continued)
Aluminum is common choice but
 Al causes spikes into Si, giving leaky junctions
 high currents carry Al atoms with them, creating shorts
 low melting point prohibits high heat processing later
Latest step is to use copper
 IBM has been shipping chips with copper for a year
 smaller, 50% less power consumption

 other fabs to follow soon

 NMOS Fabrication Cycle
Start with p-type silicon wafer
Grow a “passivation” layer of SiO2 (silicon dioxide)
over the entire wafer
Use lithography and a mask to define the source
and drain areas, and etch to expose the wafer
surface
 first masking step
Diffuse phosphorous to create source and drain n-
type regions
NMOS Fabrication Cycle (continued)
Use lithography and a mask to define the gate
area, and etch to expose the wafer surface
 second masking step
Grow a thin layer of SiO2 as the gate insulator
Use lithography and a mask to define the source
and drain contact areas, and etch to expose the
wafer surface
 third masking step
NMOS Fabrication Cycle (continued)
Evaporate metal (typically copper) over entire
surface of wafer
Use lithography and a mask to define the
interconnect areas, and etch away all other metal
 fourth masking step

An excellent animation of this process is

available at
http://jas.eng.buffalo.edu/applets/
education/fab/NMOS/nmos.html
 Testing
Two different kinds of testing
 process testing
 function testing
Process testing uses special patterns in separate
areas on the wafer to measure important
parameters
 resistivity of various conductive materials
 diffused or ion implanted areas
 polysilicon
 metal
 contact resistance
 line width and mask alignment
 simple components
 transistors
 capacitors
 simple logic gates
 Testing (continued)
Functional testing
 simple or regular circuits can be tested completely
 memories

 complex circuits cannot be fully tested

 test individual functions or paths

 registers
 arithmetic and logic units
 simple instructions
 data paths
 modifying designs for easier testing, and automated
visual inspection for particular flaws, are active research
areas
 Packaging
 Silicon processing steps are performed on whole wafers
 150mm to 200mm in diameter
 Packaging (continued)
 Each wafer contains many
individual chips
 5mm to 15 mm square

 Chips are scribed with a

diamond saw or diamond-
tipped scribe, or a laser,
and fractured along the
scribe lines into chips
 Packaging (continued)

 Each chip is cemented into a package

 Wire leads from pins on the package to bonding pads on
the chip are installed
 A cover is cemented over the cavity and marked
 Computer-Aided Design of ICs
 IC design started as hand
process
 leads to many errors
 requires many trial
fabrications and tests to
refine design before
production
 small batches, very expensive
 Around 1980, computer-aided
design systems began to be
used for ICs
 simple notations for
expressing components of
chip
 component libraries for
reuse of earlier designs
 and mirroring, rotation, etc.
 Computer-Aided Design of ICs
(continued)
CAD systems (continued)
 enforce design rules
 help with routing of connections
 simulation of interim designs
 2-D or 3-D device simulators

 logic simulators

 timing simulators

Design and layout happens at display

Simulation happens in batch mode
 extremely computation intensive
Once design is ready for fabrication, CAD system
produces pattern generation files
 Computer-Aided Design of ICs
(continued)
 PG files go to
mask house to
create masks
 photographic

exposure of
geometric
patterns to
produce mask
pattern
(reticle) for
one IC
 typically 10x
or more final
size
 Computer-Aided Design of ICs
(continued)
 photo enlarge to
produce “blowbacks”
for visual inspection
 create mask master by
“step and repeat” photo
reduction of reticle
 precise alignment
essential
make submaster and
working masks
 Send masks to fab line
and fabricate wafers
 IC Design Rules
Want design of IC to be independent of process
used to implement design
 especially want to scale as process technologies improve
Place constraints on widths, separations, overlaps
 base all measures on elementary distance unit l
 each process defines a value for l in microns
 pattern generator produces output files appropriately
Examples
 diffused regions >= 2 l
 minimum line width 2 l
 separation of lines >= l
 gate overlap >= l
Current processes have l = 0.18 - 0.25 microns
 Future Issues
Current state-of-the-art
 0.18 micron feature size
 die size about 2.5 cm2
 about 5.5 million transistors on logic devices
 64 Mbit DRAMS
 64 million transistors
Lithography
 wavelength of visible light is about 0.5 microns
 less than this difficult to pattern with visible light
 but 0.18 micron process is optical
 uses phase coherence with laser light
 electon beam exposure
 expose resist directly on Si (no mask)
 electron beam reticles, x-ray exposure of wafer
 good for 0.0? micron features
 physical limit of Si
 Future Issues (continued)
Die size
 yield goes down as die size goes up
 wafer scale integration
 hampered by warping of wafer since Si and SiO2 expand
and contract at different rates
Vertical stacking
Testing
 improved design for testability
 automated visual inspection
Expense management
 partnerships