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TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016
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Typical Application
L
Efficiency vs Output Current
4.7 µH
100
95
90
VIN VIN SW
C1 VPOS 85
Efficiency (%)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.5 Programming........................................................... 17
2 Applications ........................................................... 1 8.6 Register Maps ......................................................... 19
3 Description ............................................................. 1 9 Application and Implementation ........................ 26
4 Revision History..................................................... 2 9.1 Application Information............................................ 26
9.2 Typical Applications ................................................ 26
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 5 10 Power Supply Recommendations ..................... 53
7 Specifications......................................................... 8 11 Layout................................................................... 54
11.1 Layout Guidelines ................................................. 54
7.1 Absolute Maximum Ratings ...................................... 8
11.2 Layout Example .................................................... 54
7.2 ESD Ratings.............................................................. 8
7.3 Recommended Operating Conditions....................... 8 12 Device and Documentation Support ................. 55
7.4 Thermal Information .................................................. 8 12.1 Device Support...................................................... 55
7.5 Electrical Characteristics........................................... 9 12.2 Receiving Notification of Documentation Updates 55
7.6 I2C Interface Timing Requirements / Characteristics 12.3 Community Resources.......................................... 55
................................................................................. 10 12.4 Trademarks ........................................................... 55
7.7 Typical Characteristics ............................................ 11 12.5 Electrostatic Discharge Caution ............................ 55
8 Detailed Description ............................................ 12 12.6 Glossary ................................................................ 55
8.1 Overview ................................................................. 12 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 12 Information ........................................................... 55
8.3 Feature Description................................................. 12 13.1 CSP Package Summary ...................................... 56
8.4 Device Functional Modes........................................ 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed package type to industry standard identifier in the Device Information table ........................................................ 1
VPOS = 5.4 V
TPS65132A
VNEG = –5.4 V
80 mA 40 mA VPOS / VNEG FAST 30 µA CSP
VPOS = 5.0 V
TPS65132A0
VNEG = –5.0 V
VPOS = 5.4 V
TPS65132B
VNEG = –5.4V
VPOS = 5.0 V
TPS65132B0 80 mA 40 mA VPOS / VNEG FAST 130 nA CSP
VNEG = –5.0 V
VPOS = 5.5 V
TPS65132B5
VNEG = –5.5 V
VPOS = 5.2 V
TPS65132B2
VNEG = –5.2 V
VPOS = 5.4 V
TPS65132L 80 mA 40 mA VPOS / VNEG SLOW 130 nA CSP
VNEG = –5.4 V
VPOS = 5.0 V
TPS65132L0
VNEG = –5.0 V
(4) VPOS = 5.1 V
TPS65132L1 80 mA 40 mA VPOS / VNEG SLOW 130 nA CSP
VNEG = –5.1 V
VPOS = 5.6 V
TPS65132T6 80 mA 80 mA VPOS / VNEG SLOW 130 nA CSP
VNEG = –5.6 V
VPOS = 5.4 V
TPS65132S 150 mA 80 mA VPOS / VNEG SLOW 130 nA CSP
VNEG = –5.4 V
VPOS = 5.4 V
TPS65132W 80 mA 80 mA VPOS / VNEG SLOW 130 nA QFN
VNEG = –5.4 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com
(2) See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant
implements the active discharge function.
(3) Please refer to Power-Up And Soft-Start (LDO) and Power-Up And Soft-Start (CPN) for more details.
(4) Product preview.
YFF Package
15 Bumps
(top view) (bottom view)
TPS65132Ax / Bx / Lx / Tx TPS65132Ax / Bx / Lx / Tx
3 2 1 1 2 3
3 2 1 1 2 3
Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: TPS65132
TPS65132
SLVSBM1H – JUNE 2013 – REVISED NOVEMBER 2016 www.ti.com
Pin Functions
PIN
I/O DESCRIPTION
NAME Ax, Bx, Lx, Tx Sx
AGND D2 D2 — Analog ground
CFLY1 C3 C3 I/O Negative charge pump flying capacitor pin
CFLY2 A3 A3 I/O Negative charge pump flying capacitor pin
EN — B1 Enable pin (sequence programmed)
ENN A1 — I Enable pin for VNEG rail
ENP B1 B1 I Enable pin for VPOS rail
OUTP E3 E3 O Output pin of the LDO (VPOS)
OUTN A2 A2 O Output pin of the negative charge pump (VNEG)
B3 B3
PGND — Power ground
E1 E1
D3 D3
REG I/O Boost converter output pin
E2 E2
SCL B2 B2 I/O I²C interface clock signal pin
SDA C2 C2 I/O I²C interface data signal pin
SW D1 D1 I/O Switch pin of the boost converter
SYNC — A1 I Synchronization pin. 150 mA current enabled if this pin is pulled HIGH.
VIN C1 C1 I Input voltage supply pin
QFN Package
20 Pins
AGND
AGND
REG
REG
SW
SW
SW
SW
20 19 18 17 17 18 19 20
7 8 9 10 10 9 8 7
SDA
SCL
OUTN
CFLY2
CFLY2
OUTN
SCL
SDA
Pin Functions
PIN
I/O DESCRIPTION
NAME Wx
3
AGND — Analog ground
17
CFLY1 13 I/O Negative charge pump flying capacitor pin
CFLY2 10 I/O Negative charge pump flying capacitor pin
ENN 6 I Enable pin for VNEG rail
ENP 5 I Enable pin for VPOS rail
16
OUTP O Output pin of the LDO (VPOS)
15
OUTN 9 O Output pin of the negative charge pump (VNEG)
1
2
PGND — Power ground
11
12
14
REG I/O Boost converter output pin
18
SCL 8 I/O I²C interface clock signal pin
SDA 7 I/O I²C interface data signal pin
19
SW I/O Switch pin of the boost converter
20
VIN 4 I Input voltage supply pin
7 Specifications
7.1 Absolute Maximum Ratings (1) (2)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC,
–0.3 7 V
Voltage range VIN
CFLY2, OUTN –7 0.3 V
Continuous total power dissipation See Thermal Information
Operating junction temperature, TJ –40 150 °C
Operating ambient temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to ground.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Industry standard I2C timing characteristics according to I2C-Bus Specification, Version 2.1, January 2000. Not tested in production.
SDA
tf tLOW tf tBUF
tsu;DAT thd;STA tr
tr
SCL
3 0.6
VIN = 2.9 V VIN = 2.9 V
0.58
2.5 VIN = 3.7 V VIN = 3.7 V
0.56
VIN = 4.5 V VIN = 4.5 V
2 0.54
0.52
Isd (µA)
Iq (mA)
1.5 0.5
0.48
1
0.46
0.5 0.44
0.42
0 0.4
-40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80
Ta (ƒC) C04 Ta (ƒC) C04
Figure 2. Shutdown Current (all versions but Ax) Figure 3. Quiescent Current
1.2 2.5
VIN = 2.9 V UVLO_rising
1.15
VIN = 3.7 V 2.45 UVLO_falling
1.1 VIN = 4.5 V
2.4
Fosc (MHz)
1.05
VIN (V)
1 2.35
0.95
2.3
0.9
2.25
0.85
0.8 2.2
-40 10 60 -40 -20 0 20 40 60 80
Ta (ƒC) C03 Ta (ƒC) C03
8 Detailed Description
8.1 Overview
The TPS65132, supporting input voltage range from 2.5 V to 5.5 V, operates with a single inductor scheme to
provide a high efficiency with a small solution size. The synchronous boost converter generates a positive
voltage that is regulated down by an integrated LDO, providing the positive supply rail (VPOS). The negative
supply rail (VNEG) is generated by an integrated negative charge pump (or CPN) driven from the boost converter
output pin, REG. The operating mode can be selected between 40mA and 80mA in order to select the necessary
output current capability and to get the best efficiency possible based on the application. The device topology
allows a 100% asymmetry of the output currents.
SW REG
VIN SYNC OUTP VPOS
VIN LDO
BOOST 5.4 V/40 mA
(battery voltage)
CFLY2
SCL
SDA AGND
2 2
VREG_AC VREG_AC
VSW
VSW
3 3
IL
IL
4 4
Ch2 50.0 mV/div Ch4 100 mA/div Ch2 50.0 mV/div Ch4 100 mA/div
1 µs/div 1 µs/div
Ch3 2.00 V/div Ch3 2.00 V/div
Figure 6. Boost Converter - Light Load (1 mA) Figure 7. Boost Converter — Heavy Load (40 mA)
8.3.5.1 Operation
The negative charge pump (CPN) generates the negative voltage rail, VNEG, by inverting and regulating the
output voltage of the boost converter (VREG). The charge pump uses 4 switches and an external flying capacitor
to generate the negative rail. Two of the switches are turned on in the first phase to charge the flying capacitor
up to VREG, and in the second phase they are turned-off and the two others turn on to pump the energy
negatively out of the OUTN capacitor.
ISTARTUP = output current of the VNEG rail charging up the output capacitor at startup (12.5 mA, 25 mA, 50 mA
or 100 mA as described above)
8.5 Programming
8.5.1 I2C Serial Interface Description
The TPS65132 communicates through an industry standard I2C compatible interface, to receive data in slave
mode. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version
2.1, January 2000).
The TPS65132 integrates a non-volatile memory (EEPROM) that allows the storage of the register values with a
capability of up to 1000 programming cycles. At startup the TPS65132 loads first the EEPROM content into the
registers and uses these voltages to start.
It is recommended to stop I2C communication with the TPS65132 for 50 ms after the command "Write EEPROM
data" was sent. If the device is accessed via I2C during EEPROM programming, the device will pull down the
SCL line (clock stretch) after it recognized its I2C address. The SCL line will be released after EEPROM
programming is finished.
The TPS65132 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus
specification: standard mode (100 kbps) and fast mode (400 kbps). The data transfer protocol for standard and
fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The TPS65132
supports 7-bit addressing. The device 7-bit address is 3E (see Figure 8), and the LSB enables the write or read
function.
Figure 8. TPS65132 Slave Address Byte
MSB TPS65132 Address LSB
0 1 1 1 1 1 0 R/W
R/W = R/(W)
NOTE
With TPS65132Ax, the I2C interface is accessible as long as the input voltage is above
the undervoltage lockout threshold. In all other versions, the I2C interface is accessible
only as soon as one of the enable pins is pulled HIGH while the input voltage is above the
undervoltage lockout.
“0” Write
1 7 1 1 8 1 8 1 8 1
S Slave Address R/W A Register Address (n) A Data nth Register A Data (n+1)th Register A
“0” Write
8 1 1
1 7 1 1 8 1 8 1 1
1 7 1 1 8 1 8 1 1
1 7 1 1 8 1 1 7 1 1 8 1 1
1 7 1 1 8 1 8 1 1
1 7 1 1 8 1 1 7 1 1 8 1
th
S Slave Address R/W A Register Address A Sr Slave Address R/W A Data n Register A
8 1 8 1 1
th
Data (n+1) Register A Data (Last) Register A P
8.6.1 Registers
Attempting to read data from register addresses not listed in the following section will result in 0x00 being read
out.
(1) SEQU and SEQD bits are just valid for TPS65132Sx
(2) See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant
implements the active discharge function.
Register address
Part number
0x00 0x01 0x02 0x03
TPS65132A 0x0E 0x0E — 0x03
TPS65132A0 0x0A 0x0A — 0x03
TPS65132B 0x0E 0x0E — 0x03
TPS65132B0 0x0A 0x0A — 0x03
TPS65132B2 0x0C 0x0C — 0x03
TPS65132B5 0x0F 0x0F — 0x03
TPS65132L 0x0E 0x0E — 0x03
TPS65132L0 0x0A 0x0A — 0x03
(1)
TPS65132L1 0x0B 0x0B — 0x03
TPS65132S 0x0E 0x0E 0x00 0x43
TPS65132T6 0x10h 0x10h — 0x43
TPS65132W 0x0E 0x0E — 0x43
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VIN VIN SW
2.5V to 5.5 V C1 VPOS
4.7 µF OUTP
C3 5.4 V/40 mA
ENP REG 4.7 µF
C2
ENN 4.7 µF
VNEG
SCL OUTN
SDA –5.4 V/40 mA
C5
4.7 µF
PGND CFLY1 C4
AGND CFLY2 2.2 µF
9.2.1.2.1 Sequencing
Each output rail (VPOS and VNEG) is enabled and disabled using an external enable signal. If not explicitly
specified, the enable signal in the rest of the document refers to ENN or ENP: ENP for the positive rail VPOS and
ENN for the negative rail VNEG. Figure 33 to Figure 36 show the typical sequencing waveforms.
NOTE
In the case where VIN falls below the UVLO threshold while one of the enable signals is
still high, all converters will be shut down instantaneously and both VPOS and VNEG output
rails will be actively discharged to GND.
VIN_min ´ η
1. Duty Cycle: D = 1 -
VVS
REG
VIN_min ´ D
2. Inductor ripple current: ΔIL =
fSW ´ L
æ DIL ö
3. Maximum output current: IOUT_max = ç ILIM_min + ´ (1 - D )
è 2 ÷ø
I DI
4. Peak switch current of the application: ISWPEAK = OUT + L
1- D 2
η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)
ƒSW = Boost converter switching frequency (1.8 MHz)
L = Selected inductor value for the boost converter (see the Inductor Selection section)
ISWPEAK = Boost converter switch current at the desired output current (must be < [ ILIM_min + ΔIL])
ΔIL = Inductor peak-to-peak ripple current
VREG = max (VPOS, |VNEG|) + 200 mV (in 40mA mode — + 300 mV in 80mA mode — + 500 mV with
TPS65132Sx with SYNC = HIGH)
IOUT = IOUT_VPOS + | IOUT_VNEG| (IOUT_max being the maximum current delivered on each rail)
The peak switch current is the current that the integrated switch and the inductor have to handle. The calculation
must be done for the minimum input voltage where the peak switch current is highest.
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
100 100
95 95
90 90
85 85
Efficiency (%)
Efficiency (%)
80 80
75 75
70 70
65 VIN = 4.5V 65 VIN = 4.5V
60 60
VIN = 3.7V VIN = 3.7V
55 55
VIN = 2.8V VIN = 2.8V
50 50
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
IOUT (mA) C005 IOUT (mA) C006
Figure 20. Combined Efficiency — 40mA Mode Figure 21. Combined Efficiency — 40mA Mode
100 100
95 95
90 90
85 85
Efficiency (%)
Efficiency (%)
80 80
75 75
70 70
65 VIN = 4.5V 65 VIN = 4.5V
60 60
VIN = 3.7V VIN = 3.7V
55 55
VIN = 2.8V VIN = 2.8V
50 50
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
IOUT (mA) C003 IOUT (mA) C004
Figure 22. Combined Efficiency — 40mA Mode Figure 23. Combined Efficiency — 40mA Mode
1 1
R2
R1
R2 R1
R1 20.0mV AC BW R1 20.0mV AC BW
R2 20.0mV AC BW R2 20.0mV AC BW
Figure 24. VNEG Output Voltage Ripple — 40mA Mode Figure 25. VNEG Output Voltage Ripple — 40mA Mode
VPOS_AC
1
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
4 4
Figure 27. Load Transient — 40mA Mode Figure 28. Load Transient — 40mA Mode
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
IPOS = - INEG
4 3 VIN
Figure 29. Load Transient — 40mA Mode Figure 30. Line Transient — 40mA Mode
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
3 VIN 3 VIN
Figure 31. Line Transient — 40mA Mode Figure 32. Line Transient — 40mA Mode
ENP ENP
1 1
ENN ENN
R2
R2
VREG VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 33. Power-Up Sequencing — Simultaneous Figure 34. Power-Down Sequencing — Simultaneous
(with Active Discharge)
ENP ENP
1 1
ENN ENN
R2 R2
VREG VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 35. Power-Up Sequencing — Sequential Figure 36. Power-Down Sequencing — Sequential
(with Active Discharge)
ENP ENP
1 1
ENN ENN
R2 R2
VSW VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 37. Power-Up/Down With Active Discharge Figure 38. Power-Up/Down Without Active Discharge
(TPS65132Ax only)
VREG VREG
1 1
VPOS VPOS
2 2
3 3
VNEG VNEG
IIN IIN
4 4
Figure 39. Inrush Current — Simultaneous Figure 40. Inrush Current — Sequential
VREG VREG
1 1
VPOS VPOS
2 2
3 3
VNEG VNEG
IIN IIN
4 4
Figure 41. Inrush Current — Simultaneous Figure 42. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Tx, –Wx) (TPS65132B2, –Lx, –Sx, –Tx, –Wx)
5.05 5.45
40mA Mode ; 4.7 µH 40mA Mode ; 4.7 µH
5.04 5.44
40mA Mode ; 2.2 µH 40mA Mode ; 2.2 µH
5.03 5.43
5.02 5.42
5.41
VPOS (V)
5.01
VPOS (V)
5.00 5.40
4.99 5.39
4.98 5.38
4.97 5.37
4.96 5.36
4.95 5.35
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
IOUT (mA) C008 IOUT (mA) C009
-4.95 -5.35
40mA Mode ; 4.7 µH 40mA Mode ; 4.7 µH
-4.96 -5.36
40mA Mode ; 2.2 µH 40mA Mode ; 2.2 µH
-4.97 -5.37
-4.98 -5.38
VNEG (V)
VNEG (V)
-4.99 -5.39
-5.00 -5.40
-5.01 -5.41
-5.02 -5.42
-5.03 -5.43
-5.04 -5.44
-5.05 -5.45
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40
IOUT (mA) C01 IOUT (mA) C01
5.02 5.42
40mA Mode ; 4.7 µH 40mA Mode ; 4.7 µH
5.00 5.40
VPOS (V)
VPOS (V)
4.99 5.39
4.98 5.38
4.97 5.37
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C01 VIN (V) C01
-4.96 -5.36
40mA Mode ; 4.7 µH 40mA Mode ; 4.7 µH
VNEG (V)
-4.98 -5.38
-4.99 -5.39
-5.00 -5.40
-5.01 -5.41
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C01 VIN (V) C01
L
2.2 µH
VIN VIN SW
2.5V to 5.5 V C1 VPOS
4.7 µF OUTP
C3 5.4 V/80 mA
ENP REG 10 µF
C2
ENN 10 µF
VNEG
SCL OUTN
SDA –5.4 V/80 mA
C5
10 µF
PGND CFLY1 C4
AGND CFLY2 4.7 µF
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
100 100
95 95
90 90
85 85
Efficiency (%)
Efficiency (%)
80 80
75 75
70 70
65 VIN = 4.5V 65 VIN = 4.5V
60 60
VIN = 3.7V VIN = 3.7V
55 55
VIN = 2.8V VIN = 2.8V
50 50
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA) C001 IOUT (mA) C002
Figure 52. Combined Efficiency — 80mA Mode Figure 53. Combined Efficiency — 80mA Mode
1 1
R1 R2
R2 R1
R2 20.0mV AC BW R2 20.0mV AC BW
Figure 54. VNEG Output Voltage Ripple — 80mA Mode Figure 55. VNEG Output Voltage Ripple — 80mA Mode
VPOS_AC
1
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
4 4
IPOS = - INEG IPOS = - INEG
Figure 57. Load Transient — 80mA Mode Figure 58. Load Transient — 80mA Mode
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
4
IPOS = - INEG
3 VIN
Figure 59. Load Transient — 80mA Mode Figure 60. Line Transient — 80mA Mode
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
3 VIN 3 VIN
Figure 61. Line Transient — 80mA Mode Figure 62. Line Transient — 80mA Mode
ENP ENP
1 1
ENN ENN
R2
R2
VREG VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 63. Power-Up Sequencing — Simultaneous Figure 64. Power-Down Sequencing — Simultaneous
(with Active Discharge)
ENP ENP
1 1
ENN ENN
R2 R2
VREG VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 65. Power-Up Sequencing — Sequential Figure 66. Power-Down Sequencing — Sequential
(with Active Discharge)
ENP ENP
1 1
ENN ENN
R2 R2
VSW VSW
2 2
VPOS VPOS
3 3
4 4
VNEG VNEG
R2 5.0V R2 5.0V
Figure 67. Power-Up/Down With Active Discharge Figure 68. Power-Up/Down Without Active Discharge
(TPS65132Ax only)
VREG VREG
1 1
VPOS VPOS
2 2
3 3
VNEG VNEG
IIN IIN
4 4
Figure 69. Inrush Current — Simultaneous Figure 70. Inrush Current — Sequential
VREG VREG
1 1
VPOS VPOS
2 2
3 3
VNEG VNEG
IIN IIN
4 4
Figure 71. Inrush Current — Simultaneous Figure 72. Inrush Current — Sequential
(TPS65132B2, –Lx, –Sx, –Wx) (TPS65132B2, –Lx, –Sx, –Wx)
5.05 5.45
80mA Mode ; 2.2 µH 80mA Mode ; 2.2 µH
5.04 5.44
5.03 5.43
5.02 5.42
5.01 5.41
VPOS (V)
VPOS (V)
5.00 5.40
4.99 5.39
4.98 5.38
4.97 5.37
4.96 5.36
4.95 5.35
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA) C016 IOUT (mA) C017
-4.95 -5.35
80mA Mode ; 2.2 µH 80mA Mode ; 2.2 µH
-4.96 -5.36
-4.97 -5.37
-4.98 -5.38
VNEG (V)
VNEG (V)
-4.99 -5.39
-5.00 -5.40
-5.01 -5.41
-5.02 -5.42
-5.03 -5.43
-5.04 -5.44
-5.05 -5.45
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IOUT (mA) C01 IOUT (mA) C01
5.01 5.41
80mA Mode ; 2.2 µH 80mA Mode ; 2.2 µH
5.00 5.40
4.99 5.39
VPOS (V)
VPOS (V)
4.98 5.38
4.97 5.37
4.96 5.36
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C02 VIN (V) C02
-4.97 -5.37
80mA Mode ; 2.2 µH 80mA Mode ; 2.2 µH
-4.98 -5.38
VNEG (V)
VNEG (V)
-4.99 -5.39
-5.00 -5.40
-5.01 -5.41
-5.02 -5.42
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C02 VIN (V) C02
L
2.2 µH
VIN VIN SW
2.5V to 5.5 V C1 VPOS
4.7 µF OUTP
C3 5.4 V/150 mA
EN REG 10 µF
C2
SYNC 10 µF
VNEG
SCL OUTN
SDA –5.4 V/150 mA
C5
10 µF
PGND CFLY1 C4
AGND CFLY2 4.7 µF
9.2.3.2.1 Sequencing
The output rails (VPOS and VNEG) are enabled and disabled using an external logic signal on the EN pin. The
power-up and power-down sequencing events are programmable. Please refer to Programmable Sequencing
Scenarios for the different sequencing as well as Registers for the programming options. Figure 98 to Figure 103
show the typical sequencing waveforms.
EN EN EN
DLYP1
DLYP1 DLYP1
VPOS VPOS VPOS
VNEG VNEG VNEG
DLYN1 DLYN1
EN EN EN
NOTE
• In the case where the UVLO falling threshold is triggered while the enable signal is still
HIGH (EN), all converters will be shut down instantaneously and both VPOS and VNEG
output rails will be actively discharged to GND.
• The power-up and power-down sequencing must be finalized (all delays have passed)
before re-toggling the EN pin.
9.2.3.2.3 Startup
The TPS65132Sx can startup with SYNC = HIGH, however, the boost offset as well as the 150 mA output
current capability will only be available as soon as the last rail to start is in regulation.
spacer
NOTE
In this section, IOUT means that the outputs are loaded with IPOS = –INEG simultaneously.
100 100
95 95
90 90
85 85
Efficiency (%)
Efficiency (%)
80 80
75 75
70 70
65 VIN = 4.5V 65 VIN = 4.5V
60 60
VIN = 3.7V VIN = 3.7V
55 55
VIN = 2.8V VIN = 2.8V
50 50
0 10 20 30 40 50 60 70 80 90 100110120130140150 0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA) C02 IOUT (mA) C02
Figure 83. Combined Efficiency — ± 5.0 V — SYNC = HIGH Figure 84. Combined Efficiency — ± 5.4 V — SYNC = HIGH
L = 2.2 µH L = 2.2 µH
R1
R1R1 50.0mV
50.0mVACACBWBW
R2 50.0mV AC BW
Figure 85. VPOS Output Voltage Ripple — SYNC = HIGH Figure 86. VNEG Output Voltage Ripple — SYNC = HIGH —
L = 2.2 µH — COUT = 10 µF
R2
R1
R1 50.0mV AC BW
R2 50.0mV AC BW
SYNC SYNC
1 1
VREG_AC VREG_AC
2 2
VPOS VPOS
3 3
VNEG VNEG
4 4
Figure 88. SYNC Signal — IOUT = 10 mA Figure 89. SYNC Signal — IOUT = 150 mA
SYNC SYNC
1 1
VREG
2 2
VREG
VPOS VPOS
3 3
VNEG VNEG
4 4
Figure 90. SYNC = HIGH (zoom) Figure 91. SYNC = LOW (zoom) with Delay
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
Figure 92. Load Transient — VIN = 2.9 V Figure 93. Load Transient — VIN = 3.7 V
SYNC = HIGH — ΔIOUT = 140 mA SYNC = HIGH — ΔIOUT = 140 mA
VPOS_AC
VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
IPOS = - INEG
4 3 VIN
Figure 94. Load Transient — VIN = 4.5 V Figure 95. Line Transient — IOUT = 10 mA
SYNC = HIGH — ΔIOUT = 140 mA SYNC = HIGH — ΔVIN = 1.7 V
VPOS_AC VPOS_AC
1 1
VNEG_AC VNEG_AC
2 2
3 VIN 3 VIN
Figure 96. Line Transient — IOUT = 100 mA Figure 97. Line Transient — IOUT = 150 mA
SYNC = HIGH — ΔVIN = 1.7 V SYNC = HIGH — ΔVIN = 1.7 V
EN
1
EN
1
VSW
2
VREG
2
VPOS
3
VPOS
3 VNEG
4
VNEG
4
Figure 98. Power-Up Sequencing — Simultaneous Figure 99. Power-Down Sequencing — Simultaneous
SYNC = HIGH SYNC = HIGH
EN
1
EN
1 VSW
2
VREG
2
VPOS
3
VPOS
3
4
VNEG VNEG
4
Figure 100. Power-Up Sequencing — Sequential Figure 101. Power-Down Sequencing — Sequential
VPOS → VNEG — SYNC = HIGH VNEG → VPOS— SYNC = HIGH
EN
1
EN
1 VSW
2
VREG
2
VPOS
3
VPOS
3
4
VNEG VNEG
4
Figure 102. Power-Up Sequencing — Sequential Figure 103. Power-Down Sequencing — Sequential
VNEG → VPOS — SYNC = HIGH VPOS → VNEG — SYNC = HIGH
EN EN
1 1
VSW VSW
2 2
VPOS VPOS
3 3
VNEG VNEG
4 4
Figure 104. Power-Up/Down Without Active Discharge — Figure 105. Power-Up/Down With Active Discharge —
SYNC = HIGH SYNC = HIGH
VREG VREG
1 1
VPOS VPOS
2 2
3 3
VNEG VNEG
IIN IIN
4 4
Figure 106. Inrush Current — Simultaneous — Figure 107. Inrush Current — Sequential
SYNC = HIGH SYNC = HIGH
5.05 5.45
5.04 SYNC = HIGH_2.2µH 5.44 SYNC = HIGH_2.2µH
5.03 5.43
5.02 5.42
5.01 5.41
VPOS (V)
VPOS (V)
5.00 5.40
4.99 5.39
4.98 5.38
4.97 5.37
4.96 5.36
4.95 5.35
0 10 20 30 40 50 60 70 80 90 100110120130140150 0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA) C02 IOUT (mA) C02
Figure 108. Load Regulation VPOS = 5.0 V — SYNC = HIGH Figure 109. Load Regulation VPOS = 5.4 V — SYNC = HIGH
-4.95 -5.35
-4.96 SYNC = HIGH_2.2µH -5.36 SYNC = HIGH_2.2µH
-4.97 -5.37
-4.98 -5.38
VNEG (V)
VNEG (V)
-4.99 -5.39
-5.00 -5.40
-5.01 -5.41
-5.02 -5.42
-5.03 -5.43
-5.04 -5.44
-5.05 -5.45
0 10 20 30 40 50 60 70 80 90 100110120130140150 0 10 20 30 40 50 60 70 80 90 100110120130140150
IOUT (mA) C02 IOUT (mA) C02
Figure 110. Load Regulation VNEG = –5.0 V — SYNC = Figure 111. Load Regulation VNEG = –5.4 V — SYNC =
HIGH HIGH
5.03 -4.97
SYNC = HIGH_2.2 µH SYNC = HIGH_2.2 µH
5.02 -4.98
5.01 -4.99
VNEG (V)
VNEG (V)
5.00 -5.00
4.99 -5.01
4.98 -5.02
4.97 -5.03
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C03 VIN (V) C03
Figure 112. Line Regulation VPOS = 5.0 V — SYNC = HIGH Figure 113. Line Regulation VPOS = 5.4 V — SYNC = HIGH
-4.97 -5.37
80mA Mode ; 2.2 µH SYNC = HIGH_2.2 µH
-4.98 -5.38
VNEG (V)
-5.39
VNEG (V)
-4.99
-5.00 -5.40
-5.01 -5.41
-5.02 -5.42
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V) C02 VIN (V) C03
Figure 114. Line Regulation VNEG = –5.0 V — SYNC = HIGH Figure 115. Line Regulation VNEG = –5.4 V — SYNC = HIGH
11 Layout
C5
C2
L1
ENN OUTN CFLY2
AGND
REG
SW
SW
ENP PGND C4
C1 SCL
20 19 18 17
VIN CFLY1
SDA
PGND 1 16 OUTP
SW REG
AGND
L1 PGND 2 15 OUTP C3
PGND REG OUTP
AGND
C3 C1 3 14 REG
PowerPAD
C2 VIN 4 13 CFLY1
PGND
ENP 5 12
C4
Via to signal layer on internal or bottom layer. ENN 6 11
PGND
7 8 9 10
SDA
SCL
OUTN
CFLY2
C5
Figure 116. PCB Layout Example for CSP Package Figure 117. PCB Layout Example for QFN Package
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
E1 E2 E3
D1 D2 D3
TIYMLLLL S
65132xx
D C1 C2 C3
TPS
B1 B2 B3
A1 A2 A3
Ball A1
Code:
TI -- TI letters
YM -- Year-Month date code
LLLL -- Lot trace code
S -- Assembly site code
xx -- Revision code (contains alpha-numeric characters - can be left
blank), refer to the Ordering Information section for detailed information)
11 12 13 14 15 16
10 17
18
9
65132xx
TI YMS PowerPAD
LLLL
8 19
7 20
5 4 3 2 1
6
Pin 1
Code:
TI -- TI letters
YM -- Year-Month date code
LLLL -- Lot trace code
S -- Assembly site code
xx -- Revision code (contains alpha-numeric characters - can be left
blank), refer to the Ordering Information section for detailed information)
www.ti.com 18-Nov-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS65132A0YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132A0
TPS65132AYFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132A
TPS65132B0YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132B0
TPS65132B2YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132B2
TPS65132B5YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132B5
TPS65132BYFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132B
TPS65132L0YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132L0
TPS65132L0YFFT ACTIVE DSBGA YFF 15 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132L0
TPS65132LYFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132L
TPS65132SYFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132S
TPS65132T6YFFR ACTIVE DSBGA YFF 15 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132T6
TPS65132T6YFFT ACTIVE DSBGA YFF 15 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 TPS
& no Sb/Br) 65132T6
TPS65132WRVCR ACTIVE WQFN RVC 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 65132YA
& no Sb/Br)
TPS65132WRVCT ACTIVE WQFN RVC 20 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 65132YA
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 18-Nov-2016
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Nov-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Nov-2016
Pack Materials-Page 2
D: Max = 2.138 mm, Min =2.078 mm
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