CHAPTER 1

OVERVIEW

1.1 INTRODUCTION:
In today’s world secured data transmission has prior role. Many applications need
secured data transmission for privacy of data. Basically the project objective is to encrypt the data
at the transmitter section and is decrypted at the receiver section. In this section we implement
one bit data transmission.

1.2 Aim of the project:

The aim of this project is to transmit the data securely using RF. The data to
be sent over channel is encrypted at the transmitter and decrypted at the receiver with a
microcontroller. The data is modulated using the Amplitude Shift Keying scheme.

1.3 Methodology:
Data encryption is the process where the data to be sent is coded which can be
decoded only by the receiver which has the corresponding decoding technique. Data
decryption is the process where the data is decoded at the receiver. Here data is given with
the help of a 4*4 hex keyboard which is connected to the port 0 of the microcontroller. The data
received by the microcontroller is encrypted in the microcontroller itself and the encoded data is
given to HT640, connected to port 1, which converts parallel data to serial data. The serial data is
sent to the RF transmitter which transmits the encoded data with the help of an antenna.

At the receiver side the encoded data is received with the help of an antenna by
the RF receiver. The received data is given to HT648, connected to port 1 of another
microcontroller at the receiver side, which converts the serial data to parallel data and gives it to
the microcontroller. Microcontroller decrypts the data and gives it to port 0. LCD display is
interfaced at port 0 which displays the data, which is typed at the transmitter side. Pins P2.4, P2.5
and P2.6 are used for RS, R/W and E pins of the LCD display respectively. 10K pot is used to
adjust the contrast of the LCD display.

Keil software has been used to write and dump the program into the microcontroller.

1
1.4 Significance of the work:

Encryption has long been used by militaries and governments to facilitate

secret communication. Encryption is now commonly used in protecting information
within many kinds of civilian systems. In recent years there have been numerous reports
of confidential data such as customers' personal records being exposed through loss or
theft of laptops or backup drives. Encrypting such files at rest helps protect them should
physical security measures fail.

Encryption is also used to protect data in transit, for example data being
transferred via networks (e.g. the Internet, e-commerce), mobile telephones, wireless
microphones, wireless intercom systems, Bluetooth devices and bank automatic teller
machines. There have been numerous reports of data in transit being intercepted in recent
years. Encrypting data in transit also helps to secure it as it is often difficult to physically
secure all access to networks.

Encryption, by itself, can protect the confidentiality of messages, but other

techniques are still needed to protect the integrity and authenticity of a message; for
example, verification of a message authentication codes (MAC) or a digital signature.
Standards and cryptographic software and hardware to perform encryption are widely
available, but successfully using encryption to ensure security may be a challenging
problem. A single slip-up in system design or execution can allow successful attacks.
Sometimes an adversary can obtain unencrypted information without directly undoing the
encryption.

1.5 Organization of the Report:

The chapters are arranged in the following manner

Chapter 1 deals with introduction, aim of the project, methodology, significance of

work, organization of the project.

2
Chapter 2,3,4,5,6 discusses about the introduction to Microcontroller and other hardware
units along with their features that have been used in the project with complete circuit
description and necessary block diagrams and pin diagrams.

Chapter 7 explains in detail about the software used like Keil.

Chapter 8 shows the shows the circuit diagram of the transmitter and receiver section.

Chapter 9 gives the source code for the transmitter and receiver section.

Chapter 10 concludes the project by showing the results obtained from the execution of
the above code and implementation of data encryption and decryption along with its
future scope and the references used are listed.

3
CHAPTER 2

MICROCONTOROLLER

2.1 A Brief History of 8051:

In 1981, Intel Corporation introduced an 8 bit microcontroller called 8051.

This microcontroller had 128 bytes of RAM, 4K bytes of chip ROM, two timers, one
serial port, and four ports all on a single chip. At the time it was also referred as “A
SYSTEM ON A CHIP”

The 8051 is an 8-bit processor meaning that the CPU can work only on 8 bits data
at a time. Data larger than 8 bits has to be broken into 8 bits pieces to be processed by the
CPU. The 8051 has a total of four I\O ports each 8 bit wide.

There are many versions of 8051 with different speeds and amount of on-chip ROM and
they are all compatible with the original 8051. This means that if you write a program for
one it will run on any of them.

The 8051 is an original member of the 8051 family. There are two other members in the
8051 family of microcontrollers. They are 8052 and 8031. All the three microcontrollers
will have the same internal architecture, but they differ in the following aspects.

 8031 has 128 bytes of RAM, two timers and 6 interrupts.

 89C51 has 4KB ROM, 128 bytes of RAM, two timers and 6 interrupts.

 89C52 has 8KB ROM, 128 bytes of RAM, three timers and 8 interrupts.

Of the three microcontrollers, 89C51 is the most preferable. Microcontroller supports

both serial and parallel communication.

Features:
 Compatible with MCS-51 Products

4
  4 Kbytes of In-System Reprogrammable Flash Memory. Endurance 1,000
Write/Erase Cycles

 Fully Static Operation: 0 Hz to 24 MHz

 Three-Level Program Memory Lock

 128 x 8-Bit Internal RAM

 32 Programmable I/O Lines

 Two 16-Bit Timer/Counters

 Six Interrupt Sources

 Programmable Serial Channel

 Low Power Idle and Power Down Modes

2.2 Description:

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer

with 4 Kbytes of Flash Programmable and Erasable Read Only Memory (EPROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology and
is compatible with the industry standard MCS-51 instruction set and pin out.

The on-chip Flash allows the program memory to be reprogrammed in-system

or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit
CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer
which provides a highly flexible and cost effective solution to many embedded control
applications.

The AT89C51 provides the following standard features: 4Kbytes of Flash, 128
bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition,

5
the AT89C51 is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes.

6
2.3BlockDiagram:-

7
Fig2.1: Architecture of 89C51 Microcontroller

8
2.4 Pin configuration:-

Fig2.2: Pin Diagram of AT89C51

Pin Description:-

 VCC:- Supply voltage.

 GND:- Ground.

 Port 0:- Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each
pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high-impedance inputs. Port 0 may also be configured to be the
multiplexed low order address/data bus during accesses to external program and
data memory. In this mode P0 has internal pull-ups. Port 0 also receives the code

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 bytes during Flash programming, and outputs the code bytes during program
verification. External pull-ups are required during program verification.

Port 1:- Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins
that are externally being pulled low will source current (IIL) because of the internal
pull-ups. Port 1 also receives the low-order address bytes during Flash programming
and program verification.
Port 2:- Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins
that are externally being pulled low will source current (IIL) because of the internal
pull-ups. Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @ DPTR). In this application it uses strong internal pull-ups
when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2
also receives the high-order address bits and some control signals during Flash
programming and verification.
Port 3:- Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output
buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are
pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins
that are externally being pulled low will source current (IIL) because of the pull-ups.
Port 3 also serves the functions of various special features of the AT89C51 as listed
below:

10
 Table 2.1: Special Functions of Port3

Port 3 also receives some control signals for Flash programming and
Programming verification.

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RST :- Reset input. A high on this pin for two machine cycles while the oscillator is
running resets the device.
ALE/PROG:- Address Latch Enable output pulse for latching the low byte of the
address during accesses to external memory. This pin is also the program pulse input
(PROG) during Flash programming. In normal operation ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and may be used for external timing or
clocking purposes. Note, however, that one ALE pulse is skipped during each access
to external Data Memory. If desired, ALE operation can be disabled by setting bit 0
of SFR location 8EH. With the bit set, ALE is active only during a MOVX or
MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-
disable bit has no effect if the microcontroller is in external execution mode.
PSEN:- Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during each
access to external data memory.
EA/VPP:- External Access Enable. EA must be strapped to GND in order to enable the
device to fetch code from external program memory locations starting at 0000H up
to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally
latched on reset. EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash
programming, for parts that require 12-volt VPP.
 XTAL1:- Input to the inverting oscillator amplifier and input to the internal
clock operating circuit.

XTAL2:- Output from the inverting oscillator amplifier.

Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator as shown in Figure 2.
Either a quartz crystal or ceramic resonator may be used. To drive the device from an

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external clock source, XTAL2 should be left unconnected while XTAL1 is driven as
shown in Figure 2. There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a divide-by-two flip-
flop, but minimum and maximum voltage high and low time specifications must be
observed.

Fig2.3: Crystal Oscillator Connection

Notes : C1,C2 = 30 pF + 10 pF for Crystals

= 40 pF + 10 pF for Resonators

13
 Fig2.4: External Clock Drive Configuration

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals
remain active. The mode is invoked by software. The content of the on-chip RAM and all
the special functions registers remain unchanged during this mode. The idle mode can be
terminated by any enabled interrupt or by a hardware reset. It should be noted that when
idle is terminated by a hardware reset, the device normally resumes program execution,
from where it left off, up to two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port
pin when Idle is terminated by reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external memory.

Power Down Mode

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 In the power down mode the oscillator is stopped, and the instruction that
invokes power down is the last instruction executed. The on-chip RAM and Special
Function Registers retain their values until the power down mode is terminated. The only
exit from power down is a hardware reset. Reset redefines the SFRs but does not change
the on-chip RAM. The reset should not be activated before VCC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.

Table2.2: Status Of External Pins During Idle and Power Down Mode

2.5 Special Function Registers:-

Table 2.3 contains a list of all SFRs and their addresses. All of the SFRs that are byte-
addressable are located on the first column of the diagram in figure 5.

15
Table 2.3: Special Function Registers

Contents of the SFRs just after Power-on or a Reset

Table 2.4: Contents of the SFRs just after the Power On or a Reset

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Special Function register map

17
 Fig2.5: SFR Memory map

Accumulator (0E0h)

As its name suggests, it is used to accumulate the results of large no. of

instructions. It can hold 8 bit values.

B register (0F0h)
The B register is very similar to accumulator. It may hold 8-bit value. The B
register is only used by MUL AB and DIV AB instructions. In MUL AB the higher byte
of the products gets stored in B register. In DIV AB the quotient gets stored in B with the
remainder in A.

Stack pointer (081h)

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 The stack pointer holds 8-bit value. This is used to indicate where the next value
to be removed from the stack should be taken from. When a value is to be pushed on to
the stack, the 8051 first stores the value of SP and then stores the value at the resulting
memory location. When a value is to be popped from the stack, the 8051 returns the value
from the memory location indicated by SP and then decrements the value of SP.

Data pointer (Data pointer low/high, address 82/83h)

The SFRs DPL and DPH work together to represent a 16-bit value called the data
pointer. The data pointer is used in operations regarding external RAM and some
instructions code memory. It is a 16-bit SFR and also an addressable SFR.

Program counter
The program counter is a 16 bit register, which contains the 2 byte address, which
tells the next instruction to execute to be found in memory. When the 8051 is initialized
PC starts at 0000h and is incremented each time an instruction is executes. It is not
addressable SFR.

PCON (power control, 87h)

The power control SFR is used to control the 8051’s power control modes.
Certain operation modes of the 8051 allow the 8051 to go into a type of “sleep mode”
which consumes low power.

SMOD ---- --- ---- GF1 GF0 PD IDL

TCON(Timer control, 88h)

The timer mode control SFR is used to configure and modify the way in which
the 8051’s two timers operate. This SFR controls whether each of the two timers is
running or stopped and contains a flag to indicate that each timer has overflowed.
Additionally, some non-timer related bits are located in TCON SER. These bits are used

19
to configure the way in which the external interrupt flags are activated, which are set
when an external interrupt occur.

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD(Timer Mode,89h)
The timer mode SFR is used to configure the mode of operation of each of the
two timers. Using this SR your program may configure each timer to be a 16-bit timer, or
13 bit timer, 8-bit auto reload timer, or two separate timers. Additionally you may
configure the timers to only count when an external pin is activated or to count “events”
that are indicated on an external pin.

‌ ‌

Gate C/ T M1 M0 Gate C/ T M1 M0

TIMER1 TIMER0

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T0 (Timer 0 low/ high, address 8A/ 8C h)
These two SFRs together represent timer 0. Their exact behavior depends on how
the timer is configured in the TMOD SFR; however, these timers always count up. What
is configurable is how and when they increment value.

T1 (Timer 1 low/ high, address 8B/ 8D h)

These two SFRs together represent timer 1. Their exact behavior depends on how
the timer is configured in the TMOD SFR; however, these timers always count up. What
is configurable is how and when they increment in value.

P0 (Port 0, address 80h, bit addressable)

This is port 0 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 0 is first written on P0 register. For e.g., bit 0
of port 0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

P1(Port 1, address 90h, bit addressable)

This is port 1 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 1 is first written on P1 register. For e.g., bit 0
of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

P2 (Port 2, address 0A0h, bit addressable)

This is port 2 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 2 is first written on P2 register. For e.g., bit 0
of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

21
P3 (Port 3, address 0B0h, bit addressable)
This is port 3 latch. Each bit of this SFR corresponds to one of the pins on a micro
controller. Any data to be outputted to port 3 is first written on P3 register. For e.g., bit 0
of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a
high level on the corresponding I/O pin whereas a value of 0 will bring it to low level.

IE (Interrupt Enable, 0A8h)

The interrupt enable SFR is used to enable and disable specific interrupts. The
low 7 bits of the SFR are used to enable/disable the specific interrupts, where the MSB
bit is used to enable or disable all the interrupts. Thus, if the high bit of IE 0 all interrupts
are disabled regardless of whether an individual interrupt is enabled by setting a lower
bit.

___

EA ET2 ES ET1 EX1 ET0 EX0

IP (Interrupt Priority, 0B8h)

The interrupt priority SFR is used to specify the relative priority of each interrupt.
On 8051, an interrupt may be either low or high priority. An interrupt may interrupt
interrupts. For e.g., if we configure all interrupts as low priority other than serial
interrupt. The serial interrupt always interrupts the system; even if another interrupt is
currently executing no other interrupt will be able to interrupt the serial interrupt routine
since the serial interrupt routine has the highest priority.

___ ___

PT2 PS PT1 PX1 PT0 PX0

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PSW (Program Status Word, 0D0h)
The Program Status Word is used to store a number of important bits that are set
and cleared by 8051 instructions. The PSW SFR contains the carry flag, the auxiliary
carry flag, the parity flag and the overflow flag. Additionally, it also contains the register
bank select flags, which are used to select, which of the “R” register banks currently in
use.

CY AC F0 RS1 RS0 OV ---- P

Fig2.6: Program Status Word (PSW)

Every microcontroller contains flags that may be used for testing the outcome
of an instruction's execution. For example, the carry flag may be used to test the outcome
of an 8-bit addition to see if the result is greater than 255.

Some microcontrollers use a special bit to indicate whether the content

of the accumulator is zero or not (the PIC microcontroller, for example). This flag is
usually called the zero or Z flag and conditional jump instructions that test its value can
be used to branch if the accumulator is zero or if the accumulator is not zero (if Z is set,
the accumulator contains zero, if Z is clear the accumulator contains a number other than
zero). The 8051 does not have such a bit. To test the status of the accumulator the
instructions JZ rel (jump if (A) = 0) and JNZ rel (jump if (A) <> 0) are used. The 8051
PSW is detailed below

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 Table 2.5: Program Status Word (PSW)

Bit Symbol Address Description

PSW.7 CY D7H Carry flag

PSW.6 AC D6H Auxiliary carry flag

PSW.5 F0 D5H Flag 0

PSW.4 RS1 D4H Register bank select 1

PSW.3 RS0 D3H Register bank select 0

PSW.2 OV D2H Overflow flag

PSW.1 -- D1H Reserved

PSW.0 P D0H Even parity flag

Carry Flag:
We have already made use of the carry flag, but a recap on its function is given below.

The carry flag has two functions.

• Firstly, it is used as the carry-out in 8-bit addition/subtraction. For example, if the

accumulator contains FDH and we add 3 to the contents of the accumulator (ADD
A, #3), the accumulator will then contain zero and the carry flag will be set. It is
also set if a subtraction causes a borrow into bit 7. In other words, if a number is
subtracted from another number smaller than it, the carry flag will be set. For
example, if A contains 3DH and R3 contains 4BH, the instruction SUBB A, R3
will result in the carry bit being set (4BH is greater than 3DH).
• The carry flag is also used during Boolean operations. For example, we could
AND the contents of bit 3DH with the carry flag, the result being placed in the
carry flag - ANL C, 3DH

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Parity Bit:
The parity bit is automatically set or cleared every machine cycle to ensure
even parity with the accumulator. The number of 1-bits in the accumulator plus the parity
bit is always even. In other words, if the number of 1s in the accumulator is odd then the
parity bit is set to make the overall number of bits even. If the number of 1s in the
accumulator is even then the parity bit is cleared to make the overall number of bits even.

For example, if the accumulator holds the number 05H, this is 0000 0101 in binary =>
the accumulator has an even number of 1s, therefore the parity bit is cleared. If the
accumulator holds the number F2H, this is 1111 0010 => the accumulator has an odd
number of 1s, therefore the parity bit is set to make the overall number of 1s even.

As we shall see later in the course, the parity bit is most often used for detecting errors in
transmitted data.

Overflow Flag (OV):

The overflow flag is bit 2 of the PSW. This flag is set after an addition or subtraction
operation if the result in the accumulator is outside the signed 8-bit range (-128 to
127). In other words, if the addition or subtraction of two numbers results in a
number less than -128 or greater than 127, the OV flag is set.
When signed numbers are added or subtracted, software can check this flag to see if the
result is in the range -128 to 127.

For example: 115 + 23 = 138 (73H + 17H = 8AH). If these numbers are being treated as
signed numbers then 8AH is (as a signed number) -118 in decimal. Obviously, 115 + 23
is not equal to -118. The problem lies with the fact that the correct answer (138) is too big
to be represented by an 8-bit signed number. Therefore, the OV flag is set to alert the
program that the result is out of range.

You may wonder what happens if the sum of two numbers is outside the range of an
unsigned number. For example: 200 + 60 = 260. The result is a 9-bit number and the
carry flag is set. However, the result is also greater than 127 (the 8-bit signed number

25
maximum) so you might expect the OV flag to be set also. But, if you test this in the Keil
simulator (or any 8051 simulator) you will notice OV is not set. Why?

The answer is quite simple: the equation in HEX is: C8H + 3CH - regardless of whether
we are dealing with signed or unsigned numbers, 3CH is equal to 60 in decimal.
However, C8H as an unsigned number is 200 in decimal, but as a signed number is -56 in
decimal. When deciding the value of the OV flag, only the case of signed numbers is
taken into account. So, this equates to -56 + 60 = 4. If you run this code in the simulator
you will see that the accumulator contains 4, the carry is set to indicate that, if this is
unsigned arithmetic, the answer is greater than 255, but OV is clear because if this is
signed arithmetic the answer is in the range -128 to 127.

The largest number we could get from signed addition is 127 + 127 = 254. In this case
OV is set because the answer is outside the 8-bit signed number range. Therefore, the
only way the carry can be set is through unsigned arithmetic, and in that case OV is not
set.

 Auxiliary Carry Flag (AC): The auxiliary carry flag is set or cleared after an add
instruction (ADD A, operand or ADDC A, operand) only. There are two
conditions that result in AC being set.

• If the lower four bits of the accumulator (the lower nibble) are in the range AH to
FH.
• If a carry was generated out of bit 3 into bit 4 of the accumulator.

This flag may be tested after an addition to see if the value in the accumulator is outside
the BCD range. If it is, the instruction DA A (decimal adjust A) can be used to change the
HEX code in A to BCD.

26
SBUF (Serial Buffer, 99h)
SBUF is used to hold data in serial communication. It is physically two registers.
One is writing only and is used to hold data to be transmitted out of 8051 via TXD. The
other is read only and holds received data from external sources via RXD. Both mutually
exclusive registers use address 99h.S

2.6 Memory Organization:-

Program Memory
The AT89C Microcontroller has separate address spaces for program
memory and data memory. The program memory can be up to 64K bytes long. The lower
addresses may reside on-chip. Figure 1 shows a map of the AT89C51 program memory.
The AT89C1051/2051 do not have off-board memory expansion.

Fig2.7: AT89C51 Program Memory

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Data Memory
The AT89C can directly address up to 64K bytes of data memory external to the chip.
The MOVX instruction accesses the external data memory. The AT89C51 has 128 bytes
of on-chip RAM plus a number of Special Function Registers (SFRs). The lower 128
bytes of RAM can be accessed either by direct addressing (MOV data address) or by
indirect addressing (MOV @Ri).Figure 3 shows the AT89C51 data memory
organization.

Fig2.8: AT89C51 Data Memory

Indirect Address Area

In Figure 3b, the SFRs and the indirect address RAM have the same addresses (80H
through 0FFH). Nevertheless, they are two separate areas and are accessed in two
different ways. For example, the following instruction writes 0AAH to Port0, which is
one of the SFRs.
MOV 80H, # 0AAH
The following instruction writes 0BBH in location 80H of the data RAM.
MOVR0, # 80H
MOV@ R0, # 0BBH

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Thus, after executing both of these instructions, Port 0 contains 0AAH, and location 80H
of the RAM contains 0BBH.The stack operations are examples of indirect addressing, so
the upper 128 bytes of data RAM are available as stack space in devices that implement
256 bytes of internal RAM.

Direct and Indirect Address Area

The 128 bytes of RAM that can be accessed by both direct and indirect addressing can be
divided into 3 segments as described in this section and as shown in Figure 4.
1. Register Banks 0-3: Locations 0 through 1FH (32bytes). Reset default is to register
bank 0. To use the other register banks, the user must select them in the software. Each
register bank contains eight 1-byte registers, 0 through 7. Reset initializes the Stack
Pointer to location 07H. The Stack Pointer is then incremented once to start from location
08H, which is the first register (R0) of the second register bank. Thus, in order to use
more than one register bank, the SP should be initialized to a different location of the
RAM that is not used for data storage (that is, a higher part of the RAM).
2. Bit Addressable Area: 16 bytes have been assigned for this segment, 20H through
2FH. Each of the 128 bits of this segment can be directly addressed (0 through 7FH).
These bits can be referred to in two ways. One way is to refer to their addresses, that is, 0
to 7FH. The other way is with reference to bytes 20H to 2FH. Thus, bits 0 through 7 can
also be referred to as bits 20.0 through 20.7, and bits 8 through FH are the same as 21.0
through 21.7, and so on. Each of the 16 bytes in this segment can also be addressed as a
byte.
3. Scratch Pad Area: Bytes 30H through 7FH are available to the user as data RAM.
However, if the stack pointer has been initialized to this area, enough bytes should be left
aside to prevent SP data destruction.

29
Fig2.9: Bytes of Directly and Indirectly Addressable RAM

30
CHAPTER 3

ENCODER AND DECODER

3.1 HT640 ENCODER:

General Description
The HT640 encoder is a CMOS LSI for remote control system applications. It is capable
of encoding 18 bits of information which consists of 10 address bits and 8 data bits. Each
address/data input is externally trinary programmable if bonded out. It is otherwise set
floating internally. The programmable address/data is transmitted together with the
header bits via an RF or an infrared transmission medium upon receipt of a trigger signal.

Features
 Operating voltage: 2.4V~12V
 Low power and high noise immunity CMOS technology
 Low standby current
 Three words transmission
 Built-in oscillator needs only 5% resistor
 Easy interface with an RF or infrared transmission media
 Minimal external components

Applications
 Burglar alarm system
 Smoke and fire alarm system
 Garage door controllers
 Car door controllers
 Car alarm system
 Security system
 Cordless telephones

31
  Other remote control systems

Fig3.1: Pin Diagram of HT640 Encoder

Table 3.1: Pin Description of HT640

Functional Description
Operation
The HT640 encoder begins a three-word transmission cycle upon receipt of a
transmission enable

32
This cycle will repeat itself as long as the transmission enable (TE) is held high. Once the
transmission enable falls low, the encoder output completes its final cycle and then stops
as shown below.

Information word
An information word consists of 4 periods as shown:

Fig3.2: Flow Chart of Encoder

33
3.2 HT648L DECODER:-

General Description
The HT648L decoder is a CMOS LSIs for remote control system
applications. It is paired with the HT640 encoders. For proper operation a pair of
encoder/decoder pair with the same number of address and data format should be
selected. The HT648L decoder receives serial address and data from that series of
encoders that are transmitted by a carrier using an RF or an IR transmission medium. It
then compares the serial input data twice continuously with its local address. If no errors
or unmatched codes are encountered, the input data codes are decoded and then
transferred to the output pins. The VT pin also goes high to indicate a valid transmission.
The HT648L is capable of decoding 18 bits of information that consists of 10 bits of
address and 8 bits of data.

Features
 Operating voltage: 2.4V~12V
 Low power and high noise immunity CMOS technology
 Low standby current
 Capable of decoding 18 bits of information
 Pairs with HOLTEK’s 318 series of encoders
 8~18 address pins
 0~8 data pins
 Trinary address setting
 Two times of receiving check
 Built-in oscillator needs only a 5% resistor
 Valid transmission indictor
 Easily interface with an RF or an infrared transmission medium

34
  Minimal external components

Applications
 Burglar alarm system
 Smoke and fire alarm system
 Garage door controllers
 Car door controllers
 Car alarm system
 Security system
 Cordless telephones
 Other remote control systems
Pin diagram:-

Fig3.3: Pin Diagram of HT648L Decoder

Pin description
Table 3.2: Pin Description of HT648L

35
Functional Description

Operation
The HT648L decoder is paired with HT640 encoder. The decoder receives data
transmitted by the encoder and interprets the first 10 bits of the code period as address
and the last 8 bits as data. A signal on the DIN pin then activates the oscillator which in
turns decodes the incoming address and data. The decoder will check the received
address twice continuously. If all the received address codes match the contents of the
decoder’s local address, the 8 bits of data are decoded to activate the output pins, and the
VT pin is set high to indicate a valid transmission. That will last until the address code is
incorrect or no signal has been received. The output of the VT pin is high only when the
transmission is valid. Otherwise it is low always.

Decoder timing

36
Fig 3.4: Flow Chart of Decoder

37
CHAPTER 4
RF MODULE

4.1 ST-TX01-ASK Transmitter:

General Description:

This transmitter works based up on the ASK modulation. Amplitude-shift keying (ASK)
is a form of modulation that represents digital data as variations in the amplitude of a
carrier wave. The amplitude of an analog carrier signal varies in accordance with the bit
stream (modulating signal), keeping frequency and phase constant. The level of
amplitude can be used to represent binary logic 0s and 1s. We can think of a carrier signal
as an ON or OFF switch. In the modulated signal, logic 0 is represented by the absence of
a carrier, thus giving OFF/ON keying operation and hence the name given.

The ST-TX01-ASK is an ASK Hybrid transmitter module. ST-TX01-ASK is designed by

the Saw Resonator, with an effective low cost, small size, and simple-to-use for
Frequency

Range: 315 / 433.92 MHZ.

Supply Voltage: 3~12V.
Output Power: 4~16dBm
Circuit Shape: Saw

Fig4.1: Image and Block Diagram of ST-TX01-ASK Transmitter

38
RF ASK Transmitter pin numbers
o Pin1. Antenna
o Pin2. Vcc
o Pin3. Data
o Pin4. GND

Applications
 Wireless security systems
 Car Alarm systems
 Remote controls.
 Sensor reporting
 Automation systems

4.2 ST-RX04-ASK Receiver :-

General Description:

The ST- RX04-ASK is an ASK super heterodyne receiver module with PLL synthesizer
and crystal oscillator. The circuit shape is PLL.

Receiver Frequency: 315 / 433.92 MHZ

Operation Voltage: 5V
IF Frequency: 500k
Typical sensitivity: -105dBm
Supply Current: 2.3mA

Features

 Low power consumption.

 Easy for application.

39
  On-Chip VCO with integrated PLL using crystal oscillator reference.
 Integrated IF and data filters.
 Operation temperature range: -400C ~ -800C
 Operation voltage: 5 Volts.
 Available frequency at: 315/434 MHz

The RX – ASK is an ASK Hybrid receiver module. It is a effective low cost solution for
using 433 MHz. The TX-ASK is an ASK hybrid transmitter module. TX-ASK is
designed by the saw resonator, with an effective low cost, small size and simple to use
for designing.

Fig 4.2: Image and Block Diagram of ST-RX04-ASK Receiver

Applications:

 Car security system

 Wireless security systems
 Sensor reporting
 Automation system
 Remote Keyless entry

40
CHAPTER 5
KEY PAD

Internally, the structure of the HEX keypad is very simple.

Wires run in vertical columns (we call them C1 to C4) and in horizontal
rows (called R1 to R4). These 8 wires are available externally, and will
be connected to Port0. Each key on the keypad is essentially a switch
that connects a row wire to a column wire. When a key is pressed, it
makes an electrical connection between the row and column. The
internal structure of the hex keypad is shown in Figure

.
Fig5.1: Keypad connection with microcontroller
Row 1- Row4 are connected to P0.4 to P0.7 respectively and Column1-
Column4 are connected to P0.3 to P0.0.

41
Debouncing
Unfortunately, reality now rears its ugly head. While the above process
is correct, we have to deal with the fact that the keys are not ideal
switches. Thus, while we may represent the keys as an ideal electrical
switch connecting a row wire and column wire (as shown in Figure 3),
the reality is that the switch is a mechanical device subject to the laws
of physics.
Thus, when the switch is closed, as contact is made, the connector will
“bounce” open and closed for about 10 milliseconds. (You can view it
much like a door that rattles in its frame after it has been slammed –
the rebound of the physical force closing it causes some bouncing.)
This means that when we try to read the hex keypad, if we read in that
10 millisecond “ bounce” window, we may be reading at a time when
the switch is open, and thus not get the correct value. The solution to
this is to debounce the input.
Debouncing is achieved by simply waiting for the inputs to stabilize
before taking a reading. Thus, after detecting a key press (whether via
interrupt or polling), your program should wait for approximately 10
milliseconds before reading the row and column wires as described in
the preceding section. A delay of 10 milliseconds can be generated by
executing a short loop program n times, depending on the system
clock speed.

42
CHAPTER 6

LCD DISPLAY
The LCD unit receives character codes (8 bits per character) from a
microprocessor or microcomputer, latches the codes to its display data RAM (80-byte
DD RAM for storing 80 characters), transforms each character code into a 5 *7 dot-
matrix character pattern, and displays the characters on its LCD screen.
To display a character, positional data is sent via the data bus from the microprocessor to
the LCD unit, where it is written into the instruction register. A character code is then
sent and written into the data register. The LCD unit can either increment or decrement
the display position automatically after each character entry, so that only successive
characters codes need to be entered to display a continuous character string.

Features:-

 Interface with either 4-bit or 8-bit microprocessor.

 Display data RAM
 Character generator ROM
 160 different 5 ´ 7 dot-matrix character patterns.
 Character generator RAM
 8 different user programmed 5 ´ 7 dot-matrix patterns.
 Display data RAM and character generator RAM may be accessed by the
microprocessor.
 Numerous instructions
 Clear Display, Cursor Home, Display ON/OFF, Cursor ON/OFF, Blink Character,
Cursor Shift.
43
  Built-in reset circuit is triggered at power ON.
 Built-in oscillator.

6.1 Pin Diagram:-

Fig6.1: Pin Diagram of LCD JHD162A

44
Table 6.1: Pin description of LCD

Pin description for LCD:-

VSS, Vdd and V0:-

While VSS, and Vdd provide +5V and ground, respectively, V0 is used for controlling LCD
contrast.

45
RS, register select:-
There are two very important registers inside the LCD. The RS pin is used to selection as
follows. If RS=0, the instruction command code register is selected, allowing the user to
send a command such as clear display, cursor at home, etc. if RS=1 the data register is
selected, allowing the user to send data to be displayed on the LCD

R/W read/write:-
R/W input allows the user to write information from it. r/w=1 when reading; r/w=0 when
writing.

E, Enable:-
The enable pin is used by the LCD to latch information presented to its data
pins. When data is supplied to data pins, a high-to-low pulse must be applied to this pin
in order for the LCD to latch in data present at the data pins. This pulse must be a
minimum of 450ns wide.

D0-D7:-
The 8-bit data pins, D0-D7, are used to send to information to the LCD or
read the contains of the LCD’s internal registers. To display letters and numbers, we send
ASCII codes for the letters A-Z, a-z and numbers 0-9 to these pins while making RS=1.
There also instructions command codes that can be send to the LCD to clear display or
force the cursor to the home position or blink the cursor. We also use RS=0 to check the
busy flag bit to see if the LCD is ready to receive the information. The busy flag D7 and
can be read when R/W=1 and RS=0, as follows if R/W=1, RS=0.when D7=1, The LCD
is busy taking care of internal operation and will not accept any new information.
WhenD7=0, the LCD is ready to receive new information.

46
CHAPTER 7

KEIL SOFTWARE

Introduction to Micro vision Keil (IDE)

Keil is a cross compiler. So first we have to understand the concept of compilers and
cross compilers. After then we shall learn how to work with keil.

Concept of compiler: -

Compilers are programs used to convert a High Level Language to object code.
Desktop compilers produce an output object code for the underlying microprocessor,
but not for other microprocessors. I.E the programs written in one of the HLL like ‘C’
will compile the code to run on the system for a particular processor like x86
(underlying microprocessor in the computer). For example compilers for Dos
platform is different from the Compilers for Unix platform

So if one wants to define a compiler then compiler is a program that translates source
code into object code. The compiler derives its name from the way it works, looking
at the entire piece of source code and collecting and reorganizing the instruction. See
there is a bit little difference between compiler and an interpreter. Interpreter just
interprets whole program at a time while compiler analyzes and execute each line of
source code in succession, without looking at the entire program.

The advantage of interpreters is that they can execute a program immediately.

Secondly programs produced by compilers run much faster than the same programs
executed by an interpreter. However compilers require some time before an
executable program emerges. Now as compilers translate source code into object
code, which is unique for each type of computer, many compilers are available for the
same language.

Concept of cross compiler: -

47
A cross compiler is similar to the compilers but we write a program for the target
processor (like 8051 and its derivatives) on the host processors (like computer of x86)

It means being in one environment you are writing a code for another environment is
called cross development. And the compiler used for cross development is called
cross compiler

So the definition of cross compiler is a compiler that runs on one computer but
produces object code for a different type of computer. Cross compilers are used to
generate software that can run on computers with a new architecture or on special-
purpose devices that cannot host their own compilers. Cross compilers are very
popular for embedded development, where the target probably couldn't run a
compiler. Typically an embedded platform has restricted RAM, no hard disk, and
limited I/O capability. Code can be edited and compiled on a fast host machine (such
as a PC or Unix workstation) and the resulting executable code can then be
downloaded to the target to be tested. Cross compilers are beneficial whenever the
host machine has more resources (memory, disk, I/O etc) than the target. Keil C
Compiler is one such compiler that supports a huge number of host and target
combinations. It supports as a target to 8 bit microcontrollers like Atmel and
Motorola etc.

Why do we need cross compiler?

There are several advantages of using cross compiler. Some of them are described as
follows

• By using this compilers not only can development of complex embedded

systems be completed in a fraction of the time, but reliability is improved, and
maintenance is easy.

• Knowledge of the processor instruction set is not required.

• A rudimentary knowledge of the 8051’s memory architecture is desirable but

not necessary.

48
 • Register allocation and addressing mode details are managed by the compiler.

• The ability to combine variable selection with specific operations improves

program readability.

• Keywords and operational functions that more nearly resemble the human
thought process can be used.

• Program development and debugging times are dramatically reduced when

compared to assembly language programming.

• The library files that are supplied provide many standard routines (such as
formatted output, data conversions, and floating-point arithmetic) that may be
incorporated into your application.

• Existing routine can be reused in new programs by utilizing the modular

programming techniques available with C.

• The C language is very portable and very popular. C compilers are available
for almost all target systems. Existing software investments can be quickly and
easily converted from or adapted to other processors or environments.

Now after going through the concept of compiler and cross compilers lets we start with
Keil C cross compiler.

Keil C cross compiler: -

Keil is a German based Software development company. It provides several development

tools like

• IDE (Integrated Development environment)

• Project Manager

• Simulator

• Debugger

49
 • C Cross Compiler, Cross Assembler, Locator/Linker

Keil Software provides you with software development tools for the ARM
microcontrollers. With these tools, you can generate embedded applications for the
multitude of ARM derivatives. Keil provides following tools for ARM development

1. ARM Optimizing C Cross Compiler,

2. Macro Assembler,

3. ARM Utilities (linker, object file converter, library manager),

4. Source-Level Debugger/Simulator,

5. µVision for Windows Integrated Development Environment.

The keil ARM tool kit includes three main tools, assembler, compiler and linker.

An assembler is used to assemble your ARM assembly program

A compiler is used to compile your C source code into an object file

A linker is used to create an absolute object module suitable for your in-circuit emulator.

8051 project development cycle: -

These are the steps to develop ARM project using keil

1. Create source files in C or assembly.

2. Compile or assemble source files.
3. Correct errors in source files.
4. Link object files from compiler and assembler.
5. Test linked application.

50
CHAPTER 8

CIRCUIT DIAGRAM

51
8.1 TRANSMITTER SECTION:-

52
Fig8.1: Transmitter section circuit diagram

53
8.2 RECEIVER SECTION:-

54
 Fig8.2: Receiver section circuit diagram

CHAPTER 9

SOURCE CODING

9.1 TRANSMITTER SECTION:

org 00h

te equ p3.0

clr te

main: acall delay_10ms

wait: mov p0,#0fh

mov a,p0

anl a,#0fh

cjne a,#0fh,next

sjmp wait

next: acall delay_10ms

55
 mov p0,#0efh

mov a,p0

anl a,#0fh

cjne a,#0fh,row1

mov p0,#0dfh

mov a,p0

anl a,#0fh

cjne a,#0fh,row2

mov p0,#0bfh

mov a,p0

anl a,#0fh

cjne a,#0fh,row3

mov p0,#7fh

mov a,p0

anl a,#0fh

cjne a,#0fh,row4

row1: mov DPTR,#table1

sjmp find

row2: mov DPTR,#table2

sjmp find

row3: mov DPTR,#table3

56
 sjmp find

row4: mov DPTR,#table4

sjmp find

find: rrc a

jnc match

inc DPTR

sjmp find

match: clr a

movc a,@a+DPTR

add a,#02h

mov p1,a

setb te

acall delay_20ms

clr te

ljmp main

delay_20ms:

mov r0,#150

again: mov r1,#100

djnz r1,$

djnz r0,again

ret

57
delay_10ms:

mov r2,#10h

again1:mov r3,#10h

djnz r3,$

djnz r2,again1

ret

table1: db "A","3","2","1"

table2: db "B","6","5","4"

table3: db "C","9","8","7"

table4: db "D","F","0","E"

end

9.2 RECEIVER SECTION:-

org 00h

rs equ p2.7

rw equ p2.6

en equ p2.5

lcd_port equ p0

vt equ p3.0

58
 acall lcd_int

mov DPTR,#messg

/*mov a,#'A'

acall data_byte

jmp $*/

back: clr a

movc a,@a+DPTR

acall data_byte

acall delay_40ms

inc DPTR

jnz back

check: jb vt,disp

sjmp check

disp: mov a,#01h

acall command_byte

acall delay_40ms

mov a,#87h

acall command_byte

acall delay_40ms

mov a,p1

subb a,#02h

59
 acall data_byte

acall delay_40ms

sjmp check

lcd_int: mov a,#38h

acall command_byte

acall delay_40ms

mov a,#06h

acall command_byte

acall delay_40ms

mov a,#0ch

acall command_byte

acall delay_40ms

mov a,#01h

acall command_byte

acall delay_40ms

ret

command_byte: mov lcd_port,a

clr rs

clr rw

setb en

nop

60
 nop

nop

nop

clr en

ret

data_byte: mov lcd_port,a

setb rs

clr rw

setb en

nop

nop

nop

nop

clr en

ret

delay_40ms: mov r0,#200

back1: mov r1, #200

djnz r1,$

djnz r0,back1

ret

messg: db " MGIT College ",0

61
 end

CHAPTER 10

CONCLUSION

The project “WIRELESS SPY ROBOT WITH OBJECT

DETECTION” has been successfully designed and tested. Integrating features of all the
hardware components used have developed it. Presence of every module has been
reasoned out and placed carefully thus contributing to the best working of the unit.
Secondly, using highly advanced IC’s and with the help of growing technology the
project has been successfully implemented.

62
 BIBILIOGRAPHY

TEXT BOOKS:

The 8051 Microcontroller and Embedded Systems ,2000

By Muhammad Ali Mazidi and Janice Gillispie Mazidi

Fundamentals of Embedded Software

By Daniel W. Lewis

The 8051/8052 Microcontroller: Architecture, Assembly Language, And

Hardware Interfacing
By Craig Steiner

WEB SITES:

1. www.alldatasheets.com

2. www.8051 projects.info/projects.asp

3. www.wikipedia.org

4. http://www.wdell.com/support/encryption.html

63
64