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Demodulator
CXD2854ER
Description
The CXD2854ER demodulator offers class-leading performance, optimized BOM requiring no external memory and low
processor overhead.
Features
◆ Features DVB-T2
◆ Complies with DTG D-BOOK 7.0 V2.0, NorDig-Unified Test Specification ver2.2.1 and targeting upcoming Digital
Europe Ebook requirements
◆ Supports 5 MHz, 6 MHz, 7 MHz, 8 MHz and 1.7 MHz BW
◆ Supports all DVB-T2 modes, including
Single and multiple-PLPs
T2-Lite profile
SISO and MISO transmission
◆ Simple API
Fully-automatic acquisition
Fully-automatic L1-signalling decoding
Automatic guard-interval detection
Automatically-calculated constant-rate TS output (using L1 signalling and ISSY)
◆ Frequency offset detection range up to +/-600 kHz allows acquisition and performance optimization via tuner
frequency offset compensation
◆ Stream processor for automatic common-PLP and data-PLP combination
◆ Null-packet insertion
◆ Improved performance for multipath channel (outside the guard interval)
Note)
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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CXD2854ER
◆ Features DVB-T
◆ Complies with all European standards for static and portable equipment including NorDig-Unified Test
Specification ver2.2.1 DTG D-BOOK 7.0 V2.0, IEC 62216 and targeting upcoming Digital Europe Ebook
requirements
◆ Smart Auto Acquisition controller with fast 2k/8k acquisition, low processor overhead and re-acquisition mode
◆ Frequency offset detection range up to +/-600 kHz allows acquisition and performance optimization via tuner
frequency offset compensation
◆ Advanced channel corrector for low multipath loss and enhanced Doppler performance
◆ Improved CNR performance
◆ Features DVB-C2
◆ Demodulation:
16, 64, 256, 1024, 4096 QAM
2/3, 3/4, 4/5, 5/6, 8/9, 9/10 Code Rates
1/64 and 1/128 Guard Intervals
◆ 8 MHz and 6 MHz channel bandwidths
◆ Data Slices
Types 1 & 2 supported
Data Slice width up to 7.61 MHz
◆ Stream processor for automatic common-PLP and data-PLP combination
◆ FEC Header Type
Robust mode
High Efficiency mode
◆ Simple API
Fully-automatic acquisition
Fully-automatic L1-signalling decoding
Automatic spectrum inversion
Automatic guard-interval detection
Automatically-calculated constant-rate TS output
◆ Notch Support
Narrowband and broadband notches
Reception of narrow channels down to 2 MHz between broadband notches
◆ Time interleaving modes 4, 8 symbols and 'best fit'
◆ Features DVB-C
◆ Complies with NorDig-Unified Test specification Ver2.2.1
◆ Wide symbol range, 1.8 to 7.2 Msym/s
◆ Integrated matched filter 0.15 roll-off factor
◆ Frequency offset detection range up to ±500 kHz allows acquisition and performance optimization via tuner
frequency offset compensation
◆ Excellent equalization for cancellation of reflections at larger delays
◆ Improved performance against large continuous wave interference
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CXD2854ER
◆ Features DVB-S2
◆ Complies with NorDig-Unified Test Specification ver2.2.1
◆ Modulation: 8PSK/QPSK
◆ Symbol rate
8PSK: 333 Ksym/s to 45 Msym/s
QPSK: 333 Ksym/s to 45 Msym/s
◆ Code rate
8PSK: 3/5, 2/3, 3/4, 5/6, 8/9, 9/10
QPSK: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
◆ High speed synchronization
◆ Fast and accurate channel scan
◆ Features DVB-S
◆ Complies with NorDig-Unified Test Specification ver2.2.1
◆ Modulation: QPSK
◆ Symbol rate: 333 Ksym/s to 45 Msym/s
◆ Code rate: 1/2, 2/3, 3/4, 5/6, 7/8
◆ High speed synchronization
◆ Fast and accurate channel scan
◆ Features ISDB-T/SBTVD-T
◆ Conforms to ARIB STD-B31
◆ 6 MHz,7 MHz and 8 MHz BW support
◆ Excellent phase noise resistance
◆ Excellent multipath equalization performance
◆ Automatic detection of mode/guard interval lengths
◆ EWS (Emergency Warning System) flag output
◆ Read function of AC Carrier information corresponding to the earthquake broadcasting (ARIB STD-B31 v1.8)
◆ Enhanced in the following areas
Improved CNR performance
Improved performance for time varying channel
◆ Features ISDB-S
◆ Conforms to ARIB STD-B20
◆ Supports Zero-IF tuner
◆ Tolerates large phase noise
◆ Excellent multipath equalization performance
◆ Tolerates large IQ amplitude and phase distortion
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CXD2854ER
◆ General Features
◆ Single, 24MHz crystal with tolerance up to ±100 ppm. (Targeting support for crystal sharing with Sony SiTuner or
other Sony Analogue/Digital demodulator)
◆ High performance ADC
◆ RF power level monitor ADC
◆ Low IF and Standard-IF (36, 44, 57MHz) mode input
◆ Fast 400 kHz I2C compatible bus interface
2
◆ Quiet I C interface for dedicated tuner control
◆ Programmable I2C addresses allowing up to four devices to be connected in a single system
◆ Automatic IF AGC and optional programmable RF AGC/GPIO functions
◆ Configurable parallel and serial MPEG-2 TS outputs with smoothing buffer
◆ Simple API
◆ Conforms to DiSEqC 1.x, DiSEqC 2.x and Single Cable Distribution (CENELEC/BS EN 50494) standards with
external components.
◆ 3.3 V, 1.1 V supplies
◆ Temperature range -20 °C to +85 °C
◆ 48 pin VQFN 7 mm x 7 mm package
◆ Supplied with full reference design, including software driver, printed circuit board schematic/layouts and
documentation
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CXD2854ER
Applications
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CXD2854ER
Contents
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CXD2854ER
1. Block Diagram
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CXD2854ER
2. Pin Layout
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CXD2854ER
3. Pin Description
5 V tolerant /
DVDD
IE
Input Enable (default:
GPIO0 1 IO General purpose I/O 1 disable)
VSS
5 V tolerant /
DVDD
IE
Input Enable (default:
GPIO2 General purpose I/O
2 IO 2 disable)
(TSERR) TS error flag
Selectable output current for
VSS
TSERR
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
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CXD2854ER
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
5 V tolerant /
DVDD
VSS
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CXD2854ER
5 V tolerant /
DVDD
DVDD
5 V tolerant /
Schmitt trigger input
2
SCL 20 I I C clock 20
VSS
DVDD
5 V tolerant /
Schmitt trigger input /
2
SDA 21 IO I C data 21 Open-drain output
VSS
5 V tolerant
DVDD
VSS
DVDD
5 V tolerant /
VSS
DVDD
5 V tolerant /
Internal pull-down
I2C slave address
, SLVADR0 25 I 25
selection
VSS
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CXD2854ER
5 V tolerant /
DVDD
VSS
DVDD
5 V tolerant /
Schmitt trigger input
RST_X 29 I Hardware reset 29
VSS
DVDD
5 V tolerant /
2
Internal pull-up
I C slave address
SLVADR3 30 I 30
selection
VSS
AVDD
Internal regulated voltage
31
I-ch analog input for VINCMEN
SIAIN 31 AI
satellite tuner
AVSS
AVDD
Internal regulated voltage
32
Q-ch analog input for VINCMEN
SQAIN 32 AI
satellite tuner
AVSS
XVDD
Leave open when external
Internal regulated voltage
XTALO 34 AO Crystal oscillator output
clock input to XTALI
34
External clock input pin
35
XTALI 35 AI Crystal oscillator input
XVSS
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CXD2854ER
AVDD
Differential input
Internal regulated voltage
37
IF(+) analog input for VINCMEN
TAINP 37 AI
terrestrial tuner
38
AVSS
DVDD
5 V tolerant /
Test mode setting Internal pull-down
TESTMODE 40 I 0 Normal mode 40 This pin must be connected
AVDD
AVSS
DVDD
5 V tolerant /
Schmitt trigger input /
TTUSDA 45 IO Tuner I2C data 45 Open-drain output
VSS
DVDD
5 V tolerant /
Open-drain output
2
TTUSCL 46 O Tuner I C clock 46
VSS
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CXD2854ER
5 V tolerant /
DVDD
IE
Input Enable (default:
GPIO1 47 IO General purpose I/O 47 disable)
VSS
DVDD
NOTE1) Input voltage up to 3.6 V is acceptable on 5 V tolerant inputs even when the CXD2854ER power is off.
I/O Description
I Digital Input
O Digital Output
AI Analog Input
AO Analog Output
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CXD2854ER
NOTE1) Absolute maximum rating values must not be exceeded, even momentarily, for any item. In addition, even when
the absolute maximum ratings and operating range are not exceeded, use of this product under operating
conditions (operating temperature, current, voltage, etc.) that apply a continuously high load (high temperature
with high current and high voltage applied, large temperature changes, etc.) may significantly degrade reliability.
NOTE2) VI5 and VO5 are the 5 V tolerant I/O ratings.
NOTE3) 5 V tolerant inputs are only 5 V tolerant while the CXD2854ER power is applied. If no power is applied to
CXD2854ER there is no protection to 5 V levels and the CXD2854ER may be permanently damaged. It is
important to observe the conditions for 5 V protection when sequencing power supplies in the application.
NOTE4) VIA is the analog input rating. The applicable pins are TAINP, TAINM, SIAIN, SQAIN and RFAIN.
NOTE5) VIX is the analog input rating. The applicable pin is XTALI.
NOTE6) VOX is the analog output rating. The applicable pin is XTALO.
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CXD2854ER
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CXD2854ER
6. DC Electrical Characteristics
Digital I/Os
Corresponding I/Os are: GPIO[2:0], TSCLK, TSSYNC, TSVALID, TSDATA[7:0], RST_X, SLVADR0, SLVADR3, TTUSCL, TTUSDA,
GPIO[2:0]
Input High Voltage VIH5 - 2.0 - 5.5 V RST_X
SLVADR0
SLVADR3
TTUSDA
Input Low Voltage VIL - -0.3 - 0.8 V DSQIN
TESTMODE
TIFAGC
VOH2 IOH = -2 mA 2.4 - - V SAGC
DSQOUT
GPIO[2:0]
TSCLK
Output High Voltage VOH8 IOH = -8 mA 2.4 - - V TSSYNC
TSVALID
(*1) TSDATA[7:0]
GPIO2
TSCLK
VOH10 IOH = -10 mA 2.4 - - V TSSYNC
TSVALID
TSDATA[7:0]
TIFAGC
VOL2 IOL = +2 mA - - 0.4 V SAGC
DSQOUT
TTUSCL
VOL4 IOL = +4 mA - - 0.4 V
TTUSDA
GPIO[2:0]
Output Low Voltage TSCLK
VOL8 IOL = +8 mA - - 0.4 V TSSYNC
(*1) TSVALID
TSDATA[7:0]
GPIO2
TSCLK
VOL10 IOL = +10 mA - - 0.4 V TSSYNC
TSVALID
TSDATA[7:0]
RST_X
VI = 5.5 V or 0 SLVADR0
Input Current IILH5 - - ±10 μA SLVADR3
V DSQIN
TESTMODE
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CXD2854ER
Differential
IF Input Full Scale TAINP
VFS;IF input - - 1.4 Vp-p
Range TAINM
TAINP - TAINM
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CXD2854ER
Clock Input
Corresponding I/Os are: XTALI, XTALO
XTALO Δof Io = -2 mA
gm;XO 9.6 16.8 29.3 mS XTALO
Transconductance and Io=0 mA
RF Level Monitor
Corresponding I/Os are: RFAIN
RFAIN Zero-scale
VZST;RF - -0.015 - 0.015 V RFAIN
Transition Voltage
NOTE1) Output current of GPIO2, TSCLK, TSSYNC, TSVALID, TSDATA[7:0] can be selected by the register settings.
NOTE2) This range is specified to ensure correct propagation of an external clock through the internal logic. It does not
apply when a crystal is connected between XTALO and XTALI.
NOTE3) I2C input low voltage level conforms to the I2C bus specification, which is VBUS;I2C * 0.3, when VBUS;I2C is less than
or equal to 3.6 V.
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CXD2854ER
ICVDD;DVB-C - 50 248 mA
IXVDD;DVB-C - 8 9 mA
IXVDD;DVB-S2 - 8 9 mA
IDVDD;DVB-S (*2) - 9 13 mA
DVB-S QPSK, CR = 7/8, SR = 45 Msym/s
IAVDD;DVB-S - 63 70 mA
IXVDD;DVB-S - 8 9 mA
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CXD2854ER
IXVDD;ISDB-T - 8 9 mA
ICVDD;ISDB-T - 76 239 mA
IXVDD;ISDB-T - 8 9 mA
Standby Current
ICVDD;Sleep - 20 64 mA
When in Sleep mode (*3)
IDVDD;Sleep - 0.2 0.5 mA
Sleep ADC bias is active
IAVDD;Sleep - 9 12 mA
(*1)
IXVDD;Sleep - 8 9 mA
ICVDD;Shutdown - 5 45 mA
When in Shutdown mode (*3)
IDVDD;Shutdown - 0.2 0.5 mA
Shutdown ADC bias is active
IAVDD;Shutdown - 6 9 mA
(*1)
IXVDD;Shutdown - 0.001 0.002 mA
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CXD2854ER
7. AC Electrical Characteristics
SCL Clock
fSCL - - - 400 kHz
Frequency
Pulse Width of
tSP;I2C - - - 50 ns
Spikes Allowed
2
I C Output Load
CLD;I2C - - - 400 pF SDA
Capacitance
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CXD2854ER
TS Output
Corresponding I/Os are: TSCLK, TSSYNC, TSVALID, TSDATA[7:0], GPIO2(TSERR) (*4)
TS Output Load
CLD;TS - - - 15 pF All pins
Capacitance
GPIO Interface
Corresponding I/Os are: GPIO[2:0]
GPIO Input
CIN;GPIO - - - 5 pF All pins
Capacitance
DiSEqC Interface
Corresponding I/Os are: DSQIN, DSQOUT
DiSEqC Input
CIN;DSQ - - - 5 pF DSQIN
Capacitance
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CXD2854ER
Other I/Os
Corresponding I/Os are: RST_X, SLVADR0, SLVADR3, TESTMODE
Misc Input
CIN;MISC - - - 5 pF All pins
Cpacitance
IF Input Impedance
ZdiffNOR;IF Differential 3.4 - 7.0 kΩ
in Normal Operation
Differential All pins
IF Input Impedance
ZdiffSTB;IF ADC_VINCMEN 8.0 - 12.0 kΩ
in Standby
=1
IQ Input Impedance
ZINNOR;IQ - 2.5 - 4.5 kΩ
in Normal Operation
Single-end All pins
IQ Input Impedance
ZINSTB;IQ ADC_VINCMEN 3.2 - 100 kΩ
in Standby
=1
Clock Input
Corresponding I/Os are: XTALI, XTALO
XTALI Frequency
Ftol;XI (*3) - - ±100 ppm
Tolerance
XTALI
XTALI Input
ZIN;XI - 160 - 245 kΩ
Impedance
XTALI Input
CIN;XI - 3 - 5 pF
Capacitance
XTALO Output
COUT;XO - 2 - 4 pF XTALO
Capacitance
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CXD2854ER
RFAIN Input
FIN;RF - 0 - 200 kHz
Bandwidth
RFAIN Input
ZIN;RF - 1.0 - - MΩ RFAIN
Impedance
RFAIN Input
CIN;RF - 3 - 5 pF
Capacitance
NOTE1) Output fall time from VIH;I2C min to VIL;I2C max with a bus capacitance from 10 pF to 400 pF.
NOTE2) This is the allowable capacitance value before the RC filter.
NOTE3) Total of frequency tolerance includes aging and temperature stability.
NOTE4) These pins must be set to the same output current mode.
NOTE5) Choose output current mode so that TS outputs swing rail-to-rail to ensure AC timings. It is recommended to
use 10 mA setting when TS clock frequency is above 100 MHz.
NOTE6) Clock frequency must be carefully chosen depending on IF frequency of tuner to avoid clock interference to IF.
Mandatory setting registers according to the XTALI input clock frequency.
NOTE8) Refer to TS output load capacitance parameter for GPIO2 when GPIO2 is used as TSERR to align with TS
interface AC timing including TSERR.
NOTE9) These values are for the maximum TS serial clock frequency setting. TS serial clock frequency can be selected
2
by I C registers as shown in TS Output Interface section to reduce TS signal digital noise interference to IF.
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CXD2854ER
tof
70 %
SDA
30 %
tBUF
tSU;DAT tHD;STA tSP
tLOW
SCL
2
Fig.3. Waveform of I C Interface
TSCLK 50 %
tCYC
TSDATA[7:0]
TSVALID 50 %
TSSYNC
GPIO2(TSERR)
tPD
tHIGH tLOW
TSCLK 50 %
tCYC
TSDATA[7:0]
TSVALID 50 %
TSSYNC
GPIO2(TSERR)
tPD
NOTE: TSCLK polarity can be selected by a register setting.
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CXD2854ER
For all power supplies (i.e. CVDD, DVDD, AVDD and XVDD), there is no restriction on the order of applying or removing the
power supplies.
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CXD2854ER
9. I/O Interfaces
The CXD2854ER operates with the reference clock from a crystal or external clock source. XTALI and XTALO are the
2
crystal oscillator input and output. The oscillator is enabled by default and can be disabled by an I C register.
XTALI, XTALO
Internal voltage bias exists on XTALI and XTALO
The crystal oscillator has internal bias voltage to pull XTALI to its operating DC level when the oscillator is active. There
are two ways to input clock, one is to connect crystal between XTALI and XTALO, and other is to input AC coupled external
sine wave clock from XTALI.
TAINP, TAINM
Initial Condition: Hi-Z (Not biased)
These are the differential IF input interface for terrestrial and cable.
Standard-IF signal and Low-IF signal are supported.
NOTE1) Low-IF signal frequencies are not standardized and restrictions may apply to certain combinations of center
frequency and bandwidth.
The ADC is internally biased at the center of the dynamic range in operating mode. When the CXD2854ER is powered-up,
TAINP and TAINM are at high impedance without internally bias voltage. Therefore, the AC signal input may be clamped
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CXD2854ER
by the ESD device to ground in standby mode depending on the voltage level applied.
SIAIN, SQAIN
Initial Condition: Hi-Z (Not biased)
These are the single-end zero-IF input interfaces for satellite. SIAIN is the I-ch input and SQAIN is the Q-ch input.
The ADC is internally biased at the center of the dynamic range in operating mode. When the CXD2854ER is powered-up,
SIAIN and SQAIN are at high impedance without internally bias voltage. Therefore, the AC signal input may be clamped by
the ESD device to ground in standby mode depending on the voltage level applied.
RFAIN
Initial Condition: Hi-Z
RST_X
I/O type: Schmitt, 5 V tolerant
RST_X Description
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CXD2854ER
RST_X Description
2
9-6. I C Interfaces
Corresponding I/Os are: SCL, SDA, TTUSCL, TTUSDA, SLVADR0 and SLVADR3
2
I C bus is used to control CXD2854ER.
CXD2854ER supports both Standard Mode and Fast Mode. CXD2854ER does not convert the mode between host and
RF tuner, so whatever mode is selected by the host to communicate with the CXD2854ER is the mode used between
CXD2854ER and RF tuner. For example, if the host communicates with the CXD2854ER in Standard Mode using SCL
and SDA, the communications between CXD2854ER and RF tuner using TTUSCL and TTUSDA are also in Standard
Mode.
Standard Mode SCL operates at 100 kHz. When in Standard Mode, TTUSCL also operates at 100 kHz.
Fast Mode SCL operates at 400 kHz. When in Fast Mode, TTUSCL also operates at 400 kHz.
Access to RF tuner
2 2 2
There are two ways to access RF tuner through tuner I C interface. One is “I C Repeater” function and the other is “I C
Gateway” function.
I2C Repeater function allows a host directly communicates to RF tuner through CXD2854ER. CXD2854ER just transparently
propagates the I2C commands received from the host I2C interface to the tuner I 2C interface. CXD2854ER can enable or
2 2
disable I C Repeater function by setting I C register of the CXD2854ER.
2
I C gateway function requires a special protocol to communicate with RF tuner. When a host writes a gateway command
2
(0x09) to the CXD2854ER, CXD2854ER recognize the gateway command and propagates data between the host I C
2 2 2
interface and the tuner I C interface. Unlike I2C Repeater function, I C gateway function does not require an I C register
setting to enable or disable the function.
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CXD2854ER
2
Table.10. I C Slave Addresses Including read/write bit
SCL, SDA
I/O type: Schmitt, 5 V tolerant, Open-drain
Initial Condition: Hi-Z
These are I2C slave interface to control the CXD2854ER. The bus can also communicate to RF tuner through the tuner I 2C
interface (i.e. TTUSCL and TTUSDA) under the repeater function that transparently propagates the I 2C commands from a
host to RF tuner. Mandatory protocol features for a slave configuration are supported as listed in the NXP specification
2
reference document: UM10204”I C - Bus specification and user manual Rev.03 – 19 June 2007”. Refer to Table 2 on page 8
of the reference document.
TTUSCL, TTUSDA
I/O type: Schmitt, 5 V tolerant, Open-drain
Initial Condition: Hi-Z
2 2
These are for the tuner I C bus that connects CXD2854ER to RF tuner. The tuner I C Interface supports the mandatory
protocol features for a single master configuration as listed in the NXP specification reference document: UM10204 “I 2C -
Bus specification and user manual Rev. 03 – 19 June 2007”. Refer to Table 2 on page 8 of the reference document.
These pins are expected to be pulled up by external pull-up resistors. They must be pulled up even when they are not
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CXD2854ER
used in a system.
SLVADR0
I/O type: Internal pull-down, 5 V tolerant
2
This is the bit 0 (LSB) of I C slave address. The pin is internally pulled-down. Therefore, when the pin is open, SLVADR0
2
becomes “0”. Fix SLAVDR0 before the hardware reset is negated to make sure the I C slave address of the CXD2854ER
is fixed before it becomes active.
SLVADR0 Description
2
0 Set LSB of the I C slave address to 0.
SLVADR3
I/O type: Internal pull-up, 5 V tolerant
This is the bit 3 of I2C slave address. The pin is internally pulled-up. Therefore, when the pin is open, SLVADR3 becomes
“1”. Fix SLAVDR3 before the hardware reset is negated to make sure the I2C slave address of the CXD2854ER is fixed
before it becomes active.
SLVADR3 Description
2
0 Set Bit 3 of the I C slave address to 0.
2
1 Set Bit 3 of the I C slave address to 1.
The AGC output operates as a control signal from CXD2854ER to RF. It creates a feedback loop to automatically adjust
input signal level received by the demodulator. At the AGC pin, the control signal is output in PWM form. PWM signal
requires external RC components to integrate LPF to remove PWM harmonic content. The PWM signal with integrated
LPF can create DC reference voltage.
TIFAGC
I/O type: n/a (CMOS output)
Initial Condition: Hi-Z
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CXD2854ER
This is the PWM output to control IF AGC gain for terrestrial tuner.
SAGC
I/O type: n/a (CMOS output)
Initial Condition: Hi-Z
This is the PWM output to control AGC gain for satellite tuner.
The TS output can be selected to be either parallel output or serial output. The serial data (TSDATA) can be output from
2
either TSDATA7 or TSDATA0. TS serial clock frequency can be selected from the following table by setting I C registers to
reduce TS signal digital noise interference to IF.
Table.13. TS serial clock frequencies for terrestrial and cable and satellite
CXD2854ER has a TS smoothing function to suppress PCR jitter of TS data. The following table shows the target PCR
jitter values of CXD2854ER.
NOTE1) In case of DVB-T2 standard, valid for modulation modes specified in DTG D-Book 7.0 Table 9-3a and Table 9-3b,
and NorDig-Unified Test Specifications version 2.2.1 Table 2.17. This value will not be guaranteed if a transmitter sends
M-PLP data with incorrect ISSY information.
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CXD2854ER
NOTE2) In case of DVB-C2 standard, valid for VV1XX modes. This value will not be guaranteed if a transmitter sends
M-PLP data with incorrect ISSY information.
DiSEqC interface conforms to DiSEqC 1.x, DiSEqC 2.x and Single Cable Distribution (CENELEC/BS EN 50494) standards
with external components. Supported DiSEqC versions are: DiSEqC 1.0, 1.1, 1.2, 2.0, 2.1 and 2.2.
DSQIN
I/O type: 5 V tolerant
Initial Condition: Hi-Z
Up to 16 words (max.) of the reply signal output by a slave device can be received.
DSQOUT
I/O type: 5 V tolerant
Initial Condition: Hi-Z
GPIO pins (i.e. GPIO0, GPIO1 and GPIO2) operate as a programmable control signal configured through I 2C register setting.
GPIO pins have multiple functions which are shown in the following table. TSERR signal can be output only from GPIO2
pin. All other functions can be mapped to any of GPIO0, GPIO1 and GPIO2. PWM signal requires external RC
components to integrate LPF to remove PWM harmonic content. The PWM signal with integrated LPF can create DC
reference voltage.
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CXD2854ER
PWM PWM signal output for general purpose. It can be used for RFAGC with
O
LPF.
T.B.D - T.B.D
NOTE1) Output current mode must be set to 8 mA (IOL = +8mA, IOH = -8mA) for these functions.
NOTE2) Output current mode must be set to match with other TS outputs (i.e. TSCLK, TSVALID, TSSYNC, TSDATA[7:0])
NOTE3) DSQTXEN and DSQRXEN can be output from TSDATA6 pin when TS output is set to serial output mode.
These are the general purpose I/Os. GPIO2 has selectable output current function to match AC timing with TS interface
when GPIO2 is used as TSERR.
TESTMODE
I/O type: Internal pull-down, 5 V tolerant
This pin is to set LSI testing mode. For normal operation, connect TESTMODE directly to ground.
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CXD2854ER
TESTMODE Description
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CXD2854ER
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CXD2854ER
11. Marking
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CXD2854ER
IMPORTANT INFORMATION
Application circuits shown, if any, are typical examples illustrating the operation of the devices, they are shown for general guidance
purposes and may not be specifically relevant to individual requirements. Therefore, whilst Sony endeavour to ensure th at the information
shown is as accurate as reasonably possible, Sony does not accept liability for any faults, damage or losses of any nature (i ncluding, but
not limited, to consequential loss) arising from the use of the information contained in this document.
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