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LED TV
SERVICE MANUAL
CHASSIS : LD43B/LD44B

MODEL : 42LB55** 42LB55**-Z*


42LB552V 42LB552V-TB
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

P/NO : MFL68003704 (1312-REV00) Printed in Korea

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CONTENTS

CONTENTS . ............................................................................................. 2

SAFETY PRECAUTIONS ......................................................................... 3

SERVICING PRECAUTIONS ................................................................... 4

SPECIFICATION ....................................................................................... 6

ADJUSTMENT INSTRUCTION .............................................................. 10

EXPLODED VIEW .................................................................................. 17

SCHEMATIC CIRCUIT DIAGRAM ..............................................................

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SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE


Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

General Guidance Leakage Current Hot Check (See below Figure)


Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC Do not use a line Isolation Transformer during this check.
power line. Use a transformer of adequate power rating as this Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
protects the technician from accidents resulting in personal injury between a known good earth ground (Water Pipe, Conduit, etc.)
from electrical shocks. and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
It will also protect the receiver and it's components from being with 1000 ohms/volt or more sensitivity.
damaged by accidental shorts of the circuitry that may be Reverse plug the AC cord into the AC outlet and repeat AC voltage
inadvertently introduced during the service operation. measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
If any fuse (or Fusible Resistor) in this TV receiver is blown, 0.5 mA.
replace it with the specified. In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
When replacing a high wattage resistor (Oxide Metal Film Resistor, repaired before it is returned to the customer.
over 1 W), keep the resistor 10 mm away from PCB.
Leakage Current Hot Check circuit
Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

Always perform an AC leakage current check on the exposed


metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.

Leakage Current Cold Check(Antenna Cold Check)


With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.

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SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service 2. After removing an electrical assembly equipped with ES
manual and its supplements and addenda, read and follow the devices, place the assembly on a conductive surface such as
SAFETY PRECAUTIONS on page 3 of this publication. aluminum foil, to prevent electrostatic charge buildup or expo-
NOTE: If unforeseen circumstances create conflict between the sure of the assembly.
following servicing precautions and any of the safety precautions 3. Use only a grounded-tip soldering iron to solder or unsolder
on page 3 of this publication, always follow the safety precau- ES devices.
tions. Remember: Safety First. 4. Use only an anti-static type solder removal device. Some sol-
der removal devices not classified as “anti-static” can generate
General Servicing Precautions electrical charges sufficient to damage ES devices.
1. Always unplug the receiver AC power cord from the AC power 5. Do not use freon-propelled chemicals. These can generate
source before; electrical charges sufficient to damage ES devices.
a. Removing or reinstalling any component, circuit board 6. Do not remove a replacement ES device from its protective
module or any other receiver assembly. package until immediately before you are ready to install it.
b. Disconnecting or reconnecting any receiver electrical plug (Most replacement ES devices are packaged with leads elec-
or other electrical connection. trically shorted together by conductive foam, aluminum foil or
c. Connecting a test substitute in parallel with an electrolytic comparable conductive material).
capacitor in the receiver. 7. Immediately before removing the protective material from the
CAUTION: A wrong part substitution or incorrect polarity leads of a replacement ES device, touch the protective mate-
installation of electrolytic capacitors may result in an explo- rial to the chassis or circuit assembly into which the device will
sion hazard. be installed.
2. Test high voltage only by measuring it with an appropriate CAUTION: Be sure no power is applied to the chassis or cir-
high voltage meter or other voltage measuring device (DVM, cuit, and observe all other safety precautions.
FETVOM, etc) equipped with a suitable high voltage probe. 8. Minimize bodily motions when handling unpackaged replace-
Do not test high voltage by "drawing an arc". ment ES devices. (Otherwise harmless motion such as the
3. Do not spray chemicals on or near this receiver or any of its brushing together of your clothes fabric or the lifting of your
assemblies. foot from a carpeted floor can generate static electricity suf-
4. Unless specified otherwise in this service manual, clean ficient to damage an ES device.)
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable General Soldering Guidelines
non-abrasive applicator; 10 % (by volume) Acetone and 90 % 1. Use a grounded-tip, low-wattage soldering iron and appropri-
(by volume) isopropyl alcohol (90 % - 99 % strength) ate tip size and shape that will maintain tip temperature within
CAUTION: This is a flammable mixture. the range or 500 °F to 600 °F.
Unless specified otherwise in this service manual, lubrication 2. Use an appropriate gauge of RMA resin-core solder composed
of contacts in not required. of 60 parts tin/40 parts lead.
5. Do not defeat any plug/socket B+ voltage interlocks with which 3. Keep the soldering iron tip clean and well tinned.
receivers covered by this service manual might be equipped. 4. Thoroughly clean the surfaces to be soldered. Use a mall wire-
6. Do not apply AC power to this instrument and/or any of its bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
electrical assemblies unless all solid-state device heat sinks Do not use freon-propelled spray-on cleaners.
are correctly installed. 5. Use the following unsoldering technique
7. Always connect the test receiver ground lead to the receiver a. Allow the soldering iron tip to reach normal temperature.
chassis ground before connecting the test receiver positive (500 °F to 600 °F)
lead. b. Heat the component lead until the solder melts.
Always remove the test receiver ground lead last. c. Quickly draw the melted solder with an anti-static, suction-
8. Use with this receiver only the test fixtures specified in this type solder removal device or with solder braid.
service manual. CAUTION: Work quickly to avoid overheating the circuit
CAUTION: Do not connect the test fixture ground strap to any board printed foil.
heat sink in this receiver. 6. Use the following soldering technique.
a. Allow the soldering iron tip to reach a normal temperature
Electrostatically Sensitive (ES) Devices (500 °F to 600 °F)
Some semiconductor (solid-state) devices can be damaged eas- b. First, hold the soldering iron tip and solder the strand
ily by static electricity. Such components commonly are called against the component lead until the solder melts.
Electrostatically Sensitive (ES) Devices. Examples of typical ES c. Quickly move the soldering iron tip to the junction of the
devices are integrated circuits and some field-effect transistors component lead and the printed circuit foil, and hold it there
and semiconductor “chip” components. The following techniques only until the solder flows onto and around both the compo-
should be used to help reduce the incidence of component dam- nent lead and the foil.
age caused by static by static electricity. CAUTION: Work quickly to avoid overheating the circuit
1. Immediately before handling any semiconductor component or board printed foil.
semiconductor-equipped assembly, drain off any electrostatic d. Closely inspect the solder area and remove any excess or
charge on your body by touching a known earth ground. Alter- splashed solder with a small wire-bristle brush.
natively, obtain and wear a commercially available discharg-
ing wrist strap device, which should be removed to prevent
potential shock reasons prior to applying power to the unit
under test.

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IC Remove/Replacement 3. Solder the connections.
Some chassis circuit boards have slotted holes (oblong) through CAUTION: Maintain original spacing between the replaced
which the IC leads are inserted and then bent flat against the cir- component and adjacent components and the circuit board to
cuit foil. When holes are the slotted type, the following technique prevent excessive component temperatures.
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique Circuit Board Foil Repair
as outlined in paragraphs 5 and 6 above. Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
Removal board causing the foil to separate from or "lift-off" the board. The
1. Desolder and straighten each IC lead in one operation by following guidelines and procedures should be followed when-
gently prying up on the lead with the soldering iron tip as the ever this condition is encountered.
solder melts.
2. Draw away the melted solder with an anti-static suction-type At IC Connections
solder removal device (or with solder braid) before removing To repair a defective copper pattern at IC connections use the
the IC. following procedure to install a jumper wire on the copper pattern
Replacement side of the circuit board. (Use this technique only on IC connec-
1. Carefully insert the replacement IC in the circuit board. tions).
2. Carefully bend each IC lead against the circuit foil pad and
solder it. 1. Carefully remove the damaged copper pattern with a sharp
3. Clean the soldered areas with a small wire-bristle brush. knife. (Remove only as much copper as absolutely necessary).
(It is not necessary to reapply acrylic coating to the areas). 2. Carefully scratch away the solder resist and acrylic coating (if
used) from the end of the remaining copper pattern.
"Small-Signal" Discrete Transistor 3. Bend a small "U" in one end of a small gauge jumper wire and
Removal/Replacement carefully crimp it around the IC pin. Solder the IC connection.
1. Remove the defective transistor by clipping its leads as close 4. Route the jumper wire along the path of the out-away copper
as possible to the component body. pattern and let it overlap the previously scraped end of the
2. Bend into a "U" shape the end of each of three leads remain- good copper pattern. Solder the overlapped area and clip off
ing on the circuit board. any excess jumper wire.
3. Bend into a "U" shape the replacement transistor leads.
4. Connect the replacement transistor leads to the corresponding At Other Connections
leads extending from the circuit board and crimp the "U" with Use the following technique to repair the defective copper pattern
long nose pliers to insure metal to metal contact then solder at connections other than IC Pins. This technique involves the
each connection. installation of a jumper wire on the component side of the circuit
board.
Power Output, Transistor Device
Removal/Replacement 1. Remove the defective copper pattern with a sharp knife.
1. Heat and remove all solder from around the transistor leads. Remove at least 1/4 inch of copper, to ensure that a hazardous
2. Remove the heat sink mounting screw (if so equipped). condition will not exist if the jumper wire opens.
3. Carefully remove the transistor from the heat sink of the circuit 2. Trace along the copper pattern from both sides of the pattern
board. break and locate the nearest component that is directly con-
4. Insert new transistor in the circuit board. nected to the affected copper pattern.
5. Solder each transistor lead, and clip off excess lead. 3. Connect insulated 20-gauge jumper wire from the lead of the
6. Replace heat sink. nearest component on one side of the pattern break to the
lead of the nearest component on the other side.
Diode Removal/Replacement Carefully crimp and solder the connections.
1. Remove defective diode by clipping its leads as close as pos- CAUTION: Be sure the insulated jumper wire is dressed so the
sible to diode body. it does not touch components or sharp edges.
2. Bend the two remaining leads perpendicular y to the circuit
board.
3. Observing diode polarity, wrap each lead of the new diode
around the corresponding lead on the circuit board.
4. Securely crimp each connection and solder it.
5. Inspect (on the circuit board copper side) the solder joints of
the two "original" leads. If they are not shiny, reheat them and
if necessary, apply additional solder.

Fuse and Conventional Resistor


Removal/Replacement
1. Clip each fuse or resistor lead at top of the circuit board hollow
stake.
2. Securely crimp the leads of replacement component around
notch at stake top.

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SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.

1. Application range 3. Test method


This specification is applied to the LED TV used LD43B/ 1) Performance: LGE TV test method followed
LD43M/LD44B chassis. 2) Demanded other specification
- Safety : CE, IEC specification
- EMC : CE, IEC
2. Requirement for Test
Each part is tested as below without special appointment.

1) Temperature: 25 °C ± 5 °C(77 °F ± 9 °F), CST: 40 °C ± 5 °C


2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
: Standard input voltage (AC 100-240 V~, 50/60 Hz)
* Standard Voltage of each products is marked by models.
4) Specification and performance of each parts are followed
each drawing and specification by part number in
accordance with BOM.
5) The receiver must be operated for about 5 minutes prior to
the adjustment.

4. Model General Specification


No. Item Specification Remarks
1 Market EU(PAL Market-37Countries) DTV & Analog (Total 37 countries)
DTV (MPEG2/4, DVB-T) :37 countries
UK/Italy/Germany/France/Spain/Sweden/Finland/Netherlands/
Belgium/Luxemburg/ Greece/Denmark/Czech/Austria /Hun-
gary/Swiss/Croatia/TurkeyNorway/Slovenia/Poland/Ukraine/
Portugal/Ireland/Morocco/Latvia/Estonia/Lithania/Rumania/
Bulgaria/Russia/SlovakiaBosnia/Serbia/Albania/Kazakhstan/
Belarus

DTV (MPEG2/4, DVB-T2): 8 countries


UK/Denmark/Sweden/Finland/Norway/Ireland/Ukraine/Kaza-
khstan

DTV (MPEG2/4, DVB-C): 37 countries


UK/Italy/Germany/France/Spain/Sweden/Finland/Netherlands/
Belgium/Luxemburg/ Greece/Denmark/Czech/Austria /Hun-
gary/Swiss/Croatia/TurkeyNorway/Slovenia/Poland /Ukraine/
Portugal/Ireland/Morocco/Latvia/Estonia/Lithania/Rumania/
Bulgaria/Russia/SlovakiaBosnia/Serbia/Albania/Kazakhstan/
Belarus

DTV (MPEG2/4,DVB-S): 29 countries


Italy/Germany/France/Spain/Netherlands/ Belgium/Luxemburg/
Greece/Czech/Austria /Hungary/Swiss/Croatia/Turkey/Slove-
nia/Poland/Portugal/ Morocco/Latvia/Estonia/Lithania/Rumania/
Bulgaria/Russia/Slovakia/Bosnia/Serbia/Albania/Belarus

Supported satellite : 22 satellites


HISPASAT 1C/1D, ATLANTIC BIRD 2, NILESAT 101/102,
ATLANTIC BIRD 3, AMOS 2/3, THOR 5/6, IRIUS 4, EUTEL-
SAT-W3A, EUROBIRD 9A, EUTELSAT-W2A, HOTBIRD 6/8/9,
EUTELSAT-SESAT, ASTRA 1L/H/M/KR, ASTRA 3A/3B, BADR
4/6, ASTRA 2D, EUROBIRD 3, EUTELSAT-W7, HELLASSAT
2, EXPRESS AM1, TURKSAT 2A/3A, INTERSAT10

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No. Item Specification Remarks
Analogue TV
1) PAL-BG Analogue TV : (RF) VHF: E2 to E12, UHF : E21 to E69
2) PAL-DK (CATV) S1 to S20, HYPER: S21 to S47
3) PAL-I/I’
4) SECAM-BG Digital TV : VHF, UHF
5) SECAM-DK
2 Broadcasting system 6) SECAM L/L’ Satellite TV : VHF, UHF,
C-Band, Ku-Band
Digital TV
1) DVB-T/C/T2 * DVB-T2 ( T2 model only support )

Satellite Digital TV * DVB-S/S2 (Satellite model only support )


1) DVB-T/C/S2
► DVB-T
- Guard Interval(Bitrate_Mbit/s) : 1/4, 1/8, 1/16, 1/32
- Modulation : Code Rate
QPSK : 1/2, 2/3, 3/4, 5/6, 7/8
16-QAM : 1/2, 2/3, 3/4, 5/6, 7/8
64-QAM : 1/2, 2/3, 3/4, 5/6, 7/8

► DVB-T2
- Guard Interval(Bitrate_Mbit/s)
: 1/4, 1/8, 1/16, 1/32, 1/128, 19/128, 19/256,
- Modulation : Code Rate
QPSK : 1/2, 2/5, 2/3, 3/4, 5/6
Analog : Upper Heterodyne 16-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
3 Receiving system Digital : COFDM, QAM 64-QAM : 1/2, 2/5, 2/3, 3/4, 5/6
256-QAM : 1/2, 2/5, 2/3, 3/4, 5/6

► DVB-C
- Symbolrate : 4.0Msymbols/s to 7.2Msymbols/s
- Modulation : 16QAM, 64-QAM, 128-QAM and 256-QAM

► DVB-S/S2
- symbolrate
DVB-S2 (8PSK / QPSK) : 2 ~ 45Msymbol/s
DVB-S (QPSK) : 2 ~ 45Msymbol/s
- viterbi
DVB-S mode : 1/2, 2/3, 3/4, 5/6, 7/8
DVB-S2 mode : 1/2, 2/3, 3/4, 3/5, 4/5, 5/6, 8/9, 9/10
4 Scart Jack (1EA) PAL, SECAM Scart 1 Jack is Full scart and support RF-OUT(analog).
Video Input RCA
4 System : PAL, SECAM, NTSC, PAL60
Component & AV (PAL, SECAM, NTSC)
5
Common port (1EA) Component Input
(Y/Cb/Cr, Y/Pb/Pr)
7 HDMI Input (2EA) HDMI1/2-DTV Support HDCP
8 Audio Input (1EA) Component & AV Component & AV’s audio input is used by common port.
9 SDPIF out (1EA) SPDIF out
Antenna, AV1, AV2, Component,
10 Earphone out (1EA) LB62 &LB56 Series
HDMI1, HDMI2
11 USB (1EA) EMF, DivX HD, For SVC (download) JPEG, MP3, DivX HD
CI : U
 K, Finland, Denmark, Norway, Sweden, Russia, Spain,
DVB-T Ireland, Luxemburg, Belgium, Netherland
CI+ : France(Canal+), Italy(DGTVi)
12 DVB CI : Switzerland, Austria, Slovenia, Hungary, Bulgaria
DVB-C CI+ : S
 witzerland(UPC,Cablecom), Netherland(Ziggo),
Germany(KDG,CWB), Finland(labwise)
DVB-S CI + : Germany(Astra HD+ )
LB62 : for DLNA
13 Ethernet (1EA) DLNA(Wired, DMP only)
T2 Model ( LB62, LB56, LB55 ) : for MHEG

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5. Video resolutions (2D)
5.1. Component Input (Y, CB/PB, CR/PR)
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed
1 720*576 15.625 50.00 13.5 SDTV ,DVD 576I
2 720*480 15.73 60.00 13.5135 SDTV ,DVD 480I
3 720*480 15.73 59.94 13.50 SDTV ,DVD 480I
4 720*576 31.25 50.00 27.00 SDTV 576P
5 720*480 31.50 60.00 27.027 SDTV 480P
6 720*480 31.47 59.94 27.00 SDTV 480P
7 1280*720 37.50 50.00 74.25 HDTV 720P
8 1280*720 45.00 60.00 74.25 HDTV 720P
9 1280*720 44.96 59.94 74.176 HDTV 720P
10 1920*1080 28.125 50.00 74.25 HDTV 1080I
11 1920*1080 33.75 60.00 74.25 HDTV 1080I
12 1920*1080 33.72 59.94 74.176 HDTV 1080I
13 1920*1080 56.25 50.00 148.50 HDTV 1080P
14 1920*1080 67.50 60.00 148.50 HDTV 1080P
15 1920*1080 67.432 59.94 148.352 HDTV 1080P
16 1920*1080 27.00 24.00 74.25 HDTV 1080P
17 1920*1080 26.97 23.94 74.176 HDTV 1080P
18 1920*1080 33.75 30.00 74.25 HDTV 1080P
19 1920*1080 33.71 29.97 74.176 HDTV 1080P

5.2. HDMI Input(PC/DTV)


No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed Remark
PC(DVI) DDC
1 640*350 31.468 70.09 25.17 EGA X
2 720*400 31.469 70.08 28.32 DOS O
3 640*480 31.469 59.94 25.17 VESA(VGA) O
4 800*600 37.879 60.31 40.00 VESA(SVGA) O
5 1024*768 48.363 60.00 65.00 VESA(XGA) O
6 1152*864 54.348 60.053 80.00 VESA O
7 1360*768 47.712 60.015 85.50 VESA (WXGA) O
8 1280*1024 63.981 60.020 108.0 VESA (SXGA) O FHD only
9 1920*1080 67.50 60.00 148.5 HDTV 1080P O FHD only
DTV
1 720*480 31.47 59.94 27.00 SDTV 480P
2 720*480 31.50 60.00 27.027 SDTV 480P
3 720*576 31.250 50.00 27.00 SDTV 576P
4 1280*720 37.50 50.00 74.25 HDTV 720P
5 1280*720 45.00 60.00 74.25 HDTV 720P
6 1280*720 44.96 59.94 74.176 HDTV 720P
7 1920*1080 28.125 50.00 74.25 HDTV 1080I
8 1920*1080 33.75 60.00 74.25 HDTV 1080I
9 1920*1080 33.72 59.94 74.176 HDTV 1080I
10 1920*1080 56.250 50.00 148.50 HDTV 1080P
11 1920*1080 67.50 60.00 148.50 HDTV 1080P
12 1920*1080 67.432 59.94 148.352 HDTV 1080P
13 1920*1080 27.00 24.00 74.25 HDTV 1080P
14 1920*1080 26.97 23.976 74.176 HDTV 1080P
15 1920*1080 33.75 30.00 74.25 HDTV 1080P

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6. Video resolutions (3D)
6.1. HDMI Input
No. Resolution H-freq(kHz) V-freq(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1. 1920*1080 53.95 / 54 23.98 / 24 148.35/148.5 HDTV 1080P Frame packing
2. 1280*720 89.9 / 90 59.94/60 148.35/148.5 HDTV 720P Frame packing
3. 1280*720 75 50 148.5 HDTV 720P Frame packing
4 1920*1080 67.5 60 148.5 HDTV 1080P Side by Side(half), Top and bottom
5 1920*1080 56.3 50 148.5 HDTV 1080P Side by Side(half), Top and bottom
6 1280*720 45 60 74.25 HDTV 720P Side by Side(half), Top and Bottom
7 1280*720 37.5 50 74.25 HDTV 720P Side by Side(half), Top and Bottom
8 1920*1080 33.7 60 74.25 HDTV 1080i Side by Side(half), Top and Bottom
9 1920*1080 28.125 50 74.25 HDTV 1080i Side by Side(half), Top and Bottom
10 1920*1080 27 24 74.25 HDTV 1080P Side by Side(half), Top and Bottom
11 1920*1080 33.7 30 89.1 HDTV 1080P Side by Side(half), Top and Bottom

6.2. RF 3D Input(DTV)
No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1. 1280*720 37.500 50 74.25 HDTV 720P Side by Side, Top & Bottom
2. 1920*1080 28.125 50 74.25 HDTV 1080I Side by Side, Top & Bottom

6.3. USB Input


No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
Side by Side, Top & Bottom **support
1. 1920*1080 33.75 30.000 74.25 HDTV 1080P
MPO(Photo)

6.4. DLNA Input


No. Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode
1. 1920*1080 33.75 30 74.25 HDTV 1080p Side by Side, Top & Bottom

6.5. 3D Input mode


No. Side by Side Top & Bottom Single Frame Sequential Frame Packing

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ADJUSTMENT INSTRUCTION
1. Application Range (4) Click "Connect" tab. If "Can't" is displayed, check connection
between computer, jig, and set.
This specification sheet is applied to all of the LED TV with
LD43B/LD43M/LD44B chassis.
(2) (3)

2. Designation
(1) The adjustment is according to the order which is designated
and which must be followed, according to the plan which
can be changed only on agreeing.
(2) Power adjustment : Free Voltage.
(3) Magnetic Field Condition: Nil.
(4) Input signal Unit: Product Specification Standard.
(5) Reserve after operation : Above 5 Minutes (Heat Run) Please Check the Speed :
Temperature : at 25 °C ± 5 °C To use speed between
Relative humidity : 65 ± 10 % from 200KHz to 400KHz
Input voltage : 220 V, 60 Hz
(6) Adjustment equipments: Color Analyzer(CA-210 or CA-110), (5) Click "Auto" tab and set as below.
DDC Adjustment Jig, Service remote control. (6) Click "Run".
(7) Push the "IN STOP" key - For memory initialization. (7) After downloading, check "OK" message.

Case1 : Software version up


(4)
1. After downloading S/W by USB , TV set will reboot
automatically. filexxx.bin
2. Push “In-stop” key. (5)
3. Push “Power on” key.
4. Function inspection
5. After function inspection, Push “In-stop” key. (7)...........OK
Case2 : Function check at the assembly line
1. When TV set is entering on the assembly line, Push
“In-stop” key at first. (6)
2. Push “Power on” key for turning it on.
→ If you push “Power on” key, TV set will recover
channel information by itself.
3. After function inspection, Push “In-stop” key.
* USB DOWNLOAD
(1) Put the USB Stick to the USB socket.
(2) Automatically detecting update file in USB Stick.
3. Main PCB check process - If your downloaded program version in USB Stick is Low,
▪ APC - After Manual-Insert, executing APC it didn't work. But your downloaded version is High, USB
data is automatically detecting.
(3) Show the message "Copying files from memory".
* Boot file Download (4) Updating is starting.
(1) Execute ISP program "Mstar ISP Utility" and then click
"Config" tab.
(2) Set as below, and then click "Auto Detect" and check "OK"
message.
If "Error" is displayed, check connection between computer,
jig, and set.
(3) Click "Read" tab, and then load download file(XXXX.bin)
by clicking "Read". (5) Updating Completed, The TV will restart automatically in 5
seconds.
(1) (6) If your TV is turned on, check your updated version and
Tool option. (explain the Tool option, next stage)
filexxx.bin * If downloading version is more high than your TV have, TV
can lost all channel data. In this case, you have to channel
recover. if all channel data is cleared, you didn’t have a DTV/
ATV test on production line.

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* After downloading, have to adjust Tool Option again. 3.3. EDID data
(1) Push "IN-START" key in service remote control. (1) HD HDMI EDID data (2D model)
(2) Select "Tool Option 1" and push "OK" key. 0 1 2 3 4 5 6 7 8 9 A B C D E F
(3) Punch in the number. (Each model has their number) 00 00 FF FF FF FF FF FF 00 1E 6D a b
(4) Completed selecting Tool option. 10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 01 01
30 01 01 01 01 01 01 66 21 50 B0 51 00 1B 30 40 70
3.1. ADC Process 40 36 00 40 84 63 00 00 1E 64 19 00 40 41 00 26 30
* If ADC processes as OTP, There is no need to proceed 50 18 88 03 06 40 84 63 00 00 18 00 00 00 FD 00 3A
internal ADC. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d
- Enter Service Mode by pushing "ADJ" key, 70 d 01 e
- Enter Internal ADC mode by pushing "►" key at "8. ADC 80 02 03 22 F1 4E 10 1F 04 93 05 14 03 02 12 20 21
Calibration". 90 22 15 01 26 15 07 50 09 57 07 f
A0 80 1E 01 1D 80 18 71 1C 16 20 58 2C 25 00 A0 5A
EZ ADJUST ADC Calibration
B0 00 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
0. Tool Option1 ADC Comp 480i
1. Tool Option2
OK
C0 20 C2 31 00 00 1E 8C 0A D0 8A 20 E0 2D 10 10 3E
ADC Comp 1080p OK
2. Tool Option3 ADC Type ◄ OTP ► D0 96 00 A0 5A 00 00 00 18 02 3A 80 18 71 38 2D 40
3. Tool Option4
Start Reset
E0 58 2C 45 00 A0 5A 00 00 00 1E 00 00 00 00 00 00
4. Tool Option5
5. Tool Option Commercial F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e
6. Country Group
7. Area Option
8.ADC Calibration ►
(2) FHD HDMI EDID data (2D model)
9. White Balance 0 1 2 3 4 5 6 7 8 9 A B C D E F
10. 10 Point WB
11. Test Pattern
00 00 FF FF FF FF FF FF 00 1E 6D a b
12 EDID D/L 10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
13. Sub B/C
20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
14. Ext. Input Adjust
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
<Caution> U sing "P-ONLY" key of the Adjustment remote 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
control, power on TV. 60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d
70 d 01 e
* ADC Calibration Protocol (RS232) 80 02 03 22 F1 4E 10 9F 04 13 05 14 03 02 12 20 21
NO Item CMD 1 CMD 2 Data 0 90 22 15 01 26 15 07 50 09 57 07 f
Enter Adjust Adjust When transfer the ‘Mode In’, A0 f 01 1D 80 18 71 1C 16 20 58 2C 25 00 20 C2
A A 0 0
MODE ‘Mode In’ Carry the command. B0 31 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55 00
ADC Automatically adjustment C0 20 C2 31 00 00 1E 02 3A 80 18 71 38 2D 40 58 2C
ADC adjust A D 1 0
Adjust (The use of a internal pattern)
D0 45 00 A0 5A 00 00 00 1E 01 1D 00 BC 52 D0 1E 20
E0 B8 28 55 40 C4 8E 21 00 00 1E 00 00 00 00 00 00
F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e
Adjust Sequence
▪ aa 00 00 [Enter Adjust Mode] (3) FHD HDMI EDID data (3D model)
▪ xb 00 40 [Component Input] 0 1 2 3 4 5 6 7 8 9 A B C D E F
▪ ad 00 10 [Adjust 480i & 1080p Comp] 00 00 FF FF FF FF FF FF 00 1E 6D a b
▪ aa 00 90 End Adjust mode 10 c 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
* Required equipment : Adjustment remote control. 20 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
3.2. EDID Download 40 45 00 A0 5A 00 00 00 1E 66 21 50 B0 51 00 1B 30
▪ After enter Service Mode by pushing "ADJ" key. 50 40 70 36 00 A0 5A 00 00 00 1E 00 00 00 FD 00 3A
60 3E 1E 53 10 00 0A 20 20 20 20 20 20 d
▪ Enter EDID D/L menu.
70 d 01 e
▪ Enter "START" by pushing "OK" key.
80 02 03 33 F1 4E 10 9F 04 13 05 14 03 02 12 20 21
EZ ADJUST EDID D/L
0. Tool Option1 HDMI1 NG 90 22 15 01 26 15 07 50 09 57 07 f
1. Tool Option2 HDMI2 NG A0 80 1E 20 C0 0E 01 40 0A 0F 08 10 18 10 98 10 58
2. Tool Option3 Start Reset
3. Tool Option4
B0 10 38 10 01 1D 80 18 71 1C 16 20 58 2C 25 00 20
4. Tool Option5 C0 C2 31 00 00 9E 01 1D 00 72 51 D0 1E 20 6E 28 55
5. Tool Option Commercial D0 00 20 C2 31 00 00 1E 02 3A 80 18 71 38 2D 40 58
6. Country Group
7. Area Option
E0 2C 45 00 A0 5A 00 00 00 1E 01 1D 00 BC 52 D0 1E
8. ADC Calibration F0 20 B8 28 55 40 C4 8E 21 00 00 1E 00 00 00 00 e
9. White Balance
10. 10 Point WB
11. Test Pattern
12. EDID D/L ►
13. Sub B/C
14. Ext. Input Adjust

<Caution> Never connect HDMI cable when EDID downloaded.

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(3) Detail EDID Options are below
a. Product ID
4. Total Assembly line process
4.1. White Balance adjustment
MODEL NAME HEX EDID Table DDC Function ▪ W/B Equipment condition
HD/FHD Model 0001 01 00 Analog/Digital CA210 : LED -> CH14, Test signal: Inner pattern(80IRE)
▪ Above 5 minutes H/run in the inner pattern. (“power on” key
b. Serial No: Controlled on production line. of adjust remote control)
c. Month, Year: ▪ If it is executed W/B adjustment in 2~3 minutes H/run, it is
ex) Week : '01' -> '01' adjusted by Target data.
Year : '2014' -> '18' fix Mode Temp Coordinate spec Target
d. Model Name(Hex): X=0.271 (±0.002) X=0.278
cf) TV set’s model name in EDID data is below. Cool 13,000 K
Y=0.270 (±0.002) Y=0.280
Model name MODEL NAME(HEX) X=0.285 (±0.002) X=0.293
Medium 9,300 K
LG TV 00 00 00 FC 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 (LG TV) Y=0.293 (±0.002) Y=0.299
X=0.313 (±0.002) X=0.320
e. Checksum: Changeable by total EDID data. Warm 6,500 K
Y=0.329 (±0.002) Y=0.339
HD FHD(2D) FHD(3D)
EDID C/S data ▪ Normal line(LGD/CMI, March ~ December for Gumi, Global)
HDMI HDMI HDMI
Cool Medium Warm
Block 0 75 41 41 Aging time
Check sum NetCase4 X y x y x y
5B (HDMI1) 25 (HDMI1) 23 (HDMI1) (Min)
(Hex) Block 1 271 270 285 293 313 329
4B (HDMI2) 15 (HDMI2) 13 (HDMI2)
1 0-2 281 287 295 310 320 342
2 3-5 280 285 294 308 319 340
f. Vendor Specific(HDMI)
3 6-9 278 284 292 307 317 339
INPUT Model name(HEX)_2D Model name(HEX)_3D
4 10-19 276 281 290 304 315 336
HDMI1 67030C001000801E 78030C001000801E 5 20-35 275 277 289 300 314 332
HDMI2 67030C002000801E 78030C002000801E 6 36-49 274 274 288 297 313 329
7 50-79 273 272 287 295 312 327
8 80-119 272 271 286 294 311 326
9 Over 120 271 270 285 293 310 325
3.4. Function Check ▪ Normal line(LGD/CMI, January ~ February for Gumi, Apply
- Check display and sound not Cinema Screen)
■ Check Input and Signal items. Cool Medium Warm
1) TV Aging time
NetCase4 X y x y x y
2) AV (SCART / CVBS) (Min)
3) COMPONENT (480i) 271 270 285 293 313 329
4) HDMI 1 0-2 283 292 297 315 322 347
* Display and Sound check is executed by Remote control. 2 3-5 282 290 296 313 321 345
3 6-9 280 288 294 311 319 343
<Caution> 4 10-19 277 284 291 307 316 339
Not to push the INSTOP key after completion if the function 5 20-35 275 279 289 302 314 334
inspection. 6 36-49 274 275 288 298 313 330
7 50-79 273 272 287 295 312 327
8 80-119 272 271 286 294 311 326
9 Over 120 271 270 285 293 310 325
▪ Aging chamber(LGD/CMI)
Cool Medium Warm
Aging time
NetCase4 X y x y x y
(Min)
271 270 285 293 313 329
1 0-5 280 285 294 308 319 340
2 6-10 276 280 290 303 315 335
3 11-20 272 275 286 298 311 330
4 21-30 269 272 283 295 308 327
5 31-40 267 268 281 291 306 323
6 41-50 266 265 280 288 305 320
7 51-80 265 263 279 286 304 318
8 81-119 264 261 278 284 303 316
9 Over 120 264 260 278 283 303 315

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▪ Use only AUO/Sharp/CSOT(Cool temp Spec is 13000 K) * Manual W/B process using adjust Remote control.
Cool Medium Warm ▪ After enter Service Mode by pushing "ADJ" key,
X y x y x y ▪ E nter White Balance by pushing " ► " key at "9. White
spec 271 270 285 293 313 329 Balance".
EZ ADJUST
target 275 276 289 299 317 335
0. Tool Option1
Whit Balance
1. Tool Option2
2. Tool Option3 Color Temp. ◄ Cool ►
▪ W/B information 3. Tool Option4 R-Gain 172
G-Gain 172
Model information W/B information 4. Tool Option5
5. Tool Option Commercial B-Gain 192

Model Module Panel Backlight Type Using W/B table 6. Country Group R-Cut 64
7. Area Option G-Cut 64
All All All Direct LED O 8. ADC Calibration B-Cut 64
9. White Balance Test-Pattern ON
10. 10 Point WB Backlight 100
Reset To Set
* Connecting picture of the measuring instrument 11. Test Pattern
12 EDID D/L
(On Automatic control) 13. Sub B/C

Inside PATTERN is used when W/B is controlled. Connect to 14. Ext. Input Adjust

auto controller or push Adjustment R/C P-ONLY → Enter the


mode of White-Balance, the pattern will come out. * CASE Cool Mode
First adjust the coordinate far away from the target
value(x, y).B.
1) x, y > target
Full White Pattern CA-210
2) x, y < target
COLOR 3) x >target, y < target
ANALYZER
TYPE : CA-210 4) x < target, y > target
-E  very 4 case have to fit y value by adjusting B Gain
and then fit x value by adjusting R-Gain.
RS-232C Communication - In this case, increasing/decreasing of B Gain and R
Gain can be adjusted.

* Auto-control interface and directions How to adjust


(1) Adjust in the place where the influx of light like floodlight 1) In case G gain more than 172
around is blocked. (illumination is less than 10 lux). Adjust R Gain and B Gain less than 192
(2) Adhere closely the Color analyzer(CA210) to the module 2) If the G gain value be adjusted down to 172
less than 10 cm distance, keep it with the surface of the One of the R/B Gain is 254
Module and Color analyzer's prove vertically.(80° ~ 100°). 3) If G Gain is 172 , More than one of R/B Gain is to be
(3) Aging time between 192~254
- After aging start, keep the power on (no suspension of
power supply) and heat-run over 5 minutes. * CASE Medium / Warm
- Using 'no signal' or 'POWER ONLY' or the others, check First adjust the coordinate far away from the target
the back light on. value(x, y).
1) x, y > target
▪ Auto adjustment Map(using RS-232C to USB cable) i) Decrease the R, G.
RS-232C COMMAND 2) x, y < target
[CMD ID DATA] i) First decrease the B gain,
Wb 00 00 White Balance Start ii) Decrease the one of the others.
Wb 00 ff White Balance End 3) x > target, y < target
RS-232C COMMAND CENTER i) First decrease B, so make y a little more than the target.
[CMD ID DATA] (DEFAULT) ii) Adjust x value by decreasing the R
MIN MAX
4) x < target, y > target
Cool Mid Warm Cool Mid Warm
i) First decrease B, so make x a little more than the target.
R Gain jg Ja jd 00 172 192 192 254 ii) Adjust x value by decreasing the G
G Gain jh Jb je 00 172 192 192 192
B Gain ji Jc jf 00 192 192 172 254 * After you finished all adjustments, Press "In-start" key and
compare Tool option and Area option value with its BOM, if
R Cut 64 64 64 128
it is correctly same then unplug the AC cable. If it is not
G Cut 64 64 64 128 same, then correct it same with BOM and unplug AC cable.
B Cut 64 64 64 128 For correct it to the model's module from factory Jig model.
* P ush the "IN STOP" key after completing the function
<Caution> inspection. And Mechanical Power Switch must be set
Color Temperature : COOL, Medium, Warm. “ON”.
One of R Gain/G Gain/ B Gain should be kept on 0xC0, and
adjust other two lower than C0.(When R/G/B Gain are all
C0, it is the FULL Dynamic Range of Module)

Copyright © LG Electronics. Inc. All rights reserved. - 13 - LGE Internal Use Only
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4.2. 3D function test 4.4. MHL Test
(Pattern Generator MSHG-600, MSPG-6100[Support HDMI1.4]) (1) Turn on TV
* HDMI mode NO. 872 , pattern No.83 (2) Select HDMI2 mode using input Menu.
(1) Please input 3D test pattern like below. (3) Set MHL Zig(M1S0D3617) using MHL input, output and
power cord.
(4) Connect HDMI cable between MHL Zig and HDMI4 port.

(2) When 3D OSD appear automatically , then select OK key.

Result) I f, The LED light is green and the Module shows


normal stream → OK, Else → NG

4.5. Outgoing condition Configuration


■ When pressing IN-STOP key by SVC remocon, Red LED
(3) Don't wear a 3D Glasses, Check the picture like below. are blinked alternatively. And then automatically turn off.
(Must not AC power OFF during blinking)

4.3. IR emitter inspection


(1) Start 3D pattern inspection.
(2) If IR emitter signal is correctly received to IR receiver, the
lamp of IR tester turns on.

Copyright © LG Electronics. Inc. All rights reserved. - 14 - LGE Internal Use Only
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5. HI-POT Test 6.2. Command Set
5.1. HI-POT auto-check preparation Adjust mode CMD(hex) LENGTH(hex) Description
- Check the POWER cable and SIGNAL cable insertion condition EEPROM WRITE A0h 84h+n n-bytes Write (n = 1~16)
* Description
5.2. HI-POT auto-check FOS Default write : <7mode data> write
(1) Pallet moves in the station. (POWER CORD / AV CORD is Vtotal, V_Frequency, Sync_Polarity, Htotal, Hstart, Vstart, 0,
tightly inserted) Phase
Data write : Model Name and Serial Number write in EEPROM,.
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on.
(4) HI-POT test (Auto) 6.3. Method & notice
- If Test is failed, Buzzer operates. (1) Serial number D/L is using of scan equipment.
- If Test is passed, GOOD Lamp on and move to next proc- (2) S etting of scan equipment operated by Manufacturing
ess automatically. Technology Group.
(3) Serial number D/L must be conformed when it is produced in
production line, because serial number D/L is mandatory by
5.3. Checkpoint D-book 4.0.
(1) Test voltage
- Touchable Metal : 3 KV / min at 100 mA * Manual Download(Model Name and Serial Number)
- SIGNAL : 3KV / min at 100 mA If the TV set is downloaded by OTA or Service man, sometimes
(2) TEST time: 1 second. (case : mass production ) model name or serial number is initialized.(Not always)
(3) TEST POINT There is impossible to download by bar code scan, so It need
- Touchable Metal => LIVE & NEUTRAL : Touchable Metal. Manual download.
- SIGNAL => LIVE & NEUTRAL : SIGNAL. 1) Press the "Instart" key of Adjustment remote control.
2) Go to the menu "6.Model Number D/L" like below photo.
3) Input the Factory model name or Serial number like photo.

6. Model name & Serial number D/L


▪ Press "Power on" key of service remote control.
(Baud rate : 115200 bps)
▪ Connect RS232 Signal Cable to USB Jack.
▪ Write Serial number
▪ Must check the serial number at the Diagnostics of SET UP menu.
(Refer to below).

4) Check the model name Instart menu. → Factory name displayed.


ex 47LB560V-ZA)
5) Check the Diagnostics.(DTV country only) → Buyer model
displayed.(ex 47LB560V-ZA)

6.1. Signal Table


CMD LENGTH ADH ADL DATA_1 ... Data_n CS DELAY

CMD : A0h
LENGTH : 85~94h (1~16 bytes)
ADH : EEPROM Sub Address high (00~1F)
ADL : EEPROM Sub Address low (00~FF)
Data : Write data
CS : CMD + LENGTH + ADH + ADL + Data_1 +...+ Data_n
Delay : 20ms

Copyright © LG Electronics. Inc. All rights reserved. - 15 - LGE Internal Use Only
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7. MAC Address & CI+ key download 7.2. LAN Inspection
7.1 MAC Address 7.2.1. Equipment & Condition
▪ Each other connection to LAN Port of IP Hub and Jig
7.1.1 Equipment & Condition
▪ Play file : Serial.exe
▪ MAC Address edit
▪ Input Start / End MAC address

7.1.2 Download method


(1) Communication Prot connection

7.2.2. LAN inspection solution


▪ LAN Port connection with PCB
▪ Network setting at MENU Mode of TV
▪ Setting automatic IP
Connection: PCBA(USB Port) → USB to Serial Adapter(UC-
▪ Setting state confirmation
232A) → RS-232C cable → PC(RS-232C port)
-> If automatic setting is finished, you confirm IP and MAC
* Caution: L
 J21* chassis support only UC-232A driver. (only
Address.
use this one.)

(2) MAC Address & CI+ Key Download


▪ Set CI+ Key path Directory at Start Mac & CI+ Download
Programme
▪ Com 1,2,3,4 and 115200(Baudrate)

7.3. LAN PORT INSPECTION(PING TEST)


GP4_LOW Connect SET -> LAN port == PC -> LAN Port

SET PC

7.3.1. Equipment setting


(1) Play the LAN Port Test PROGRAM.
(2) Input IP set up for an inspection to Test Program.
*IP Number : 12.12.2.2
▪ Port connection button click(1)
▪ Push the (2) MAC Address write. 7.3.2. LAN PORT inspection (PING TEST)
▪ At success Download, check the OK (3) (1) Play the LAN Port Test Program.
▪ Start CI+ Key Download, Push the (4) (2) Connect each other LAN Port Jack.
▪ Check the OK or NG (3) Play Test (F9) button and confirm OK Message.
(4) Remove LAN cable.

Copyright © LG Electronics. Inc. All rights reserved. - 16 - LGE Internal Use Only
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EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.

500

502
501
400

900
420
410

521
540

121
530

120
LV1

820

Set + Stand
A10
AW1
A2
200

Copyright © LG Electronics. Inc. All rights reserved. - 17 - LGE Internal Use Only
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LD43B

Copyright © LG Electronics. Inc. All rights reserved. - 18 - LGE Internal Use Only
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L14 POWER BLOCK (POWER DETECT 2)

+24V +12V +3.5V_POWER_DET


OLD_18PIN +3.5V_ST

FROM LIPS or POWER B/D P401-*1


SMAW200-H18S1
R435
100K PD_+3.5V
Power_DET PANEL_VCC
+3.5V_ST OPT OPT R454-*1 OPT +12V PANEL_VCC
R457 R430 R432 300
Q401 R438
8.2K 2.7K 0
1% 5% 5% 4.7K
MMBT3906(NXP) PWR ON 1 2 DRV ON 1%
IC401
3.5V 3 4 PDIM#1 APX803D29
R454 L408
3.5V 5 6 3.5V 100 5% Q405
1 3 OPT VCC RESET UBW2012-121F
GND PDIM#2 3 2 POWER_DET DMP2130L
R412 7 8 120OHM
R406

D
10K 2 33K 24V 9 10 24V C415 1
R431 C422
+3.5V_ST GND 11 12 GND 0.1uF 1.2K GND OPT
R404 16V POWER_DET_RESET 0.1uF C425 R445 C427 R451 R452
12V 13 14 12V 1% 10uF 5.6K 5.6K
4.7K 0.1uF 33K G
12V 15 16 N.C 25V 16V
OPT OPT
R400 GND 17 18 GND +3.5V_POWER_DET R436
10K C Q400 +24V
100K
R402 R446
10K B MMBT3904(NXP)
12K
RL_ON 19
OPT
OPT OPT
R401 R455 R427 R458 IC402
E +3.3V_Normal 27K 0 APX803D29 OPT R442 C
10K 0 R437
1% 5% 100 5% 10K B Q403
OPT VCC 3 2 RESET PANEL_CTL
R456 MMBT3904(NXP)
0 +3.5V_ST OPT 1
R420 OPT R441 E
1K C413 R428 GND 10K
ZD404 0.1uF 5.1K
5V R419 16V 1%
100 R426
+3.5V_POWER_DET NEW_18PIN 10K
P401
SMAW200-H18S5
C
R425 Ready - Dual Power Det Power Detect activity
B 10K
L400 INV_CTL
CB2012PK501T
+3.5V_ST Detect Valtage Now is Use Circuit Designator FET_2.5V_DIODE
E Q402
PWR ON 1 2 DRV ON MMBT3904(NXP) Q406-*1
L401
C407
10uF
10V
C400
1uF
10V
ZD400
5V
CB2012PK501T 3.5V
3.5V
3 4 PDIM#1
3.5V
PWM_DIM Power Detect +3.5V R432, R454-*1, R438 +3.3V_Normal DMP2130L

D
2012 1005 5 6
OPT GND PDMI#2
L402 7 8 PWM1 * Notice Power Detect +12V O R430, R431, R454
MLB-201209-0120P-N2 24V 24V
+24V 9 10 PWM_DIM_PULL_DOWN PWM2_2CH_POWER
OPT
- Applying all inch models for LCD L14 +3.5V_ST +3.3V_Normal

G
+24V_CAP GND GND R424 R423
C401 11 12
100
R467 - Dual Power Det is used Power Detect +24V R457, R454
C432 12V 12V 3.9K 1K
4.7uF 0.1uF 13 14 for detecting two kinds of voltage
50V 12V NC FET_2.5V_AOS
50V 15 16
Q406 L410
3216 GND 17 18 GND
L403 AO3435 BLM18PG121SN1D
MLB-201209-0120P-N2
+12V

D
+12V_CAP
C433
4.7uF
C402
0.1uF
19
+1.10V_VDDC
.

C428 C429 C430

G
16V 16V R443 R447 ZD402
+3.5V_ST 10K 22K 2.2uF 0.1uF 22uF
3216 5V
IC403 +3.3V_Normal 10V 16V 10V
L406 TPS5432DDAR [EP]GND
CB2012PK501T
C418
OPT 0.01uF
C437 C436 C414 C435 BOOT SS R429 R448
1 8 2.2K
0.1uF 10uF 10uF 0.1uF 10K
THERMAL

16V 10V 10V 16V


+1.10V_VDDC VIN EN
9

2 7 C

+1.5V_DDR Vout=1.25*(1+R2/R1)+Iadj*R2 L407 C417


0.1uF
POWER_ON/OFF_1
R444
10K B Q404
3.6uH PH COMP MMBT3904(NXP)
16V 3 6 C416
+3.3V_Normal +1.5V_DDR 3A 0.33uF E
OPT R433 16V
ZD401 C424 C421 C420 GND VSENSE 2.7K
22uF 22uF 4 5
L409 IC404 L411 2.5V 0.1uF 1%
AZ1117EH-ADJTRG1 16V 10V 10V C419 C434
BLM18PG121SN1D CB2012PK501T C423 R439 0.039uF 390pF
50V 20K
R1 50V 50V
270pF 1%
IN OUT
ADJ/GND
C426 R449 R453 ZD403
10uF 1K R1 0 2.5V R440 R2
10V 1/16W 47K
1% C431 1%
10uF
1.3A R450
200
1/16W R2
10V

1%
Vout=0.808*(1+R1/R2)

+5V_Normal & +5V_USB with OCP


+12V

C405 C406
10uF 10uF
16V
[EP]GND

PGND_2

PGND_1
PGOOD

VIN_2

VIN_1

OPT R410
V7V

100K
C403
100pF +5V_Normal
50V C409 L405
24

23

22

21

20

19

0.047uF 4.7uH
EN BST 25V
C404
R408 4700pF 1 18
4.7K 50V THERMAL
+3.3V_Normal COMP 25
LX_2 R421 C411 C412
2 17 18K 82pF 22uF
+3.3V_Normal OPT SS LX_1 1% 50V 16V
R459 3 16
OPT OPT 0 IC400 R1
ROSC FB
R403 R405 4 15
4.7K 4.7K TPS65282REGR
EN_SW2 SW_IN_2 R2
MHL_5V_EN 5 14
MHL_SW_TR
R463
MHL_SW_TR
R464
USB1_CTL
EN_SW1
6
4A 13
SW_IN_1
R422
3.3K
2.7K 10K 1%
10

11

12
7

MHL_SW_TR +3.3V_Normal C410


+5V_USB 10uF
Q408 10V
FAULT2

FAULT1

SW_OUT2

RLIM

AGND

SW_OUT1

E C
MHL_5V_EN R407 R409
MHL_SW_TR 10K 10K
C
R461 R415 5V_HDMI_4 AVDD5V_MHL
10K B R466
B 15K
/VBUS_EN 20K
5%
D401 R418
(Active Low) MHL_SW_TR MBR230LSFT1G
E MHL_SW_TR
Q407 R465 30V 10
10K
MHL_SW_TR C OPT C408
R462 R416 10uF
10K
/MHL_OCP_DET

USB1_OCD

B 100K 10V
MHL_OCP_EN
MHL_SW_TR
(Active High) Q409 E

Vout=0.8*(1+R1/R2)

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013.09.14
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. Power_PD2 4

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USB (SIDE)

+5V_USB

JK700
ZD700 C700 C703
SD05 22uF 22uF
3AU04S-305-ZC-(LG)

5V 10V 10V
USB DOWN STREAM

OPT OPT
2

SIDE_USB1_DM
3

SIDE_USB1_DP
OPT OPT OPT
C701 C702 D700
5pF 5pF RCLAMP0502BA
4

50V 50V
5

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 13/04/30
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. USB_S1 7

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HDMI (REAR 1 / SIDE 1 MHL)
HDMI_1 HDMI_2 MHL
VA805
5V_HDMI_2 5V_DET_HDMI_2 5V_HDMI_4 5V_DET_HDMI_4
ESD_HDMI2
R808
HDMI-2
10K R814
HPD4
33
SHIELD ESD_HDMI2
R803 GND VA808
C HDMI-2
20 R809 R815 100
1K 10K 20
Q800 B DDC_SDA_4
MMBT3904(NXP) HPD2
19 HP_DET R816 100
19 DDC_SCL_4
R802 E R810 100 HDMI-2
VA802 DDC_SDA_2 5V R812
18 1.8K 18
ESD_HDMI1 VA809 VA810
R805

3.3K

R811 100 1.8K


VA800 DDC_SCL_2 GND HDMI-2
R813
ESD_HDMI2 ESD_HDMI2
17 17 3.3K
HDMI-2
VA803 VA804 16 DDC_DATA
16 ESD_HDMI1_VARISTOR
ESD_HDMI1 ESD_HDMI1
15 DDC_CLK HDMI_CEC
15 VA811
HDMI_ARC NC ESD_HDMI2
14 14
HDMI_CEC
13 CE_REMOTE
13
EAG59023302

EAG62611204

D803 12 CK-
12
1 10 D805
CK-_HDMI2
11 CK_GND 1 10
11 CK-_HDMI4
CK+ 2 9
10 CK+_HDMI2
10
CK+ 2 9
CK+_HDMI4
D0- 3 8
9
9
D0- 3 8
D0_GND 4 7
8 D0-_HDMI2
8
D0_GND 4 7
D0-_HDMI4
D0+ 5 6
7 D0+_HDMI2
7
D0+ 5 6
D1- D0+_HDMI4
6 ESD_HDMI1_IP4294 BODY_SHIELD
D1-
6 ESD_HDMI2_IP4294
D1_GND IP4294CZ10-TBR
5 20
D1_GND IP4294CZ10-TBR
19
HOT_PLUG_DETECT 5
D1+ D804 18
VDD[+5V]

4 17
D1+ D806
1 10 D1-_HDMI2
16
DDC/CEC_GND

SDA
4
3
D2-
15

14
SCL

RESERVED
D2-
1 10
2 9 D1+_HDMI2
13

12
CEC
3 D1-_HDMI4
2
D2_GND 11
TMDS_CLK-

TMDS_CLK_SHIELD

D2_GND
2 9
3 8 10

9
TMDS_CLK+

TMDS_DATA0- 2 D1+_HDMI4
1
D2+ 8

7
TMDS_DATA0_SHIELD

D2+
3 8
4 7 D2-_HDMI2
6
TMDS_DATA0+

TMDS_DATA1-
1
5

4
TMDS_DATA1_SHIELD

TMDS_DATA1+
4 7
VA801 5 6 D2+_HDMI2
3

2
TMDS_DATA2- D2-_HDMI4
ESD_HDMI1_VARISTOR 1
TMDS_DATA2_SHIELD

TMDS_DATA2+ 5 6
JK800 D2+_HDMI4
ESD_HDMI1_IP4294 JK801-*1 JK801 ESD_HDMI2
VA800-*1 DAADR019A HDMI-2 VA806
IP4294CZ10-TBR ESD_HDMI2_IP4294
1uF HDMI-2_EMI_FOOSUNG
10V IP4294CZ10-TBR
ESD_HDMI1_CAP MHL_CD_SENSE
VA801-*1
1uF C800
10V VA807 0.047uF R817
5.6V 25V 300K
ESD_HDMI1_CAP
OPT
MHL Spec
HDMI-2 HDMI-2

D803-*1 D804-*1 D805-*1 D806-*1

TMDS_CH1- NC_4 TMDS_CH1- NC_4 TMDS_CH1- NC_4 TMDS_CH1- NC_4

CEC TMDS_CH1+

GND_1
1

2
10

9
NC_3

GND_2
TMDS_CH1+

GND_1
1

2
10

9
NC_3

GND_2
TMDS_CH1+

GND_1
1

2
10

9
NC_3

GND_2
TMDS_CH1+

GND_1
1

2
10

9
NC_3

GND_2
3 8 3 8 3 8 3 8

TMDS_CH2- NC_2 TMDS_CH2- NC_2 TMDS_CH2- NC_2 TMDS_CH2- NC_2


4 7 4 7 4 7 4 7

TMDS_CH2+ NC_1 TMDS_CH2+ NC_1 TMDS_CH2+ NC_1 TMDS_CH2+ NC_1


R804 5 6 5 6 5 6 5 6

100
HDMI_CEC CEC_REMOTE_S7 ESD_HDMI1_IP4283 ESD_HDMI1_IP4283 ESD_HDMI2_IP4283 ESD_HDMI2_IP4283
IP4283CZ10-TBA IP4283CZ10-TBA IP4283CZ10-TBA IP4283CZ10-TBA

D803-*2 D804-*2 D805-*2 D806-*2


1 10 1 10 1 10 1 10
5V_HDMI_4 +5V_Normal 2 9 2 9 2 9 2 9
5V_HDMI_2 +5V_Normal +3.5V_ST
3 8 3 8 3 8 3 8
4 7 4 7 4 7 4 7
A1

A2

A1

A2
A1

A2

5 6 5 6 5 6 5 6
MMBD6100 MMBD6100
MMBD6100 D801 D802
D800 ESD_HDMI1_SEMTECH ESD_HDMI1_SEMTECH ESD_HDMI2_SEMTECH ESD_HDMI2_SEMTECH
C

RCLAMP0524PA RCLAMP0524PA RCLAMP0524PA RCLAMP0524PA


C

R800 R801 R806 R807


2.7K 2.7K
2.7K 2.7K
DDC_SDA_4
DDC_SDA_2

DDC_SCL_4
DDC_SCL_2

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013/08/15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
HDMI_R1_S1 8
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

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SPDIF

SPDIF OPTIC JACK


+3.3V_Normal
5.15 Mstar Circuit Application

JK1001
JST1223-001

GND
1

Fiber Optic

VCC
2

VINPUT
3

SPDIF_OUT
4

SPDIF_CAP_68pF SPDIF_CAP_47pF
C1001 C1002 C1002-*1
FIX_POLE

OPT 1uF 68pF 47pF


10V 50V 50V

ESD Ready

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_L14 2013/05/15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SPDIF 10

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+1.5V_DDR +1.5V_DDR Option : Ripple Check !!!
R12011K1%

R1205 1K 1% R1204 1K 1%

+1.5V_DDR +1.5V_DDR
DDR_EXT

DDR_EXT
C1202 1000pF

A-MVREFDQ A-MVREFCA
1K1%

C1201 0.1uF

C1213 0.1uF

C12141000pF

10uF 10V

C1219

C1220

C1221

C1222

C1223
DDR_EXT

DDR_EXT

DDR_EXT

DDR_EXT

0.1uF

0.1uF

0.1uF
C1217

C1218

C1224
DDR_EXT

DDR_EXT

C1216

1uF

1uF

1uF

1uF

1uF
R1202

OPT OPT OPT OPT OPT OPT OPT OPT


OPT

CLose to DDR3 CLose to Saturn7M IC

DDR_1600_1G_HYNIX
IC1201 M1A_256M M1A_128M
H5TQ1G63EFR-PBC IC101 IC101-*1
DDR_1600_1G_SS DDR_1600_2G_HYNIX_OLD DDR_1600_2G_HYNIX_NEW LGE2132(M1A_256M) LGE2131(M1A_128M)
EAN61829003
IC1201-*1 IC1201-*2 IC1201-*3
M8 N3
K4B1G1646G-BCK0 H5TQ2G63DFR-PBC H5TQ2G63FFR-PBC A-MVREFCA VREFCA A0 A-MA0
EAN61836301 EAN61829203 EAN61829204 P7
A1 A-MA1 E11 E11
N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 N3
A0 VREFCA
M8 P3 A-MA0 B_DDR3_A[0] B_DDR3_A[0]
P7
A1
P7
A1
P7
A1 A2 A-MA2 F12 F12
P3
A2
P3
A2
P3
A2 H1 N2 A-MA1 B_DDR3_A[1] B_DDR3_A[1]
N2
A3 VREFDQ
H1 N2
A3 VREFDQ
H1 N2
A3 VREFDQ
H1 A-MVREFDQ VREFDQ A3 A-MA3 D10 D10
P8
A4
P8
A4
P8
A4 P8 A-MA2 B_DDR3_A[2] B_DDR3_A[2]
P2
A5
P2
A5
P2
A5 A4 A-MA4 B10 B10
R8
A6 ZQ
L8 R8
A6 ZQ
L8 R8
A6 ZQ
L8
DDR_EXT P2 A-MA3 B_DDR3_A[3] B_DDR3_A[3]
R2
A7
R2
A7
R2
A7 R1203 A5 A-MA5 E15 E15
T8
A8
T8
A8
T8
A8 L8 R8 A-MA4 B_DDR3_A[4] B_DDR3_A[4]
R3
A9 VDD_1
B2 R3
A9 VDD_1
B2 R3
A9 VDD_1
B2
ZQ A6 A-MA6 B11 B11
L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9 L7
A10/AP VDD_2
D9
240 R2 A-MA5 B_DDR3_A[5] B_DDR3_A[5]
R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 R7
A11 VDD_3
G7 +1.5V_DDR A7 A-MA7 F14 F14
N7
A12/BC VDD_4
K2 N7
A12/BC VDD_4
K2 N7
A12/BC VDD_4
K2 1% T8 A-MA6 B_DDR3_A[6] B_DDR3_A[6]
T3
A13 VDD_5
K8 T3
A13 VDD_5
K8 T3
A13 VDD_5
K8
A8 A-MA8 C11 C11
VDD_6
N1
VDD_6
N1
VDD_6
N1 B2 R3 A-MA7 B_DDR3_A[7] B_DDR3_A[7]
M7
NC_5 VDD_7
N9 M7
NC_5 VDD_7
N9 M7
NC_5 VDD_7
N9
VDD_1 A9 A-MA9 D14 D14
DDR_EXT 10V C1203 D9 L7 A-MA8
R1 R1 R1
VDD_8 VDD_8 VDD_8 10uF B_DDR3_A[8] B_DDR3_A[8]
M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9 M2
BA0 VDD_9
R9
VDD_2 A10/AP A-MA10 A12 A12
N8
BA1
N8
BA1
N8
BA1 DDR_EXT C1204 0.1uF G7 R7 A-MA9 B_DDR3_A[9] B_DDR3_A[9]
M3
BA2
M3
BA2
M3
BA2 VDD_3 A11 A-MA11 F16 F16
VDDQ_1
A1
VDDQ_1
A1
VDDQ_1
A1
DDR_EXT C1205 0.1uF K2 N7 A-MA10 B_DDR3_A[10] B_DDR3_A[10]
J7
CK VDDQ_2
A8 J7
CK VDDQ_2
A8 J7
CK VDDQ_2
A8
VDD_4 A12/BC A-MA12 D13 D13
K7
CK VDDQ_3
C1 K7
CK VDDQ_3
C1 K7
CK VDDQ_3
C1
DDR_EXT C1206 0.1uF K8 T3 A-MA11 B_DDR3_A[11] B_DDR3_A[11]
K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9 K9
CKE VDDQ_4
C9
VDD_5 NC_7 A-MA13 D15 D15
VDDQ_5
D2
VDDQ_5
D2
VDDQ_5
D2
DDR_EXT C1207 0.1uF N1 A-MA12 B_DDR3_A[12] B_DDR3_A[12]
L2
CS VDDQ_6
E9 L2
CS VDDQ_6
E9 L2
CS VDDQ_6
E9
VDD_6 C12 C12
K1
ODT VDDQ_7
F1 K1
ODT VDDQ_7
F1 K1
ODT VDDQ_7
F1
DDR_EXT C1208 0.1uF N9 M7 A-MA13 B_DDR3_A[13] B_DDR3_A[13]
J3
RAS VDDQ_8
H2 J3
RAS VDDQ_8
H2 J3
RAS VDDQ_8
H2
VDD_7 NC_5 E13 E13
K3
CAS VDDQ_9
H9 K3
CAS VDDQ_9
H9 K3
CAS VDDQ_9
H9
DDR_EXT C1209 0.1uF R1 A-MA14 B_DDR3_A[14] B_DDR3_A[14]
L3 L3 L3
WE WE WE VDD_8
NC_1
J1
NC_1
J1
NC_1
J1
DDR_EXT C1210 0.1uF R9 M2
T2 J9 T2 J9 T2 J9
VDD_9 BA0 A-MBA0 A-MCK A9 A9
1%
DDR_EXT DDR_EXT

RESET NC_2 RESET NC_2 RESET NC_2


R1207

NC_3
L1
NC_3
L1
NC_3
L1
DDR_EXT C1211 0.1uF N8 A-MBA0 B_DDR3_BA[0] B_DDR3_BA[0]
NC_4
L9
NC_4
L9
NC_4
L9
BA1 A-MBA1 D16 D16
F3 T7 F3 T7 F3 T7
C1212 0.1uF M3 A-MBA1 B_DDR3_BA[1] B_DDR3_BA[1]
56

G3
DQSL NC_6
G3
DQSL NC_6
G3
DQSL NC_6
DDR_EXT BA2 A-MBA2 DDR_EXT A10 A10
DQSL DQSL DQSL
A1 C1215 A-MBA2 B_DDR3_BA[2] B_DDR3_BA[2]
C7 A9 C7 A9 C7 A9
DQSU VSS_1 DQSU VSS_1 DQSU VSS_1 VDDQ_1
A8 J7
1%

B7 B3 B7 B3 B7 B3
R1208

DQSU VSS_2 DQSU VSS_2 DQSU VSS_2


VSS_3
E1
VSS_3
E1
VSS_3
E1
VDDQ_2 CK 0.01uF C13 C13
E7
DML VSS_4
G8 E7
DML VSS_4
G8 E7
DML VSS_4
G8 C1 K7 50V A-MCK B_DDR3_MCLK B_DDR3_MCLK
B13 B13
56

D3 J2 D3 J2 D3 J2
DMU VSS_5 DMU VSS_5 DMU VSS_5 VDDQ_3 CK
VSS_6
J8
VSS_6
J8
VSS_6
J8 C9 K9 A-MCKB B_DDR3_MCLKZ B_DDR3_MCLKZ
E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1 E3
DQL0 VSS_7
M1
VDDQ_4 CKE A-MCKE E17 E17
F7
DQL1 VSS_8
M9 F7
DQL1 VSS_8
M9 F7
DQL1 VSS_8
M9 D2 A-MCKE B_DDR3_MCLKE B_DDR3_MCLKE
F2
DQL2 VSS_9
P1 F2
DQL2 VSS_9
P1 F2
DQL2 VSS_9
P1
VDDQ_5 A-MCKB
F8
DQL3 VSS_10
P9 F8
DQL3 VSS_10
P9 F8
DQL3 VSS_10
P9 E9 L2
H3
DQL4 VSS_11
T1 H3
DQL4 VSS_11
T1 H3
DQL4 VSS_11
T1
VDDQ_6 CS A/B_DDR3_CS B8 B8
H8
DQL5 VSS_12
T9 H8
DQL5 VSS_12
T9 H8
DQL5 VSS_12
T9 F1 K1 A-MODT B_DDR3_ODT B_DDR3_ODT
G2
DQL6
G2
DQL6
G2
DQL6 VDDQ_7 ODT A-MODT C8 C8
H7
DQL7
H7
DQL7
H7
DQL7 H2 J3 A-MRASB B_DDR3_RASZ B_DDR3_RASZ
VSSQ_1
B1
VSSQ_1
B1
VSSQ_1
B1
VDDQ_8 RAS A-MRASB +1.5V_DDR B9 B9
D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9 D7
DQU0 VSSQ_2
B9 H9 K3 A-MCASB B_DDR3_CASZ B_DDR3_CASZ
C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1 C3
DQU1 VSSQ_3
D1
VDDQ_9 CAS A-MCASB DDR_EXT D11 D11
L3 A-MWEB
A-MDQSU
A-MDQSL

C8 D8 C8 D8 C8 D8
B_DDR3_WEZ B_DDR3_WEZ
A-MWEB R1206
DQU2 VSSQ_4 DQU2 VSSQ_4 DQU2 VSSQ_4
E2 E2 E2
C2
DQU3 VSSQ_5
C2
DQU3 VSSQ_5
C2
DQU3 VSSQ_5 WE
A7
DQU4 VSSQ_6
E8 A7
DQU4 VSSQ_6
E8 A7
DQU4 VSSQ_6
E8 J1
A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9 A2
DQU5 VSSQ_7
F9
NC_1 10K F10 F10
B8 G1 B8 G1 B8 G1 J9 T2 A-MRESETB B_RESET B_RESET
A-MDQSUB
A-MDQSLB

DQU6 VSSQ_8 DQU6 VSSQ_8 DQU6 VSSQ_8


A3
DQU7 VSSQ_9
G9 A3
DQU7 VSSQ_9
G9 A3
DQU7 VSSQ_9
G9
NC_2 RESET A-MRESETB
L1
NC_3 D12 D12
L9 A/B_DDR3_CS B_DDR3_CS0 B_DDR3_CS0
NC_4
T7 F3
A-MA14 NC_6 DQSL A-MDQSL A19 A19
G3 B_DDR3_DQSL B_DDR3_DQSL
DQSL A-MDQSLB B18 B18
B_DDR3_DQSU B_DDR3_DQSU
A9 C7
VSS_1 DQSU A-MDQSU C16 C16
B3 B7 A-MDML B_DDR3_DQML B_DDR3_DQML
VSS_2 DQSU A-MDQSUB D21 D21
E1 A-MDMU B_DDR3_DQMU B_DDR3_DQMU
VSS_3
G8 E7
VSS_4 DML A-MDML C18 C18
J2 D3 B_DDR3_DQSBL B_DDR3_DQSBL
VSS_5 DMU A-MDMU C17 C17
J8 B_DDR3_DQSBU B_DDR3_DQSBU
VSS_6
M1 E3
VSS_7 DQL0 A-MDQL0 A20 A20
M9 F7 A-MDQL0 B_DDR3_DQL[0] B_DDR3_DQL[0]
VSS_8 DQL1 A-MDQL1 A16 A16
P1 F2 A-MDQL1 B_DDR3_DQL[1] B_DDR3_DQL[1]
VSS_9 DQL2 A-MDQL2 C19 C19
P9 F8 A-MDQL2 B_DDR3_DQL[2] B_DDR3_DQL[2]
VSS_10 DQL3 A-MDQL3 C15 C15
T1 H3 A-MDQL3 B_DDR3_DQL[3] B_DDR3_DQL[3]
VSS_11 DQL4 A-MDQL4 C20 C20
T9 H8 A-MDQL4 B_DDR3_DQL[4] B_DDR3_DQL[4]
VSS_12 DQL5 A-MDQL5 C14 C14
G2 A-MDQL5 B_DDR3_DQL[5] B_DDR3_DQL[5]
DQL6 A-MDQL6 B21 B21
H7 A-MDQL6 B_DDR3_DQL[6] B_DDR3_DQL[6]
DQL7 A-MDQL7 B15 B15
B1 A-MDQL7 B_DDR3_DQL[7] B_DDR3_DQL[7]
VSSQ_1 F18 F18
B9 D7 A-MDQU0 B_DDR3_DQU[0] B_DDR3_DQU[0]
VSSQ_2 DQU0 A-MDQU0 D19 D19
D1 C3 A-MDQU1 B_DDR3_DQU[1] B_DDR3_DQU[1]
VSSQ_3 DQU1 A-MDQU1 D17 D17
D8 C8 A-MDQU2 B_DDR3_DQU[2] B_DDR3_DQU[2]
VSSQ_4 DQU2 A-MDQU2 E21 E21
E2 C2 A-MDQU3 B_DDR3_DQU[3] B_DDR3_DQU[3]
VSSQ_5 DQU3 A-MDQU3 E19 E19
E8 A7 A-MDQU4 B_DDR3_DQU[4] B_DDR3_DQU[4]
VSSQ_6 DQU4 A-MDQU4 D20 D20
F9 A2 A-MDQU5 B_DDR3_DQU[5] B_DDR3_DQU[5]
VSSQ_7 DQU5 A-MDQU5 D18 D18
G1 B8 A-MDQU6 B_DDR3_DQU[6] B_DDR3_DQU[6]
VSSQ_8 DQU6 A-MDQU6 F20 F20
G9 A3 A-MDQU7 B_DDR3_DQU[7] B_DDR3_DQU[7]
VSSQ_9 DQU7 A-MDQU7
R1209
E9 E9
ZQ ZQ
240
1%

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_S7LR(M1A) 2013/05/20
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. 1_DDR 12

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Serial Flash for SPI boot

+3.5V_ST +3.5V_ST

SPI_FLASH_MACRONIX
OPT IC1300
R1301
+3.5V_ST 4.7K MX25L8006EM2I-12G
C1300
CS# VCC 0.1uF
/SPI_CS 1 8
OPT
R1300
10K SO/SIO1 HOLD#
SPI_SDO 2 7

WP# SCLK
/FLASH_WP 3 6 SPI_SCK
R1302
GND SI/SIO0 33
4 5 SPI_SDI

SPI_FLASH_WINBOND
IC1300-*1
W25Q80BVSSIG

CS VCC
1 8

DO[IO1] HOLD[IO3]
2 7

%WP[IO2] CLK
3 6

GND DI[IO0]
4 5

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_S7LR(M1A) 2013/04/29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. S_FLASH 13

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LVDS_EU

FOR FHD REVERSE(10bit)


[51Pin LVDS Connector] [30Pin LVDS Connector]
(For FHD 60Hz) Change in S7LR
(For HD 60Hz_Normal)
MO_FHD MIRROR Pol-change
P1800
FI-RE51S-HF-J-R1500 RXA4+ RXA0+ RXA0- MO_HD
RXA4- RXA0- RXA0+ P1801
10031HR-30
RXA3+ RXA1+ RXA1-
1
RXA3- RXA1- RXA1+
2
LVDS_SEL 1
RXACK+ RXA2+ RXA2-
3
2
+3.3V_Normal RXACK- RXA2- RXA2+
4 VCOM_SDA 3 VCOM_SDA
RXA2+ RXACK+ RXACK-
5 VCOM_SCL
OPT 4 VCOM_SCL
RXA2- RXACK- RXACK+
6 R1806
3.3K 5
RXA1+ RXA3+ RXA3-
7
6 RXA3+
OPT RXA1- RXA3- RXA3+
8
R1807 7
RXA0+ RXA4+ RXA4- RXA3-
9 10K
8
RXA0- RXA4- RXA4+
10
9 RXACK+
11
10 RXACK-
12 RXA4+ RXB4+ RXB0+ RXB0-
11
13 RXA4- RXB4- RXB0- RXB0+
12 RXA2+
14 RXA3+ RXB3+ RXB1+ RXB1-
13 RXA2-
15 RXA3- RXB3- RXB1- RXB1+
14
16 RXACK+ RXBCK+ RXB2+ RXB2-
15 RXA1+
17 RXACK- RXBCK- RXB2- RXB2+
16 RXA1-
18 RXB2+ RXBCK+ RXBCK-
17
19 RXA2+ RXB2- RXBCK- RXBCK+ LVDS_SEL
18 RXA0+
20 RXA2- RXB1+ RXB3+ RXB3- +3.3V_Normal
19 RXA0-
21 RXB1- RXB3- RXB3+
20
22 RXB0+ RXB4+ RXB4- OPT
RXA1+ 21 R1808
3.3K
23 RXA1- RXB0- RXB4- RXB4+
22
24 RXA0+ 23 OPT
R1809
25 RXA0- 10K
24
26 R1801 0
25 PANEL_VCC
MO_FHD
27

28
FOR FHD REVERSE(8bit) 26
RXB4+ 27
29 RXB4- Change in S7LR 28
30 RXB3+ 29
31 MIRROR Pol-change Shift
RXB3- 30
RXA4+ RXA4+ RXA4- RXA0-
32 RXBCK+
RXA4- RXA4- RXA4+ RXA0+ 31
33 RXBCK-
RXA3+ RXA0+ RXA0- RXA1-
34
RXA3- RXA0- RXA0+ RXA1+
35 RXB2+
RXACK+ RXA1+ RXA1- RXA2-
36 RXB2-
RXACK- RXA1- RXA1+ RXA2+
37
RXA2+ RXA2+ RXA2- RXACK-
38 RXB1+
RXA2- RXA2- RXA2+ RXACK+
39 RXB1-
RXA1+ RXACK+ RXACK- RXA3-
40 RXB0+
RXA1- RXACK- RXACK+ RXA3+
41 RXB0-
RXA0+ RXA3+ RXA3- RXA4-
EU pin assign is different from NON EU.
42 R1802 0
MO_FHD
R1803 0 RXA0- RXA3- RXA3+ RXA4+
Because of position of HD wafer.
43
MO_FHD
44

45 RXB4+ RXB4+ RXB4- RXB0-


V-COM I2C
46 RXB4- RXB4- RXB4+ RXB0+
PANEL_VCC +3.3V_Normal
47 RXB3+ RXB0+ RXB0- RXB1- URSA/VCOM_SCL

48 RXB3- RXB0- RXB0+ RXB1+ URSA/VCOM_SDA

49 C1800 RXBCK+ RXB1+ RXB1- RXB2-


VCOM_I2C_PULL_UP VCOM_I2C_PULL_UP
0.1uF
50 16V RXBCK- RXB1- RXB1+ RXB2+ R1810 R1811
2K 2K
51 RXB2+ RXB2+ RXB2- RXBCK-
VCOM_I2C
RXB2- RXB2- RXB2+ RXBCK+ R1804
52 0
RXB1+ RXBCK+ RXBCK- RXB3- VCOM_SCL URSA/VCOM_SCL
R1805
0
RXB1- RXBCK- RXBCK+ RXB3+ VCOM_SDA URSA/VCOM_SDA
VCOM_I2C
RXB0+ RXB3+ RXB3- RXB4-

RXB0- RXB3- RXB3+ RXB4+

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013.07.15
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. LVDS_EU 18

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CI Region * Option name of this page : CI_SLOT
(because of Hong Kong)

CI SLOT
+5V_CI_ON
CI_DATA[0-7]
CI TS INPUT
CI_DATA[0-7]

+5V_Normal AR1903 33
C1903 FE_TS_DATA[7]
CI_MDI[7]
10uF FE_TS_DATA[6]
10V CI_MDI[6]

FE_TS_DATA[0-7]
R1908 FE_TS_DATA[5]
CI_MDI[5]
10K FE_TS_DATA[4]
CI_SLOT_JACK CI_MDI[4]
/CI_CD1 P1900
10067972-000LF
AR1904 33 FE_TS_DATA[3]
R1914 35 1 CI_MDI[3]
100 CI_DATA[3] FE_TS_DATA[2]
36 2 CI_MDI[2] FE_TS_DATA[1]
AR1900 CI_DATA[4]
CI_DATA[0-7]

33 37 3 CI_MDI[1] FE_TS_DATA[0]
CI_DATA[5] R1919
CI_TS_DATA[4] 38 4 10K CI_MDI[0]
CI_DATA[6]
CI_TS_DATA[5] 39 5
CI_DATA[7] FE_TS_DATA[0-7]
CI_TS_DATA[6] 40 6
R1917 R1921 33
CI_TS_DATA[7] 41 7 47 CI_MISTRT FE_TS_SYNC
CI_ADDR[10] /PCM_CE R1922 33
42 8 CI_MIVAL_ERR FE_TS_VAL_ERR
R1910 10K R1923 100
43 9 CI_OE CI_MCLKI FE_TS_CLK
CI_ADDR[11]
CI_IORD 44 10 +5V_Normal
CI_ADDR[9]
CI_IOWR 45 11
CI_ADDR[8]
46 12 R1920
CI_ADDR[13] 10K
CI_MDI[0] 47 13
CI_ADDR[14]
CI_MDI[1] 48 14
CI_MDI[2] 49 15 CI_WE
50 16 R1918 100
CI_MDI[3] /PCM_IRQA
51 17

GND
C1901
0.1uF
52
53
18
19
C1904
0.1uF
C1905
0.1uF
CI HOST I/F
CI_MDI[4]
GND
CI_MDI[5] 54 20
+5V_Normal CI_ADDR[12]
CI_MDI[6] 55 21 CLOSE TO MSTAR
CI_ADDR[7]
R1900 CI_MDI[7] 56 22 GND +3.3V_Normal
10K R1911 10K CI_ADDR[6]
57 23
R1903 CI_ADDR[5]
47 58 24
PCM_RST CI_ADDR[4]
R1904 47 CI_DET
/PCM_WAIT 59 25 IC1902
CLOSE TO MSTAR CI_ADDR[3]
REG 60 26 C1906
R1905 100 CI_ADDR[2]
CI_TS_CLK 61 27 0.1uF
R1906 33 CI_ADDR[1] 1OE BUFFER_ORG VCC 16V
CI_TS_VAL 62 28 1 20
R1907 33 CI_ADDR[0]
CI_TS_SYNC 63 29
CI_DATA[0]
64 30 1A1 2OE
AR1901 33 CI_DATA[1] 2 19
65 31 CI_ADDR[0-14] PCM_A[0]
CI_TS_DATA[0] CI_DATA[2] AR1902 AR1910
66 32 100
CI_TS_DATA[1] 2Y4 1Y1 100
67 33 3 18
CI_TS_DATA[2] CI_ADDR[7] CI_ADDR[0]
68 34
CI_TS_DATA[3] CI_ADDR[6] CI_ADDR[1]
G2 69 G1 CI_ADDR[5] 1A2 2A4 CI_ADDR[2]
PCM_A[1] 4 17 PCM_A[7]
R1912 CI_ADDR[4] CI_ADDR[3]
100
/CI_CD2 2Y3 1Y2
TC74LCX244FT

+5V_Normal GND 5 16

GND 1A3 2A3


PCM_A[2] 6 15 PCM_A[6]
C1900
2pF
R1909
50V 2Y2 1Y3
10K GND 7 14
CLOSE TO MSTAR
1A4 2A2
PCM_A[3] 8 13 PCM_A[5]

2Y1 1Y4
CI_MISTRT 9 12
CI_MIVAL_ERR
GND 2A1
10 11 PCM_A[4]
CI_MCLKI

CI DETECT +3.3V_Normal
OR_GATE_CI_PHILIPS
IC1900
74LVC1G32GW +3.3V_Normal
B 1 5 VCC
/CI_CD2
A 2
/CI_CD1 AR1905 33
GND 3 4 Y R1913 CI_DATA[0] PCM_D[0]
10K CI_DATA[1] PCM_D[1]
CI_DATA[0-7]

CI_DATA[2] PCM_D[2]
OR_GATE_CI_TI OR_GATE_CI_TOSHIBA R1924 CI_DATA[3] PCM_D[3]
IC1900-*1 IC1900-*2 0
SN74LVC1G32DCKR TOSHIBA ELECTRONICS KOREA CORPORATION
CI_DET
IC1902-*1
PCM_D[0-7]

A VCC IN_B VCC


1 5 1 5
/PCM_CD AR1906 33
B IN_A R1915 CI_DATA[4] PCM_D[4] 74LCX244FT
2 2
47 CI_DATA[5] PCM_D[5]
GND Y GND OUT_Y
3 4 3 4
CI_DATA[6] PCM_D[6]
1OE BUFFER_CI VCC
CI_DATA[7] PCM_D[7] 1 20

1A1 2OE
2 19
PCM_D[0-7]
CI_DATA[0-7] 2Y4 1Y1
CI POWER ENABLE CONTROL 3 18

1A2 2A4
4 17
AR1908 33
CI_ADDR[8] PCM_A[8] 2Y3 1Y2
CI_ADDR[9] PCM_A[9] 5 16
+5V_Normal IC1901
AP2151WG-7 +5V_CI_ON CI_ADDR[10] PCM_A[10]
L1900 CI_ADDR[11] PCM_A[11] 1A3 2A3
6 15
BLM18PG121SN1D
IN OUT
5 1
2Y2 1Y3
7 14
GND AR1909 33
2 CI_ADDR[12] PCM_A[12]
R1916 1A4 2A2
C1902 8 13
100K CI_ADDR[13] PCM_A[13]
R1902 1uF
100 EN FLG 10V CI_ADDR[14] PCM_A[14]
PCM_5V_CTL 4 3
/PCM_REG 2Y1 1Y4
REG 9 12
R1901
10K
GND 2A1
10 11
AR1907 33
CI_OE /PCM_OE
CI_WE /PCM_WE
CI_IORD /PCM_IORD
CI_IOWR /PCM_IOWR

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013.04.29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. PCMCI 19

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ETHERNET
* H/W option : ETHERNET

JK2100
RJ45VT-01SN002

1
1
EPHY_TP
ETHERNET

2
2

3
3
EPHY_TN

4
4
EPHY_RP

5
5

6
6
EPHY_RN

7
7

8
8

ETHERNET ETHERNET
C2105 C2104
0.01uF 0.01uF
50V 50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013.04.29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
LAN 21
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

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DVB-S2 LNB Part Allegro
(Option:LNB)

Input trace widths should be sized to conduct at least 3A

Ouput trace widths should be sized to conduct at least 2A

3A
+12V_LNB

2A LNB_SX34
D2705-*1
40V
LNB
Max 1.3A
L2702
SP-7850_15
D2705 15uH
LNB LNB_SMAB34
D2703 40V 3.5A

30V
LNB
C2708
LNB LNB LNB 10uF
LNB
C2703 C2704 C2705 C2706 25V
0.01uF 10uF 10uF 10uF
50V 25V 25V 25V

close to Boost pin(#1)


A_GND A_GND
A_GND

close to VIN pin(#15)


[EP]GND

LNB
LNB C2709
BOOST

GNDLX
NC_3

NC_2

C2707 0.1uF
50V
LX

0.1uF
20

19

18

17

16

LNB
D2702 VCP 1 15 VIN
close to TUNER MBR230LSFT1G
LNB
THERMAL
GND
LNB_OUT 2 21 14
LNB
30V NC_1 VREG R2703
3 13 36K
LNB
LNB LNB LNB TDI ISET 1/16W 1%
R2702 C2712 LNB_SMAB34 4 IC2701 12
LNB LNB LNB LNB C2713
C2714 C2701 C2702 D2701
2.2K 0.22uF 0.1uF D2704 TDO A8303SESTR-T TCAP
1W 25V 50V 40V 5 11
18pF 18pF 33pF
10

LNB
6

LNB_SX34 C2710
D2704-*1 0.1uF
IRQ

SCL

SDA

ADD

TONECTRL

40V LNB
C2711
Close to Tuner 0.22uF
Surge protectioin

A_GND A_GND

R2706
0

LNB LNB
R2704 R2705
33 33

Caution!! need isolated GND

R2701
0
DEMOD_SCL

DEMOD_SDA

LNB_TX

A_GND

Max 1.3A

+12V +12V_LNB

LNB
L2701
BLM18PG121SN1D

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013.04.29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
LNB 27
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

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SCART_COMPONENT
COMPONENT SCART AMP

+12V

JK2802
PPJ245N2-01
R2811 EU
6E [RD2]E-LUG 10K C2808
COMP2_R_IN
VA2804 R2803 R2816 IC2801 0.1uF
[RD2]O-SPRING 5.6V 470K 12K 50V
5E AZ4580MTR-E1
OPT
R2810 EU
4E [RD2]CONTACT 10K R2831
COMP2_L_IN 2.2K OUT1 8 VCC
R2815 DTV/MNT_L_OUT 1
[WH]O-SPRING
VA2803 R2802
470K 12K EU EU EU
5D 5.6V +3.3V_Normal EU
C2804 R2834 R2844
OPT OPT 33K IN1- 7 OUT2 2.2K
R2817 R2818 10uF R2832 2
[RD1]CONTACT 10K 1K 16V DTV/MNT_R_OUT
4C 470K EU
COMP2_DET R2841 EU
EU IN1+ IN2- 33K C2812
[RD1]O-SPRING VA2816 EU 3 6 OPT 10uF
5C R2836
COMP2_Pr+ 5.6V C2807 10K EU R2843 16V
VA2802 R2801 33pF 470K
OPT R2839
7C [RD1]E-LUG-S 5.5V 75 VEE 5 IN2+ 10K
4 EU
ESD_COMP C2810
[BL]O-SPRING EU 33pF
5B
COMP2_Pb+ R2835
VA2801 R2800 5.6K EU
[GN/YL]CONTACT 5.5V +3.3V_Normal SCART1_Lout R2840
4A 75 5.6K
ESD_COMP SCART1_Rout
R2812 R2814 330pF 220K
[GN/YL]O-SPRING 1K C2806 R2833
5A 10K EU EU
AV_CVBS_DET EU EU
VA2800 OPT R2842 C2811
C2800 220K 330pF
6A [GN/YL]E-LUG 5.6V
OPT 0.1uF
16V

COMP2_Y+/AV_CVBS_IN
R2804 CLOSE TO MSTAR
D2800-*1 D2800 75
ESD_COMP_ZENER_ROHM
ESD_COMP_ZENER_KEC CLOSE TO MSTAR
D2801-*1 D2801
ESD_COMP_ZENER_KEC ESD_COMP_ZENER_ROHM

FULL SCART +3.3V_Normal [SCART AUDIO MUTE] +3.5V_ST

R2819 DTV/MNT_L_OUT SCART_MUTE


10K R2837 SCART_MUTE
2K R2845
R2820 1K SCART_MUTE 10K
SC1/COMP1_DET Q2802
VA2815 EU MMBT3904(NXP)
5.6V R2850 1K
AV2_CVBS_DET
OPT AV2
SCART1_MUTE
SCART_MUTE
DTV/MNT_R_OUT R2838 SCART_MUTE
2K C2809
SCART_MUTE 0.1uF
Q2803
SC1/AV2_CVBS_IN MMBT3904(NXP)
EU
R2813 OPT
C2801
75 47pF
AV_DET 50V
22 VA2807
COM_GND 5.5V
ESD_SCART
21
SYNC_IN EU
L2800 AV2
20 CM2012FR22KT
SYNC_OUT 220nH JK2803
EU EU DTV/MNT_VOUT
19 PPJ231-01
SYNC_GND2 VA2808 EU C2815 C2816
VA2814 R2821 R2851
18 20V 5.6V 75 68pF 68pF 4 10K
SYNC_GND1 ESD_SCART 50V 50V EU AV2_R_IN_A AV2_R_IN_A AV2_R_IN
R2827 R2846 AV2
17 22 0
RGB_IO 5 AV2 VA2818 R2854 C2817 R2853
SC1_FB AV2_L_IN_A 1000pF 12K
16 5.6V 470K AV2
R_OUT AV2_LR_ZENER AV2 50V
7 OPT
15 SC1_R+/COMP1_Pr+
RGB_GND ESD_SCART
VA2810 R2807 R2852
14 75 EU 8
R_GND 20V 10K
R2822 AV2_L_IN_A AV2_L_IN
13 75 R2849 AV2
D2B_OUT 6 R2848 0
0 AV2 R2855
12 EU VA2819 R2856 C2818 12K
G_OUT 5.6V 470K 1000pF AV2
AV2_LR_ZENER AV2 50V
11 SC1_G+/COMP1_Y+ OPT
D2B_IN VA2811 R2808
10 20V 75
G_GND ESD_SCART EU
9 R2824
ID 15K R2847
0
8 SC1_ID AV2
B_OUT EU AV2_CVBS_DET
7 SC1_B+/COMP1_Pb+ R2828
AUDIO_L_IN VA2812 VA2817 VA2820
20V 3.9K 5.6V
20V R2805 OPT
6 75 ESD_SCART
B_GND ESD_SCART
5
AUDIO_GND EU
4
AUDIO_L_OUT R2826
10K
3 SC1/COMP1_L_IN
AUDIO_R_IN R2823
0
2 EU R2806 R2829
AUDIO_R_OUT VA2813 470K 12K
5.6V
EU

1
ESD_SCART
SC1/AV2_CVBS_IN
AV2_L_IN_A ZD2800-*1 ZD2800 AV2
EU EU C2819
AV2_CVBS_ZENER_KEC AV2_CVBS_ZENER_ROHM R2857 47pF
JK2801 R2825 75
10K ZD2801-*1 ZD2801 50V
PSC008-01 SC1/COMP1_R_IN
1608 AV2
R2858 AV2_CVBS_ZENER_KEC AV2_CVBS_ZENER_ROHM 1%
0 VA2809
EU 5.6V
ESD_SCART R2809 R2830
470K 12K
Size Check !!!
EU

AV2_R_IN_A
AV2
DTV/MNT_L_OUT
EU
VA2806 C2813
5.6V 1000pF
OPT 50V

DTV/MNT_R_OUT
EU
VA2805 C2814
5.6V 1000pF
OPT 50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013.07.24
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. SCART_ COMPONENT 28

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Headphone
*Option : HEAD_PHONE_EU
Close to the Main IC
HEAD_PHONE
L3000
5.6uH HEAD_PHONE
HP_LOUT
HEAD_PHONE C3000 OPT C
C3004 HEAD_PHONE E
10uF C3002 R3002
4.7uF 16V 1000pF Q3002 B Q3004
1K MMBT3904(NXP)
10V 50V MMBT3904(NXP) B OPT HEAD_PHONE
OPT JK3000
+3.5V_ST E +3.3V_Normal
C KJA-PH-0-0177
GND 5
E
OPT OPT HEAD_PHONE
Q3001 R3005
10K L 4
OPT MMBT3906(NXP)
C R3001 B
R3000 3.3K
1K B C DETECT 3
SIDE_HP_MUTE HP_DET
Q3000 R3004
MMBT3904(NXP) 1K
OPT E HEAD_PHONE R 1

HEAD_PHONE
L3001 HEAD_PHONE
5.6uH
HP_ROUT
HEAD_PHONE C3001 OPT HEAD_PHONE C E
C3005 10uF C3003 R3003
4.7uF 16V 1000pF Q3003 B Q3005
1K MMBT3904(NXP) MMBT3904(NXP)
10V 50V B
OPT OPT
E C

Close to the Main IC

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013.04.29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. HEAD_PHONE_EU 30

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L14 TUNER_EU T/C_T2/C/S2_CHINA
TU_I2C Multi option
TU3700 TU3702 TU3703 TU3701
TU_I2C_FILTER
TDJH-G101D TDJM-G105D TDJM-C301D TDJM-G101D RF_SW_OPT
R2603
0
TU_ATSC
C3705-*1
18pF
TU_ATSC R3838-*1
R3716-*1 MLG1005SR27JT
1.8K
RF_SWITCH_CTL TU_ATSC
TUNER_T/C TUNER_AJ_T2 TUNER_CHINA TUNER_T2/C/S2 +3.3V_LNA TU_ATSC R3717-*1 TU_I2C_FILTER
1.8K R3739-*1
C2603 C3707-*1 MLG1005SR27JT
0.1uF 18pF
B1[+3.3V] B1[+3.3V] B1[+3.3V] B1[+3.3V] 16V
RF_SW_OPT
1 1 1 1
C3708 C3714
NC_1 NC_1 RF_SW_CTL NC_1 100pF 0.1uF Close to TUNER
50V 16V
2 2 2 2 +3.3V_TU
IF_AGC AIF_AGC NC_1 AIF_AGC should be guarded by ground
3 3 3 3 C3703 IF_AGC_MAIN TU_NON_ATSC TU_NON_ATSC
0.1uF R3714 R3716 R3717
16V 0
SCL SCL_RF SCL_RF SCL_RF TU_I2C_NON_FILTER
R3738 33
1K 1K
4 4 4 4 TU_SCL

SDA SDA_RF SDA_RF SDA_RF TU_I2C_NON_FILTER


5 5 5 5 C3705 C3707
R3739 33
TU_SDA
TU_NON_ATSC TU_ATSC C3710 C3711 R3726 OPT 0
20pF 20pF 20pF 20pF
IF[P] AIF[P] NC_2 AIF[P] R3709
10
R3709-*1 TU_NON_ATSC TU_NON_ATSC
TU_NON_ATSC TU_NON_ATSC +3.3V_TU
+3.3V_TU
6 6 6 6 0 IF_P_MSTAR CHINA CHINA
CHINA R3732 R3735
CHINA
IF[N] AIF[N] NC_3 AIF[N] R3725
470 R3728
220 220
7 7 7 7 IF_N_MSTAR
82
TU_SIF TU_CVBS
TU_NON_ATSC TU_ATSC E
R3710 R3710-*1 CHINA
NC_2 NC_2 SIF NC_2 10 C3726
E
CHINA Q3701
8 8 8 8 0 Q3700 B MMBT3906(NXP)
0.1uF R3724 B MMBT3906(NXP) C
4.7K
NC_3 NC_3 CVBS NC_3 16V
CHINA
CHINA C
9 9 9 9 R3731 OPT 0

close to TUNER
NC_4 NC_4 NC_4
10 10 10 CHINA
AR3700-*1 47

A1 B1 B2[+3.3V] NC_5 B2[+3.3V] +3.3V_TU


A1 B1 11 11 11 T2_OR_CHINA
C3718
T2_OR_CHINA
C3722
AR3700
100pF 0.1uF 0
47 ERROR ERROR ERROR 50V 16V 1/16W
12 12 12
TU_GND_A

TU_GND_B

FE_TS_ERR CHINA
AR3701-*1 47
FE_TS_CLK
GND_1 GND_1 GND_1 FE_TS_SYNC
SHIELD 13 13 13 FE_TS_VAL
T2
MCLK MCLK MCLK
14 14 14 CHINA
AR3702-*1 47
SYNC SYNC SYNC
15 15 15
VAILD VAILD VALID
16 16 16
AR3701
0 FE_TS_DATA[0-7]
D0 D0 D0 1/16W
TU3700-*1 17 17 17 FE_TS_DATA[0]
FE_TS_DATA[1]
D1 D1 D1 FE_TS_DATA[2]
TDJH-H101F 18 18 18 FE_TS_DATA[3]

T2
D2 D2 D2
TUNER_NTSC 19 19 19
B1[+3.3V] D3 D3 D3
1 20 20 20
AR3702
NC_1 D4 D4 D4 0
1/16W
2 21 21 21 FE_TS_DATA[4]
FE_TS_DATA[5] +3.3V_LNA +3.3V_TU +3.3V_Normal
IF_AGC D5 D5 D5 FE_TS_DATA[6]
3 22 22 22 FE_TS_DATA[7]

T2 L3701 L3704
SCL D6 D6 D6 UBW2012-121F UBW2012-121F
4 23 23 23 C3739 C3706 C3730 C3731 C3733 C3738
22uF 0.1uF 22uF 0.1uF 22uF 0.1uF
SDA D7 D7 D7 10V 16V 10V 16V 10V 16V
5 24 24 24
T2_OR_CHINA
IF[P] RESET_DEMOD RESET_DEMOD RESET_DEMOD R3719 IC3701
6 25 25 25 10
DEMOD_RESET
+3.3V_TU AP7361-Y-13
+1.2V_DEMOD
T2_OR_CHINA T2_OR_CHINA
IF[N] B3[+3.3V] B2[+3.3V] B3[+3.3V] C3716
0.1uF
+3.3V_DEMOD R3723
3.3K EN OUT
7 1 T2_OR_CHINA 5
26 26 26 16V
T2_OR_CHINA
T2_OR_CHINA C3725
C3721 C3723 T2_OR_CHINA
NC_2 SCL_DEMOD SCL_DEMOD SCL_DEMOD T2_OR_CHINA 100pF 0.1uF
1uF
10V
GND
2 T2_OR_CHINA R3737
8 27 27 27 R3711 22
DEMOD_SCL
50V 16V
T2_OR_CHINA
R3733
12K
1
T2_OR_CHINA
C3702 1%
ADJ/NC IN C3737
20pF R1
NC_3 B4[+1.1V] B3[+1.1V] B4[+1.1V] 50V +1.2V_DEMOD 3 4 10uF
9 28 28 28 T2_OR_CHINA 10V
C3713 C3729 T2_OR_CHINA
100pF 0.1uF C3732
T2_OR_CHINA 50V 16V
F22_OUTPUT NC_6 F22_OUTPUT R3707 T2_OR_CHINAT2_OR_CHINA
0.1uF
16V
29 29 29 0
LNB_TX
T2_OR_CHINA
A1 B1 SDA_DEMOD SDA_DEMOD SDA_DEMOD T2_OR_CHINA R3734
A1 B1 30 30 30 R3712 22
DEMOD_SDA
22K
1%
C3704
20pF R2
47 LNB 50V
T2_OR_CHINA Vo=0.8*(1+R1/R2)
31 C3709 LNB_OUT
0.1uF
50V GND seperation for CHINA tuner
A1 B1 A1 B1 GND
TU_GND_A

T2_OR_CHINA
SHIELD A1 B1 A1 B1 32
TU_GND_B

47 47
NON_CHINA

NON_CHINA

NON_CHINA

NON_CHINA

NON_CHINA
NON_CHINA
TU_GND_A

TU_GND_B

TU_GND_A

TU_GND_B

R3708

R3713

R3715

R3718

R3720

R3721

C3712 C3701
1000pF 1000pF
A1 B1 630V
0

630V
CHINA
SHIELD SHIELD A1 B1 CHINA

47
TU_GND_A

TU_GND_B

+3.3V_TU +3.3V_DEMOD
T2_OR_CHINA
L3702
47 BLM18PG121SN1D

T2_OR_CHINA T2_OR_CHINA T2_OR_CHINA


C3724 C3734 C3727
0.1uF 10uF 0.1uF
16V
10V 16V

ERROR & VALID PIN


T2_OR_CHINA
R3736
FE_TS_VAL 0
FE_TS_VAL_ERR
FE_TS_ERR
GPIO must be added.

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013.08.27
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. TUNER_EU 37

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RS-232C 4PIN & MSTAR DEBUG 4PIN

RS-232C 4PIN

RS232C_DEBUG_4P
+3.5V_ST P4000
12507WS-04L

R4001
100 VCC
1
PM_TXD
R4000
100 PM_RXD
2
PM_RXD

GND
3

RM_TXD
4

GND

MSTAR DEBUG 4PIN

MSTAR_DEBUG_4P

P4001
JP_GND1

JP_GND2

JP_GND3

JP_GND4

12505WS-04A00

3 RGB_DDC_SCL

4 RGB_DDC_SDA

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_S7LR(M1A) 2013/04/30
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. RS232C_MSTAR_DEBUG_4P 40

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TP for EU

RF_SWITCH_CTL HDMI_ARC HP_ROUT CI_DET EPHY_RP SENSOR_SCL FRC_RESET


IF_AGC_SEL CK+_HDMI2 HP_LOUT /CI_CD1 EPHY_TN SENSOR_SDA DEMOD_RESET
CK-_HDMI2 SIDE_HP_MUTE /CI_CD2 EPHY_TP
SPDIF_OUT D0+_HDMI2 HP_DET EPHY_RN
AV2_CVBS_DET D0-_HDMI2
5V_DET_HDMI_2 D1+_HDMI2
D1-_HDMI2
D2+_HDMI2
D2-_HDMI2
DDC_SDA_2
DDC_SCL_2
HPD2

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS NC5_M1A 2013/04/29
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
TP_EU 41
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

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manuals search engine LGE Internal Use Only
IR/LED + Digital Eye + Control

+3.5V_ST

R4603 R4604
10K 10K
1% 1%

R4601
100 P4600 OPT
KEY1
OPT 12507WR-10L P4601
C4602 12507WR-08L
0.1uF
16V
R4602 1
100 1
KEY2
OPT
C4603 2
0.1uF 2
+3.5V_ST 16V
3
L4600 3
BLM18PG121SN1D
4
4
R4606
+3.5V_ST C4600 C4601 1.8K
0.1uF 1000pF LED_R/BUZZ 5
16V 50V 5
VA4600
LED_R_Zener
R4600 6
3.3K 6

IR 7
C4604 7
VA4601
100pF IR_Zener
50V 8
8

9 9
+3.3V_Normal

10

Digital Eye Digital Eye OPT 11


R4605 R4607 C4605
1K 1K 18pF
50V
R4608 100
SENSOR_SCL
Digital Eye

R4609 100
SENSOR_SDA
Digital Eye OPT
C4606
18pF
50V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013/09/03
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. IR_EYE_SENSOR 46

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NAND FLASH MEMORY +3.5V_ST PM MODEL OPTION
<CHIP Config>
IC102 (SPI_SDI, PM_LED, PWM_PM)
H27U1G8F2CTR-BC R177
LG-NonOS SB51_ExtSPI 3’b000 51boot from SPI 10K PM_MODEL_OPT_0
LG-OS HEMCU_ExtSPI 3’b001 MIPS boot from SPI LCD - HIGH : LCD
+3.3V_Normal +3.3V_Normal +3.5V_ST PM_MODEL_OPT_0
NC_1 NC_29 R176 - LOW :: PDP
1 NAND_FLASH_1G_HYNIX
48 10K
PDP PM_MODEL_OPT_1
NC_2 NC_28 M1A_256M
2 EAN35669103 47 M1A_128M
- Not Use (Ready) IC101
NC_3 NC_27 PCM_A[0-7] IC101-*1
4.7K

LGE2132(M1A_256M)
4.7K

2.7K

3 46 LGE2131(M1A_128M)
22
NC_4 NC_26 I2C
OPT

OPT

4 45 AR101 +3.3V_Normal
NC_5 I/O7 PCM_A[7]
R115

R117

R165

5 44 U19 D5
RXA4+ LVA4P/TTL_B[0]/HCONV/GPIO170 U19 D5
NC_6 I/O6 PCM_A[6] SAR0/GPIO35 KEY1 LVA4P/TTL_B[0]/HCONV/GPIO170 SAR0/GPIO35
6 43 R140 R141 R144 R145 T20 F8 T20 F8
AR103 R107 R109 1K 1K 2.2K 2.2K RXA4- LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36 KEY2
22 T21 E7 LVA4M/TTL_B[1]/E_O/GPIO171 SAR1/GPIO36
1K 3.9K R/B I/O5 PCM_A[5] LED_R/BUZZ RXA3+ T21 E7
7 42 I2C_SDA LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37 PM_MODEL_OPT_0 LVA3P/TTL_B[2]/FB/GPIO172 SAR2/GPIO37
T19 E6 T19 E6
RE I/O4 PCM_A[4] PM_LED I2C_SCL RXA3- LVA3M/TTL_B[3]/OPT_P/GPIO173 SAR3/GPIO38 PANEL_CTL LVA3M/TTL_B[3]/OPT_P/GPIO173
/F_RB R21 D6 SAR3/GPIO38
8 41 RXACK+ R21 D6
AMP_SDA LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39 SCART1_MUTE LVACKP/TTL_B[4]/MCLK/GPIO174 SAR4/GPIO39
/PF_OE CE NC_25 SPI_SDI R20 R20
9 40 AMP_SCL RXACK- LVACKM/TTL_B[5]/GCLK/GPIO175
/PF_CE0 R19 W10 LVACKM/TTL_B[5]/GCLK/GPIO175
4.7K

4.7K

2.7K

RXA2+ R19 W10


NC_7 NC_24 LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20 MHL_CD_SENSE LVA2P/TTL_B[6]/GST/GPIO176 GPIO_PM[13]/GPIO20
10 39 C102 P20 Y10 P20 Y10
R108 10uF RXA2- LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21 /VBUS_EN
OPT

1K P3 LVA2M/TTL_B[7]/POL/GPIO177 GPIO_PM[14]/GPIO21
OPT
NC_8
11 38
NC_23 10V DIMMING PM_LED/GPIO4 PM_LED
P3
C101 P19 Y3 PM_LED/GPIO4
R116

R118

R121

RXA1+ P19 Y3
0.1uF VCC_1 VCC_2 LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7 POWER_DET LVA1P/TTL_G[0]/EPI0+/GPIO178 GPIO_PM[0]/GPIO7
12 37 N20 Y5 N20 Y5
RXA1- LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17 AMP_MUTE
C103 N21 W11 LVA1M/TTL_G[1]/EPI0-/GPIO179 PM_SPI_SCZ2/GPIO_PM[10]/GPIO17
VSS_1 VSS_2 R157 100 RXA0+ N21 W11
13 36 0.1uF PWM_DIM PWM2 LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22 INV_CTL LVA0P/TTL_G[2]/EPI1+/GPIO180 GPIO_PM[15]/GPIO22
R156 10K N19 D3 N19 D3
NC_9 NC_22 PWM0 RXA0- LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11 POWER_ON/OFF_1
M21 AA3 LVA0M/TTL_G[3]/EPI1-/GPIO181 GPIO_PM[4]/GPIO11
+3.3V_Normal 14 35 R103 10K RXB4+ M21 AA3
PWM3 LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14 RL_ON LVB4P/TTL_G[4]/EPI2+/GPIO182 GPIO_PM[7]/GPIO14
NC_10 NC_21 M20 W5 M20 W5
R105 15 34 RXB4- LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15 /FLASH_WP
NVRAM_RHOM M19 D4 LVB4M/TTL_G[5]/EPI2-/GPIO183 GPIO_PM[8]/GPIO15
1K RXB3+ M19 D4
OPT CLE NC_20 LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200 LED_R/BUZZ LVB3P/TTL_G[6]/EPI3+/GPIO184 PWM_PM/GPIO200
16 33 IC104 L20 L15 L20 L15
AR104
22
AR102 BR24G256FJ-3
RXB3- LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8
Y11
PM_TXD LVB3M/TTL_G[7]/EPI3-/GPIO185 PM_UART_TX/GPIO_PM[1]/GPIO8
ALE I/O3 PCM_A[3] Y11
17 32 PM_UART_RX/GPIO_PM[5]/GPIO12 PM_RXD PM_UART_RX/GPIO_PM[5]/GPIO12
/PF_CE1 +3.3V_Normal EEPROM L19 L19
WE I/O2 PCM_A[2] RXBCK+ LVBCKP/TTL_R[0]/EPI4+/GPIO186
PF_ALE K20 LVBCKP/TTL_R[0]/EPI4+/GPIO186
18 31 A0 VCC RXBCK- K20
LVBCKM/TTL_R[1]/EPI4-/GPIO187 LVBCKM/TTL_R[1]/EPI4-/GPIO187
/PF_WE WP I/O1 PCM_A[1] 1 8 K21 K21
19 30 C105 RXB2+ LVB2P/TTL_R[2]/EPI5+/GPIO188
/PF_WP K19 LVB2P/TTL_R[2]/EPI5+/GPIO188
0.1uF RXB2- K19
R102 R106 NC_11 I/O0 PCM_A[0] LVB2M/TTL_R[3]/EPI5-/GPIO189 LVB2M/TTL_R[3]/EPI5-/GPIO189
3.3K 1K 20 29 A1 WP J21 J21
2 7 RXB1+ LVB1P/TTL_R[4]/EPI6+/GPIO190
J20 LVB1P/TTL_R[4]/EPI6+/GPIO190
NC_12 NC_19 22 RXB1- LVB1M/TTL_R[5]/EPI6-/GPIO191 J20
21 28 J19 LVB1M/TTL_R[5]/EPI6-/GPIO191
A2 A0’h SCL RXB0+ LVB0P/TTL_R[6]/EPI7+/GPIO192 J19
NC_13 NC_18 3 6 R111 22 H20 LVB0P/TTL_R[6]/EPI7+/GPIO192
22 27 I2C_SCL H20
RXB0- LVB0M/TTL_R[7]/EPI7-/GPIO193 LVB0M/TTL_R[7]/EPI7-/GPIO193
NC_14 NC_17
23 26 GND SDA
4 5 R112 22
NC_15 NC_16 I2C_SDA
24 25 C104 C106
8pF 8pF
OPT OPT
EAN62389502

NAND_FLASH_2G_HYNIX NAND_FLASH_1G_TOSHIBA
EAN60708702 EAN61508001 NVRAM_ATMEL
IC102-*1 IC102-*2 IC104-*1
H27U2G8F2CTR TC58NVG0S3ETA0BBBH AT24C256C-SSHL-T M1A_256M M1A_128M
IC101 IC101-*1
A0 VCC LGE2132(M1A_256M) from CI SLOT LGE2131(M1A_128M)
NC_1 NC_29 NC_1 NC_29 1 8
1 48 1 48
NC_2 NC_28 NC_2 NC_28 A1 WP CI_TS_CLK
2 47 2 47 2 7 CI_TS_DATA[0-7]
NC_3 NC_27 NC_3 NC_27 Y1 V10 Y1 V10
3 46 3 46 GPIO78 TS0CLK/GPIO92 CI_TS_DATA[0] CI_TS_SYNC GPIO78 TS0CLK/GPIO92
A2 SCL W4 T14 W4 T14
3 6 CI_TS_VAL
NC_4 NC_26 NC_4 NC_26 5V_DET_HDMI_4 GPIO79 TS0DATA[0]/GPIO82 CI_TS_DATA[1] GPIO79 TS0DATA[0]/GPIO82
4 45 4 45 T13 T13
GND SDA
TS0DATA[1]/GPIO83 CI_TS_DATA[2] TS0DATA[1]/GPIO83
NC_5 I/O7 NC_5 I/O8 4 5 R184 22 K17 U13 K17 U13
5 44 5 44 I2C_SCL I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84 CI_TS_DATA[3] I2C_SCKM3/I2C_DDCR_CK/GPIO77 TS0DATA[2]/GPIO84
R183 22 J15 V15 J15 V15
NC_6 I/O6 NC_6 I/O7 I2C_SDA I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85 CI_TS_DATA[4] I2C_SDAM3/I2C_DDCR_DA/GPIO76 TS0DATA[3]/GPIO85
6 43 6 43 U8 U12 U8 U12
URSA/VCOM_SDA SDAM2/GPIO55 TS0DATA[4]/GPIO86 CI_TS_DATA[5] SDAM2/GPIO55 TS0DATA[4]/GPIO86
R/B I/O5 RY/BY I/O6 EAN61133501 T7 V13 T7 V13
7 42 7 42 URSA/VCOM_SCL SCKM2/GPIO56 TS0DATA[5]/GPIO87 CI_TS_DATA[6] SCKM2/GPIO56 TS0DATA[5]/GPIO87
U7 U14 U7 U14
RE I/O4 RE I/O5 SENSOR_SCL SCKM0/GPIO58 TS0DATA[6]/GPIO88 CI_TS_DATA[7] SCKM0/GPIO58 TS0DATA[6]/GPIO88
8 41 8 41 V7 T11 Internal demod out V7 T11
SENSOR_SDA SDAM0/GPIO59 TS0DATA[7]/GPIO89 SDAM0/GPIO59 TS0DATA[7]/GPIO89
CE NC_25 CE NC_25 T2_OR_CHINA F6 T12 F6 T12
9 40 9 40 R113 22 AMP_SCL I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91 FE_TS_CLK I2S_IN_BCK/GPIO159 TS0SYNC/GPIO91
DEMOD_SCL G6 V12 G6 V12
R114 22 AMP_SDA I2S_IN_SD/GPIO160 TS0VALID/GPIO90 FE_TS_DATA[0-7] I2S_IN_SD/GPIO160 TS0VALID/GPIO90
NC_7 NC_24 NC_7 NC_24 AA4 Y14 AA4 Y14
10 39 10 39 DEMOD_SDA
T2_OR_CHINA TU_SCL I2C_SCKM1/GPIO80 TS1CLK/GPIO103 FE_TS_DATA[0] FE_TS_SYNC I2C_SCKM1/GPIO80 TS1CLK/GPIO103
NC_8 NC_23 NC_8 NC_23 Y4 Y16 Y4 Y16
11 38 11 38 TU_SDA I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93 FE_TS_DATA[1] FE_TS_VAL_ERR I2C_SDAM1/GPIO81 TS1DATA[0]/GPIO93
AA15 AA15
VCC_1 VCC_2 VCC_1 VCC_2 TS1DATA[1]/GPIO94 FE_TS_DATA[2] TS1DATA[1]/GPIO94
12 37 12 37 J6 Y13 J6 Y13
AV_CVBS_DET ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95 FE_TS_DATA[3] ET_TXD[0]/GPIO62 TS1DATA[2]/GPIO95
VSS_1 VSS_2 VSS_1 VSS_2 K6 AA16 K6 AA16
13 36 13 36 AV2_CVBS_DET EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96 FE_TS_DATA[4] FE_TS_DATA[0] EXT_TX_CLK/GPIO64 TS1DATA[3]/GPIO96
W12 W12
TS1DATA[4]/GPIO97 FE_TS_DATA[0] TS1DATA[4]/GPIO97
NC_9 NC_22 NC_9 NC_22 G7 AA13 FE_TS_DATA[5] G7 AA13
14 35 14 35
COMP2_DET I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98 FE_TS_DATA[6] I2S_IN_WS/GPIO158 TS1DATA[5]/GPIO98
NC_10 NC_21 NC_10 NC_21 W14 W14
15 34 15 34 TS1DATA[6]/GPIO99 FE_TS_DATA[7] TS1DATA[6]/GPIO99
J4 W13 J4 W13
CLE NC_20 CLE NC_20 DEMOD_RESET ET_COL/GPIO60 TS1DATA[7]/GPIO100 ET_COL/GPIO60 TS1DATA[7]/GPIO100
16 33 16 33 J5 Y15 J5 Y15
MODEL_OPT_0 ET_TXD[1]/GPIO61 TS1SYNC/GPIO102 ET_TXD[1]/GPIO61 TS1SYNC/GPIO102
ALE I/O3 ALE I/O4 W15 W15
17 32 17 32 TS1VALID/GPIO101 TS1VALID/GPIO101
H19 H19
WE I/O2 WE I/O3 MODEL_OPT_1 LCK/GPIO194 LCK/GPIO194
18 31 18 31 G20 B3 R189 33 G20 B3
MODEL_OPT_2 LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13 /SPI_CS LDE/GPIO195 PM_SPI_SCZ1/GPIO_PM[6]/GPIO13
WP I/O1 WP I/O2 G19 A3 R188 33 G19 A3
19 30 19 30 /MHL_OCP_DET LHSYNC/GPIO196 PM_SPI_SCK/GPIO1 SPI_SCK LHSYNC/GPIO196 PM_SPI_SCK/GPIO1
G21 A4 G21 A4
NC_11 I/O0 NC_11 I/O1 FRC_RESET LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0 SIDE_HP_MUTE LVSYNC/GPIO197 PM_SPI_SCZ0/GPIO0
20 29 20 29 33 R182 C3 C3
PM_SPI_SDI/GPIO2 SPI_SDI PM_SPI_SDI/GPIO2
NC_12 NC_19 NC_12 NC_19 J17 A2 R190 33 J17 A2
21 28 21 28 HP_DET UART2_RX/GPIO69 PM_SPI_SDO/GPIO3 SPI_SDO UART2_RX/GPIO69 PM_SPI_SDO/GPIO3
J16 J16
NC_13 NC_18 NC_13 NC_18 SC1/COMP1_DET UART2_TX/GPIO70 UART2_TX/GPIO70
22 27 22 27 E8 B1 E8 B1
MHL_OCP_EN UART3_TX/GPIO52 RP EPHY_RP UART3_TX/GPIO52 RP
NC_14 NC_17 NC_14 NC_17 D7 C2 D7 C2
23 26 23 26 AMP_RESET UART3_RX/GPIO53 TN EPHY_TN UART3_RX/GPIO53 TN
U6 C1 U6 C1
NC_15 NC_16 NC_15 NC_16 MODEL_OPT_4 GPIO46[CTS] TP EPHY_TP GPIO46[CTS] TP
24 25 24 25 V6 B2 V6 B2
RF_SWITCH_CTL GPIO47[RTS] RN EPHY_RN GPIO47[RTS] RN
33 R181 K15 K15
/CI_CD1 UART1_TX/GPIO48 UART1_TX/GPIO48
L16 D2 L16 D2
/CI_CD2 UART1_RX/GPIO49 SPDIF_IN/GPIO161 5V_DET_HDMI_2 UART1_RX/GPIO49 SPDIF_IN/GPIO161
D1 R192 100 D1
+3.3V_Normal SPDIF_OUT/GPIO162 SPDIF_OUT SPDIF_OUT/GPIO162
NAND_FLASH_2G_TOSHIBA NAND_FLASH_1G_SS H5 SPDIF_OPTIC H5
USB1_CTL ET_TX_EN/GPIO63 ET_TX_EN/GPIO63
EAN60991001 EAN61857001 R180 K5 D8 K5 D8
IC102-*3 IC102-*4 10K MODEL_OPT_5 ET_RXD[0]/GPIO65 HWRESET SOC_RESET ET_RXD[0]/GPIO65 HWRESET
K4 E5 K4 E5
TC58NVG1S3ETA00 K9F1G08U0D-SCB0 R197 0 MODEL_OPT_6 ET_MDC/GPIO66 IRIN/GPIO5 IR ET_MDC/GPIO66 IRIN/GPIO5
CI_DET H6 G4 H6 G4
R178 22 USB1_OCD ET_MDIO/GPIO67 DDCA_CK/UART0_RX RGB_DDC_SCL ET_MDIO/GPIO67 DDCA_CK/UART0_RX
/PCM_CD L5 G5 L5 G5
PCM_A[0-14] ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX RGB_DDC_SDA ET_RXD[1]/GPIO68 DDCA_DA/UART0_TX
NC_1 NC_29 NC_1 NC_29
1 48 1 48 PCM_A[0] U17 J18 U17 J18
NC_2 NC_28 NC_2 NC_28 PCM_A[1] PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71 PWM0 PCMADR[0]/NF_AD[0]/GPIO130 PWM0/GPIO71
2 47 2 47 R18 K18 R18 K18
PCM_A[2] PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72 PWM1 PCMADR[1]/NF_AD[1]/GPIO129 PWM1/GPIO72
NC_3 NC_27 NC_3 NC_27 V17 K16 V17 K16
3 46 3 46 PCM_A[3] PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73 PWM2 PCMADR[2]/NF_AD[2]/GPIO127 PWM2/GPIO73
R16 L18 R16 L18
NC_4 NC_26 NC_4 NC_26 PCM_A[4] PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74 PWM3 PCMADR[3]/NF_AD[3]/GPIO126 PWM3/GPIO74
4 45 4 45 U16 L17 U16 L17
PCM_A[5] PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75 PCM_5V_CTL PCMADR[4]/NF_AD[4]/GPIO104 PWM4/GPIO75
NC_5 I/O8 NC_5 I/O7 T17 T17
5 44 5 44 PCM_A[6] PCMADR[5]/NF_AD[5]/GPIO106 PCMADR[5]/NF_AD[5]/GPIO106
W18 T8 +3.3V_Normal W18 T8
NC_6 I/O7 NC_6 I/O6 PCM_A[7] PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146 PF_ALE PCMADR[6]/NF_AD[6]/GPIO107 NF_ALE/GPIO146
6 43 6 43 U20 T9 U20 T9
PCM_A[8] PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142 /PF_CE0 PCMADR[7]/NF_AD[7]/GPIO108 NF_CEZ/GPIO142
RY/BY I/O6 R/B I/O5 Y19 U9 Y19 U9
7 42 7 42 PCM_A[9] PCMADR[8]/GPIO113 NF_CLE/GPIO141 /PF_CE1 L101 PCMADR[8]/GPIO113 NF_CLE/GPIO141
AA19 U11 BLM18PG121SN1D AA19 U11
RE I/O5 RE I/O4 PCM_A[10] PCMADR[9]/GPIO115 NF_RBZ/GPIO147 /F_RB PCMADR[9]/GPIO115 NF_RBZ/GPIO147
8 41 8 41 AA20 V9 AA20 V9
PCM_A[11] PCMADR[10]/GPIO119 NF_REZ/GPIO144 /PF_OE PCMADR[10]/GPIO119 NF_REZ/GPIO144
CE NC_25 CE NC_25 W21 U10 R193 C119 W21 U10
9 40 9 40 PCM_A[12] PCMADR[11]/GPIO117 NF_WEZ/GPIO145 /PF_WE 10K 0.1uF PCMADR[11]/GPIO117 NF_WEZ/GPIO145
V20 T10 V20 T10
NC_7 NC_24 NC_7 NC_24 PCM_A[13] PCMADR[12]/GPIO109 NF_WPZ/GPIO199 /PF_WP R196 PCMADR[12]/GPIO109 NF_WPZ/GPIO199
10 39 10 39 Y17 0 Y17
PCM_A[14] PCMADR[13]/GPIO112 IF_AGC_MAIN PCMADR[13]/GPIO112
NC_8 NC_23 NC_8 NC_23 V18 W2 C120 V18 W2
11 38 11 38 PCMADR[14]/GPIO111 IF_AGC CHINA 0.047uF PCMADR[14]/GPIO111 IF_AGC
V19 W1 C115 0.1uF R198 CHINA47 V19 W1
VCC_1 VCC_2 VCC_1 VCC_2 PCM_D[0-7] /PCM_CD PCMCD_N/GPIO135 SIFM 25V PCMCD_N/GPIO135 SIFM
12 37 12 37 W19 W3 C116 0.1uF R199 47 W19 W3
/PCM_CE PCMCE_N/GPIO120 SIFP C123 PCMCE_N/GPIO120 SIFP
VSS_1 VSS_2 VSS_1 VSS_2 PCM_D[0] U18 V2 CHINA CHINA 1000pF U18 V2
13 36 13 36 PCMDATA[0]/GPIO131 IM PCMDATA[0]/GPIO131 IM
PCM_D[1] V16 V1 ANALOG SIF OPT V16 V1
NC_9 NC_22 NC_9 NC_22 PCMDATA[1]/GPIO132 IP PCMDATA[1]/GPIO132 IP
14 35 14 35 PCM_D[2] W17 Close to MSTAR TU_SIF W17
PCMDATA[2]/GPIO133 PCMDATA[2]/GPIO133
NC_10 NC_21 NC_10 NC_21 PCM_D[3] Y20 AA2 R194 0 Y20 AA2
15 34 15 34 PCMDATA[3]/GPIO125 XIN IF_N_MSTAR PCMDATA[3]/GPIO125 XIN
PCM_D[4] R15 Y2 OPT R15 Y2
CLE NC_20 CLE NC_20 PCMDATA[4]/GPIO124 XOUT C117 C121 PCMDATA[4]/GPIO124 XOUT
16 33 16 33 PCM_D[5] AA18 0.1uF 100pF DTV_IF AA18
PCMDATA[5]/GPIO123 R195 0 PCMDATA[5]/GPIO123
ALE I/O4 ALE I/O3 PCM_D[6] T15 IF_P_MSTAR T15
17 32 17 32 PCMDATA[6]/GPIO122 C118 C122 C124 PCMDATA[6]/GPIO122
PCM_D[7] Y21 0.1uF 33pF 33pF Y21
WE I/O3 WE I/O2 PCMDATA[7]/GPIO121 TU_NON_ATSC TU_NON_ATSC PCMDATA[7]/GPIO121
18 31 18 31 W20 W20
/PCM_IORD PCMIORD_N/GPIO116 PCMIORD_N/GPIO116
WP I/O2 WP I/O1 V21 Close to MSTAR V21
19 30 19 30 /PCM_IOWR PCMIOWR_N/GPIO114 PCMIOWR_N/GPIO114
Y18 Y18
NC_11 I/O1 NC_11 I/O0 /PCM_IRQA PCMIRQA_N/GPIO110 XTAL_LOAD_22pF PCMIRQA_N/GPIO110
20 29 20 29 T16 T16
/PCM_OE PCMOE_N/GPIO118 PCMOE_N/GPIO118
R17 R17
R187

NC_12 NC_19 NC_12 NC_19


/PCM_REG
X101 C113 22pF
21 28 21 28 PCMREG_N/GPIO128 PCMREG_N/GPIO128
1M

T18 24MHz C114 22pF T18


NC_13 NC_18 NC_13 NC_18 PCM_RST PCM_RESET/GPIO134 PCM_RESET/GPIO134
22 27 22 27 W16 W16
/PCM_WAIT PCMWAIT_N/GPIO105 XTAL_LOAD_22pF PCMWAIT_N/GPIO105
NC_14 NC_17 NC_14 NC_17 U15 U15
23 26 23 26 /PCM_WE PCMWE_N/GPIO198 PCMWE_N/GPIO198
NC_15 NC_16 NC_15 NC_16 XTAL_LOAD_30pF XTAL_LOAD_27pF
24 25 24 25 C113-*1 30pF C113-*2 27pF

XTAL_LOAD_30pF XTAL_LOAD_27pF
C114-*1 30pF C114-*2 27pF

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES


SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS L14_M1A 2013.08.27
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC. MAIN1_EU 1

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MODEL OPTION +3.3V_Normal
SOC_RESET +3.5V_ST
STby 3.5V Normal Power 3.3V DDR3 1.5V VDDC 1.05V +1.10V_VDDC
+1.10V_VDDC
MO_DVB_T2/C/S2
MO_DUALSTREAM

MO_S/W_EU/AJ

SWITCH_POSTEC
DDR_EXT:256

DDR_EXT:128
1K

1K

1K

1K

1K

1K

1K

L206
1K

MO_S/W_AJ

SW200-*1 BLM18PG121SN1D AVDD_NODIE +1.5V_DDR VDDC : 2026mA


MO_M120

TMSV153BRA +3.3V_Normal VDD33


MO_HD

+1.10V_VDDC
2

C289 C286 C252 +1.10V_VDDC


POWER_DET_RESET +3.5V_ST SWITCH_NAMAE 10uF 0.1uF 0.1uF AVDD_DDR0:55mA
SW200 C296 C210 C279
L204 10uF 0.1uF 0.1uF
R291

R222

R221

R206

R208

R211

R226
R290

JTP-1127WEM

0.1uF

0.1uF
0.1uF
BLM18PG121SN1D 10V
2

10uF

0.1uF
1

10V

1uF
OPT
0.1uF

0.1uF

0.1uF
0.1uF