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1/29/2020

Q-1
In the circuit below,
1. Find the range of 𝑣 over which 𝑀 is in saturation
2. Express the output voltage 𝑣 in terms of transistor
sizes, 𝑉 and 𝑉 of the transistor.
3. Using this expression, find the gain of the circuit for
𝑊 ⁄𝐿 = 50𝜇𝑚⁄0.5𝜇𝑚 and 𝑊 ⁄𝐿 = 5𝜇𝑚⁄0.5𝜇𝑚.
Neglect channel length modulation

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 1

Q-2
An NMOS amplifier is to be designed to provide a 0.20-V peak output
signal across a 20𝑘Ω load that can be used as a drain resistor. If a gain of
atleast 10 𝑉 ⁄𝑉 is needed, design the common source amplifier circuit for a
dc supply of 1.8V. Assume 𝜇 𝐶 = 200 𝜇𝐴⁄𝑉 and 𝑉 = 0.4 𝑉. What is the
average dc power consumed by the circuit?

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 2

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Q-3
In the CS stage below,
1. Neglecting channel length modulation, express
the gain only in voltages.
2. Assume a maximum possible input small signal
of 𝑣 , find the minimum value of 𝑉 (in terms of
𝑉 , 𝑣 , 𝑉 ) that maximizes gain. Assume that
𝑉 ≫ 𝑣 . You need to ensure that a negative
voltage swing of 𝑣 = − 𝐴 𝑣 may be supported
by the transistor in saturation.
3. Find 𝑉 , 𝐴 , 𝑣 for 𝑉 = 2.5𝑉, 𝑣 = 20𝑚𝑉 and
𝑉 = 0.3𝑉
4. Design the circuit in this case, assuming
𝑘 = 100 𝜇𝐴⁄𝑉 .

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 3

Q-4
In the circuit below, the NMOS transistor has 𝑉 = 0.5𝑉 and 𝑉 = 50𝑉 and
operates with 𝑉 = 1𝑉. What is the small signal voltage gain? What do 𝑉
and the gain become for 𝐼 increased to 1𝑚𝐴. You can assume that the
coupling capacitors are shorted for the given signal frequency.

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 4

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1/29/2020

Q-5
In the circuit below, assume all capacitors behave as short circuit for
signals and open circuits for dc.
1. If the transistor has 𝑉 = 1𝑉 and 𝑘 = 4 𝑚𝐴⁄𝑉 , find the bias voltages
and currents in the circuit.
2. If 𝑉 = 100𝑉 find 𝑔 and 𝑟 .
3. find 𝑅 , 𝑅 and 𝑣 ⁄𝑣 .

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 5

Q-6
Using the circuit topology shown in the figure below,
arrange to bias the NMOS transistor at 𝐼 = 0.5𝑚𝐴 with
𝑉 midway between cutoff and the beginning of triode
operation. The available supplies are ±5𝑉. For the
NMOS, 𝑉 = 1.0𝑉, 𝜆 = 0 and 𝑘 = 1 𝑚𝐴⁄𝑉 . Use a
gate bias resistor of 10𝑀Ω. Specify 𝑅 and 𝑅 to 2
significant digits.

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 6

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1/29/2020

Q-7
A very useful way to characterize the stability of the bias
current is to evaluate its sensitivity to particular transistor
parameters whose variability might be large. The
sensitivity of 𝐼 to 𝐾 = 0.5𝑘 𝑊 ⁄𝐿 is defined as

𝑆 = ⁄
= . The expected variability in the bias
∆ ∆
current is given by =𝑆
1. Find 𝑆 assuming that 𝑉 is constant.
2. For a MOSFET having a 𝐾 = 100 𝜇𝐴⁄𝑉 with a
variability of ±10% and 𝑉 = 1𝑉, find the value of 𝑅
that would result in 𝐼 = 100𝜇𝐴 with variability of
± 1%. Also find 𝑉 and required value of 𝑉 .
3. If the available supply 𝑉 = 5𝑉, find the value of 𝑅
for 𝐼 = 100𝜇𝐴. Evaluate the sensitivity function and
give the expected value in the variation
1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 7

Q-8
Consider the circuit topology as below. Using a 5-V
supply with an NMOS transistor for which 𝑉 = 0.8𝑉,
𝑘 = 8 𝑚𝐴⁄𝑉 , and 𝜆 = 0, provide a design that biases
the transistor at 𝐼 = 1𝑚𝐴, with 𝑉 large enough to allow
saturation operation for a 2-V negative voltage swing at
the drain. Use 22ΜΩ as the largest resistor in the
feedback network. What values of 𝑅 , 𝑅 and 𝑅 have
you chosen? Specify to two significant digits.

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 8

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Q-9
The NMOS transistor in the circuit below has 𝑉 = 0.7𝑉 and 𝑉 = 50𝑉.
1. Neglecting Early effect, verify that the MOSFET is in saturation with 𝐼 = 0.5𝑚𝐴
and 𝑉 = 0.3𝑉. What must the MOSFET 𝑘 be? What is the dc voltage at the
drain?
2. Find 𝑅
3. If 𝑣 is a sinusoid, with a peak amplitude 𝑣 , find the maximum allowable value
of 𝑣 for which the transistor remains in saturation. What is the corresponding
amplitude of output voltage?

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 9

Q-10
The MOSFET in the amplifier circuit below has 𝑉 = 0.6𝑉, 𝑘 = 5 𝑚𝐴⁄𝑉
and 𝑉 = 60𝑉. The signal 𝑣 has zero average.VDD=10V
1. It is required to bias the transistor to operate at an 𝑉 = 0.2𝑉? What
must be the value of the dc-current at the drain with and without
considering Early effect. What value must 𝑅 have?
2. Calculate the values of 𝑔 and 𝑟 at the bias point
3. Find the gain of the circuit.

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 10

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Q-11
We wish to design the stage of figure below for a voltage gain of 5 with 𝑊 ⁄𝐿 ≤
20⁄0.18.Determine the required value of 𝑅 if the power dissipation must not exceed
1 mW. 𝜇 𝐶 = 2𝜇 𝐶 = 200 𝜇𝐴⁄𝑉 , 𝑉 = 𝑉 = 0.4𝑉.

1/29/2020 BITS Pilani, K.K. Birla Goa Campus (AP) - 11

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