Academic Year 2017-2018 Regulation 2013

IFET COLLEGE OF ENGINEERING

DEPARTMENT OF CSE & IT
CS6303 – COMPUTER ARCHITECTURE
UNIT V– MEMORY AND I/O SYSTEMS
(100% THEORY)
QUESTION BANK
MEMORY AND I/O SYSTEMS
Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache
performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts, I/O
processors.
PART-A (2 MARKS)

Knowledge:
1. Define principle of locality.(K)
2. Write a short note on temporal locality.(K)
3. What is meant by spatial locality?(K)
4. Define hit rate and miss penalty. (K)  (Nov/Dec 2014)(Nov/Dec 2015)
5. What are the various memory technologies? (K)        (Nov/Dec 2015)
6. Define SRAM and its advantages.(K)
7. Write a note on DRAM. (K)
8. State the difference between SRAM and DRAM. (K)
9. What is DDR SDRAM?(K)        (Nov/Dec 2011)
10. What is meant by an interleaved memory?(K) (May/Jun 2013)
11. Write a short note ondual inline memory modules.(K)
12. Define flash memory. (K)
13. What is meant by wear leveling? (K)
14. Define the term seek and seek time.(K)
15. What is meant by rotational latency? (K)
16. Define transfer time.(K)
17. Write about tag field in the table used in memory hierarchy.(K)
18. List the steps to be taken on instruction cache miss. (K)
19. Define write-through.Write a technique to overcome the problem in write-through?(K)
20. Explain about write-back.(K)
21. Define the term write-allocate and no-write-allocate.(K)
22. Write a note on split cache.(K)
23. What is cache memory?(K) (Nov/Dec 2016)
24. Define Memory-stall clock cycles.(K)
25. Distinguish about Read-stall cycles and Write-stall cycles.(K)
26. What is average memory access time? (K)
27. What is direct mapped cache?(K)
28. What is set-associative cache and fully associative cache?(K)
1
IFETCE/CSE&IT/II YEAR/III SEM/CS6303/CA/UNIT-V/QB/VERSION1.2
Academic Year 2017-2018 Regulation 2013

29. What is multilevel cache?(K)

30. What is the purpose of Dirty/Modified bit in Cache memory?(K)  (Nov/Dec 2014)
31. What is virtual memory and what are the benefits of virtual memory? (K)          (Nov/Dec
2010)
32. Write a note on physical address?(K)
33. State virtual address.(K)        (Apr/May 2013)
34. What do you mean by segmentation? (K)
35. What is meant by address mapping with a neat diagram? (K) (Nov/Dec 2016)
36. Define page table. (K)
37. Discuss about swap space. (K)
38. What is TLB? (K) (Nov/Dec 2011)
39. What are the typical values for a TLB?(k)
40. What is Aliasing?(K)
41. Explain about Input/output system with its metrics.(K)
42. Draw the diagram of I/O interface for input device.(K)
43. Define Memory mapped I/O.(K)
44. Write a note on Programmed I/O. (K)
45. What is DMA controller? Mention the use of DMA controller.(K)
46. Define cycle stealing. What are the functions of Cycle stealing?(K)
47. What are the modes of operation available in DMA?(K) (Nov/Dec 2014)
48. What is meant by bus arbitration? (K) (Nov/Dec 2010)
49. What are vectored interrupt?(K)
50. Brief about nested interrupt.(K)
51. Write a note on I/O processors.Draw the block diagram of computer system with I/O Processor.
(K)
52. What are the functions of IOP?(K)

Understand:
1. Distinguish memory hierarchy.(U)
2. Compare the memory types based on size, speed and cost. (U) (Nov/Dec 2014)
3. What is the need to implement memory as a hierarchy? (U) (Apr/May 2015)
4. Mention the use of valid bit.(U)
5. What is meant by cache miss and how it is handled by using control unit?(U)
6. List the two different techniques for improving cache performance. (U)
7. Write the formula to find the position of a memory block in direct-mapped cache and set-
associative cache.(U)
8. Write the steps that must be completed when the operating system knows the virtual address
that caused the page fault.(U)
9. Compare between Memory mapped I/O and I/O mapped I/O.(U)
10. Compare Programmed I/O and Interrupt I/O. (U) (Nov/Dec 2014)
11. How CPU support the programmed I/O module?(U)
12. Point out how DMA can improve I/O speed. (U)(Apr/May 2015)
13. What are the advantages and disadvantages of DMA?(U)
14. What is the use of DMA?(U) (Nov/Dec 2012)

2
IFETCE/CSE&IT/II YEAR/III SEM/CS6303/CA/UNIT-V/QB/VERSION1.2
Academic Year 2017-2018 Regulation 2013

Application:
1. Consider the average latency to the desired information is halfway around the disk and disks
rotate at 5400 RPM to 15,000 RPM. Calculate average rotational latency at 5400
RPM?   (A)      
2. How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word
blocks, assuming a 32-bit address?(A)
3. The application program in a computer system with cache uses 1400 instruction acquisition bus
cycle from cache memory and 100 from main memory. What is the hit rate? If the cache
memory operates with zero wait state and the main memory bus cycles use three wait states,
what is the average number of wait states experienced during the program execution?(A)

4. Calculate the AMAT for a processor with a 1 ns clock cycle time, a miss penalty of 20 clock
cycles, a miss rate of 0.05 misses per instruction, and a cache access time (including hit
detection) of 1 clock cycle. Assume that the read and write miss penalties are the same and
ignore other write stalls.(A)
5. A block set-associative cache consists of 64 blocks divided into 4 block sets. The main memory
contains 4096 blocks, each consists of 128 words of 16 bits length:
i) How many bits are there in main memory?
ii) How many bits are there in each of the TAG, SET and WORD fields?(A)
6. Construct the diagram for eight-block cache configured as direct mapped, two-way set
associative, four-way set associative, and fully associative. (A)
7. A digital computer has a memory unit of 64k X 16 and a cache memory of 1 k words. The
cache uses direct mapping with a block size of four words. How many bits are there in tag
index, block and word field of the address format?(A)
8. A two way set associative cache memory uses block of four words. The cache can
accommodate a total of 2048 words from main memory. The main memory size is
128 K X 32.
i) How many bits are there in tag index, block and word field of address format?
ii) What is size of cache memory? (A)
9. An address space is specified by 32 bits and corresponding memory space by 24 bits.
i) How many words are there in the address space?
ii) How many words are there in the memory space?
iii)If a page consist of 4 K words, how many pages and blocks are there in the systems.(A)
10. An address space is specified by 24 bits and corresponding memory space by 16 bits. How
many words are there in the virtual memory and in the main memory? (A)
11. A bipolar RAM chip is arranged as 16 words. How many bits are stored in the chip and
calculate how many locations are addressed using 18 address bits?(A)
12. The logical address space in a computer system consists of 128 segments. Each segment   can
have up to 32 pages of 4K words each. Physical memory consists of 4K blocks of   4K words in
each. Formulate the logical and physical address formats.(A)
13. Calculate the effective address time if average page-fault service time of 20   milliseconds and
a memory access time of 80 nanoseconds. Let us assume the   probability of a page fault is 10%.
(A)
Skill:
3
IFETCE/CSE&IT/II YEAR/III SEM/CS6303/CA/UNIT-V/QB/VERSION1.2
Academic Year 2017-2018 Regulation 2013

1. Compare temporal and spatial locality.(S)

2. How to reduce the Miss Penalty Using Multilevel Caches? (S)

PART-B (13 MARKS)

Knowledge:
1. Explain in detail about memory hierarchy. (K) (16)
2. Explain the following:(K)
i) Memory mapped I/O (4)
ii) I/O mapped I/O (4)
iii) Hardware Interrupts (4)
iv) Vectored Interrupts (4)
(Nov/Dec 2010)
3. Explain in detail about cache basics. (K) (16)
4. What is virtual memory? Explain the steps involved in virtual memory address      translation.
(16) (K) (Apr/May 2015)(Nov/Dec 2015)
Or
Explain the virtual memory address translation with necessary tables and diagram. (16)
(K) (Nov/Dec 2014) (Nov/Dec 2016)
5. (i) Write about Input/output system and explain programmed I/O in detail. (K)(10)
(ii) Discuss in detail about interrupt. (K) (6) (May/Jun 2013)
6. (i) Explain mapping functions in cache memory to determine how memory blocks are
placed in Cache. (K) (8) (Nov/Dec 2014)
(ii) Explain in detail about the Bus Arbitration techniques in DMA. (K) (8)
(Nov/Dec 2014)(Nov/Dec 2016)
7. Explain the IOP organization and communication between CPU and IOP.(K)(16)

Understand:
1. Elaborate on the various memory technologies and its relevance. (U)(16)
(Apr/May 2015)
2. (i) Discuss in detail about the concept of TLBs. (U) (10)
(ii) How TLB misses and page faults are handled? (U) (6)
3.  Draw the typical block diagram of a DMA controller and explain how it is used for direct
data transfer between memory and peripherals?(U) (16)
(Nov/Dec 2011,2015,2016)

Application:
1. (i)Assume there are three small caches, each consisting of four one-word blocks. One cache         is
fully associative, a second is two-way set-associative, and the third is direct-mapped. Find         the
number of misses for each cache organization given the following sequence of block        addresses: 0,
8, 0, 6, and 8.       (10)
4
IFETCE/CSE&IT/II YEAR/III SEM/CS6303/CA/UNIT-V/QB/VERSION1.2
Academic Year 2017-2018 Regulation 2013

(ii)Suppose we have a processor with a base CPI of 1.0, assuming all references hit in the primary
cache, and a clock rate of 4 GHz. Assume a main memory access time of 100 ns, including all the
miss handling. Suppose the miss rate per instruction at the primary cache is 2%. How much faster
will the processor be if we add a secondary cache that has a 5 ns access time for either a hit or a
miss and is large enough to reduce the miss rate to main memory to 0.5%?    (A) ((
       (6)

5
IFETCE/CSE&IT/II YEAR/III SEM/CS6303/CA/UNIT-V/QB/VERSION1.2