LAB 5

FIRNA FRILANISA / 175060307111004

1.1 Desain sebuah SR Latch!

SR Latch (Set/Reset) merupakan perangkat asinkron, dimana ia bekerja sendiri dengan sinyal control dan
hanya bergantung pada input S dan R. Pada symbol latch ini, rangkaian SR menggunakan gerbang NOR,
dan memiliki tabel kebenaran sebagai berikut.

Desain

----------------------------------------------------------------------
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SR_latch is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end SR_latch;

architecture Dataflow of SR_latch is

signal Q_i, Qbar_i : STD_LOGIC;
begin
Q_i <= Q;
Qbar_i <= Qbar;
Q <= not(R or Qbar);
Qbar <= not(S or Q);
end Dataflow;
Testbench
----------------------------------------------------------------------
----------
-- Company:
-- Engineer:
--
-- Create Date: 13:59:44 12/05/2019
-- Design Name:
-- Module Name: C:/Users/Firna/Desktop/New folder/LAB5/tb.vhd
-- Project Name: LAB5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SR_latch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types
std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx
recommends
-- that these types always be used for the top-level I/O of a design
in order
-- to guarantee that the testbench will bind correctly to the post-
implementation
-- simulation model.
----------------------------------------------------------------------
----------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT SR_latch
PORT(
S : IN std_logic;
R : IN std_logic;
Q : INOUT std_logic;
Qbar : INOUT std_logic
);
END COMPONENT;
 --Inputs
signal S : std_logic := '0';
signal R : std_logic := '0';

--BiDirs
signal Q : std_logic;
signal Qbar : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SR_latch PORT MAP (
S => S,
R => R,
Q => Q,
Qbar => Qbar
);

stim_proc: process
begin
S<='0';
R<='0';
wait for 10 ns;
S<='0';
R<='1';
wait for 10 ns;
S<='1';
R<='0';
wait for 10 ns;
S<='1';
R<='1';
wait for 10 ns;
wait;
end process;
END;

Hasil :

1.2 Desain sebuah gated SR latch dengan menggunakan model dataflow!

Dikarenakan SR Latch asinkron memiliki kekurangan, yaitu adanya kondisi terlarang setiap nilai S dan R
adalah 1, maka dibuatlah SR Latch sinkron yang memiliki input enable. Sync SR Latch/gated SR Latch
ini memperkecil kemungkinan adanya kondisi terlarang, yaitu hanya saat nilai S dan R bernilai 1 serta
enable diaktifkan. Berikut adalah rangkaian dan tabel kebenaran gated SR Latch.
 Desain

----------------------------------------------------------------------
------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity gated_SR_latch is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC;
E : in STD_LOGIC;
Qbar : inout STD_LOGIC);
end gated_SR_latch;

architecture dataflow of gated_SR_latch is

signal R1,S1 : std_logic;
begin
R1 <= E and R;
S1 <= E and S;
Q <= Qbar nor R1;
Qbar <= Q nor S1;
end dataflow;

Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb2 IS
END tb2;

ARCHITECTURE behavior OF tb2 IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT gated_SR_latch
PORT(
S : IN std_logic;
R : IN std_logic;
Q : INOUT std_logic;
E : IN std_logic;
Qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
signal S : std_logic := '0';
signal R : std_logic := '0';
signal E : std_logic := '0';

--BiDirs
signal Q : std_logic;
signal Qbar : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: gated_SR_latch PORT MAP (
S => S,
R => R,
Q => Q,
E => E,
Qbar => Qbar
);

stim_proc: process
begin
E <= '1'; S <= '1'; R <= '0';

wait for 100 ns;

E <= '0'; S <= '1'; R <= '0';

wait for 100 ns;

E <= '1'; S <= '0'; R <= '0';

wait for 100 ns;

 E <= '0'; S <= '0'; R <= '0';

wait for 100 ns;

E <= '1'; S <= '0'; R <= '1';

wait for 100 ns;

E <= '0'; S <= '0'; R <= '1';

wait for 100 ns;

E <= '1'; S <= '1'; R <= '1';

wait for 100 ns;

E <= '0'; S <= '1'; R <= '1';
wait;
end process;

END;
Hasil :

1.3 Desain sebuah D latch dengan menggunakan model dataflow!

D Latch dikembangkan untuk mengatasi masalah keluaran terlarang. Dengan satu buah input yang
dihubungkan langsung dan yang dihubungkan dengan inverter, lalu di AND dengan input Enable sebelum
menuju rangkaian latch, hasil keluaran pada Q dan Qbar tidak akan sama. Seperti rangkaian berikut.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_Latch is
Port ( D : in STD_LOGIC;
E : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end D_Latch;
architecture Dataflow of D_Latch is
signal D1,D2 : std_logic;

begin
D1 <= E and D;
D2 <= E and (not D);
Q <= Qbar nor D2;
Qbar <= Q nor D1;
end Dataflow;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Dlatchtb IS
END Dlatchtb;

ARCHITECTURE behavior OF Dlatchtb IS

COMPONENT D_Latch
PORT(
D : IN std_logic;
E : IN std_logic;
Q : INOUT std_logic;
Qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal E : std_logic := '0';

--BiDirs
signal Q : std_logic;
signal Qbar : std_logic;

BEGIN
uut: D_Latch PORT MAP (
D => D,
E => E,
Q => Q,
Qbar => Qbar
);
-- Stimulus process
stim_proc: process
begin
E<='1';
D<='0';
wait for 10 ns;
E<='0';
D<='0';
wait for 10 ns;
 E<='0';
D<='1';
wait for 10 ns;
E<='1';
D<='1';
wait for 10 ns;
E<='0';
D<='1';
wait for 10 ns;
wait;
end process;

END;

2.1 Desain sebuah D flip flop menggunakan model behavioral!

Flip-flop adalah rangkaian dengan clock, dimana output akan berubah pada titik aktif sebuah sinyal clock
tergantung pada inputnya. Titik aktif sinyal clock dapat berupa rising atau falling sebagai pemicu D flip-
flop. Simulasikan sesuai diagram berikut.

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_ff is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Q : inout STD_LOGIC;
Qbar : inout STD_LOGIC);
end D_ff;

architecture Behavioral of D_ff is

begin
process (clk)
begin
if rising_edge(clk) then
Q <= D;
Qbar <= not D;
end if;
end process;

end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY D_fftb IS
END D_fftb;

ARCHITECTURE behavior OF D_fftb IS

COMPONENT D_ff
PORT(
D : IN std_logic;
clk : IN std_logic;
Q : INOUT std_logic;
Qbar : INOUT std_logic
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';

--BiDirs
signal Q : std_logic;
signal Qbar : std_logic;

BEGIN
uut: D_ff PORT MAP (
D => D,
clk => clk,
Q => Q,
Qbar => Qbar
);

-- Stimulus process
stim_proc: process
begin
clk<='0'; D<='0';
wait for 10 ns;
clk<='1'; D<='0';
wait for 10 ns;
clk<='0'; D<='0';
wait for 10 ns;
clk<='1'; D<='1';
wait for 10 ns;
clk<='0'; D<='1';
wait for 10 ns;
clk<='1'; D<='1';
wait for 10 ns;
clk<='0'; D<='0';
wait for 10 ns;
clk<='1'; D<='0';
wait for 10 ns;
clk<='0'; D<='0';
 wait for 10 ns;
clk<='1'; D<='1';
wait for 10 ns;
clk<='0'; D<='1';
wait for 10 ns;
clk<='1'; D<='1';
wait for 10 ns;
clk<='0'; D<='0';
wait for 10 ns;
clk<='1'; D<='0';
wait for 10 ns;
clk<='0'; D<='0';
wait for 10 ns;
clk<='1'; D<='0';
wait for 10 ns;
clk<='0'; D<='0';
wait for 10 ns;
wait;
end process;
END;

2.2 Desain rangkaian dengan timing diagram seperti dibawah dengan menggunakan model behavioral!
Perbandingan output D latch (Qa), D flip-flop positive triggered (Qb), D flip-flop negative triggered (Qc).

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_package is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
Qa : out STD_LOGIC;
Qb : out STD_LOGIC;
Qc : out STD_LOGIC);
end D_package;
architecture Behavioral of D_package is

begin
process (D, clk)
begin
if (clk='1') then
Qa <= D;
end if;
end process;

process (clk)
begin
if rising_edge(clk) then
Qb <= D;
end if;
end process;

process (clk)
begin
if falling_edge(clk) then
Qc <= D;
end if;
end process;
end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY D_tb IS
END D_tb;

ARCHITECTURE behavior OF D_tb IS

COMPONENT D_package
PORT(
D : IN std_logic;
clk : IN std_logic;
Qa : OUT std_logic;
Qb : OUT std_logic;
Qc : OUT std_logic
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';

--Outputs
signal Qa : std_logic;
signal Qb : std_logic;
signal Qc : std_logic;
BEGIN
uut: D_package PORT MAP (
D => D,
clk => clk,
Qa => Qa,
Qb => Qb,
Qc => Qc
);

-- Stimulus process
stim_proc: process
begin
wait for 10 ns; D <= '1'; clk <= '0';
wait for 10 ns; D <= '1'; clk <= '1';
wait for 10 ns; D <= '0'; clk <= '1';
wait for 10 ns; D <= '1'; clk <= '1';
wait for 10 ns; D <= '0'; clk <= '1';
wait for 10 ns; D <= '0'; clk <= '0';
wait for 10 ns; D <= '1'; clk <= '0';
wait for 10 ns; D <= '1'; clk <= '0';
wait for 10 ns; D <= '0'; clk <= '0';
wait for 10 ns; D <= '1'; clk <= '0';
wait for 10 ns; D <= '0'; clk <= '0';
wait for 10 ns; D <= '0'; clk <= '1';
wait for 10 ns; D <= '1'; clk <= '1';
wait for 10 ns; D <= '0'; clk <= '1';
wait for 10 ns; D <= '1'; clk <= '1';
wait for 10 ns; D <= '1'; clk <= '1';
wait for 10 ns; D <= '1'; clk <= '0';
wait for 10 ns; D <= '0'; clk <= '0';
wait;
end process;
END;

2.3 Desain D flip-flop dengan synchronous reset menggunakan model behavioral!

Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Dff_syncreset is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
 Q : out STD_LOGIC);
end Dff_syncreset;

architecture Behavioral of Dff_syncreset is

begin
process (clk, reset)
begin
if rising_edge(clk) then
if (reset = '1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Dff_syncreset_tb IS
END Dff_syncreset_tb;

ARCHITECTURE behavior OF Dff_syncreset_tb IS

COMPONENT Dff_syncreset
PORT(
D : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal Q : std_logic;

BEGIN
uut: Dff_syncreset PORT MAP (
D => D,
clk => clk,
reset => reset,
Q => Q
);

-- Stimulus process
stim_proc: process
 begin
wait for 10 ns; clk <= '1'; D <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; reset <= '1';
wait for 5 ns; clk <= '0'; D <= '1'; reset <= '0';
wait for 5 ns; clk <= '1'; D <= '1'; reset <= '1';
wait for 10 ns; clk <= '0'; D <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; reset <= '0';
wait for 2 ns; clk <= '1'; D <= '0'; reset <= '1';
wait for 5 ns; clk <= '1'; D <= '0'; reset <= '0';
wait for 3 ns; clk <= '0'; D <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; reset <= '0';
wait for 10 ns;
wait;
end process;
END;

2.4 Desain D flip-flop dengan synchronous reset dan clock enable menggunakan model behavioral!

Desain

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Dff_syncreset_clken is
Port ( D : in STD_LOGIC;
clk : in STD_LOGIC;
clk_en : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC);
end Dff_syncreset_clken;

architecture Behavioral of Dff_syncreset_clken is

begin
process (clk, reset, clk_en)
begin
if rising_edge(clk) then
if (reset = '1') then
Q <= '0';
elsif (clk_en = '1') then
 Q <= D;
end if;
end if;
end process;
end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Dff_syncreset_clken_tb IS
END Dff_syncreset_clken_tb;

ARCHITECTURE behavior OF Dff_syncreset_clken_tb IS

COMPONENT Dff_syncreset_clken
PORT(
D : IN std_logic;
clk : IN std_logic;
clk_en : IN std_logic;
reset : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;

--Inputs
signal D : std_logic := '0';
signal clk : std_logic := '0';
signal clk_en : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal Q : std_logic;

BEGIN
uut: Dff_syncreset_clken PORT MAP (
D => D,
clk => clk,
clk_en => clk_en,
reset => reset,
Q => Q
);

-- Stimulus process
stim_proc: process
begin
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '1'; reset <= '0';
 wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '0'; reset <= '1';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '1';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '1'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '0'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '1'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '1'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '0'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns; clk <= '1'; D <= '1'; clk_en <= '0'; reset <= '0';
wait for 10 ns;
wait;
end process;
END;

2.5 Desain sebuah T flip-flop dengan synchronous negative-logic reset dan clock enable!
Desain
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_ff is
Port ( T : in STD_LOGIC;
en : in STD_LOGIC;
clk : in STD_LOGIC;
Q : inout STD_LOGIC);
end T_ff;

architecture Behavioral of T_ff is

begin
process (clk,en,T)
begin
Q<='0';
if falling_edge(clk) then
if (en = '1') and (T = '1') then
Q <= not(Q);
else
 Q <= Q;
end if;
end if;
end process;
end Behavioral;

Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Tff_tb IS
END Tff_tb;

ARCHITECTURE behavior OF Tff_tb IS

COMPONENT T_ff
PORT(
T : IN std_logic;
en : IN std_logic;
clk : IN std_logic;
Q : INOUT std_logic
);
END COMPONENT;

--Inputs
signal T : std_logic := '0';
signal en : std_logic := '0';
signal clk : std_logic := '0';

--BiDirs
signal Q : std_logic;

BEGIN
uut: T_ff PORT MAP (
T => T,
en => en,
clk => clk,
Q => Q
);

-- Stimulus process
stim_proc: process
begin
wait for 10 ns; clk <= '1'; en <= '0'; T <= '0';
wait for 10 ns; clk <= '0'; en <= '1'; T <= '0';
wait for 10 ns; clk <= '1'; en <= '1'; T <= '0';
wait for 10 ns; clk <= '0'; en <= '0'; T <= '1';
wait for 10 ns; clk <= '1'; en <= '0'; T <= '1';
wait for 10 ns; clk <= '0'; en <= '1'; T <= '1';
wait for 10 ns; clk <= '1'; en <= '1'; T <= '0';
wait for 10 ns; clk <= '0'; en <= '0'; T <= '0';
wait for 10 ns; clk <= '1'; en <= '0'; T <= '1';
wait for 10 ns; clk <= '0'; en <= '1'; T <= '1';
 wait for 10 ns; clk <= '1'; en <= '0'; T <= '0';
wait for 10 ns; clk <= '0'; en <= '1'; T <= '0';
wait for 10 ns;
wait;
end process;
END;