As you work through the design and simulation example complete

the Assignment Template File  as instructed in the file itself and in

design study walkthrough documents. All files are available on the Digital
System Design Study Assignment page.
Upload your edited copy of the template file to the assignment.

Digital System Design Study Assignment page:-

Digital System Design Study

Assignment
Remote working update - please read the
announcement.
Introduction
The Digital System Design Study Assignment is a guided study and
assessment. You will work through the design of digital circuit using
professional software tools for design input and circuit simulation. You will
be provided with detailed written instructions on what to do, but will also
have to make some minor adjustments or modifications to the design and
simulation to help develop your understanding, and provide evidence of
your progress. At the end of the stud you will implement the design
physically by programming an FPGA (Field Programmable Gate Array)
using development boards provided in the laboratory.
The aims is for you:

 To see how such design work progresses – the thinking that goes
into the design process.
 To see how simulation is used to verify the correctness of a digital
design.
 To experience using the design tools and “workflow” involved.

This will help prepare you for working on your own designs in the future.

What to do
All the detailed instructions are provided on the Digital System Design
Study Assignment page of the 400463 Canvas site. There are also links to
design files for the software that you need to download. It is important
that you read the instructions very carefully and follow them
exactly. You are likely experience problems using the software if you do
not follow the instructions accurately.
There is a document referred to a “Walkthrough 1” which describes basic
procedures for using the software without reference to the specific design
you are working on. This must be completed before working on the main
design.
The main design study is described in the “Design and Simulation
Walkthrough”. The overview must be read before starting the work in the
Design and Simulation Walkthrough – it does not contain any instructions
on using the software so can be read away from the lab if required. It
provides essential background and explanation of the design you will be
working on.
Once you have worked through Walkthrough 1 work through the main
Study/Assignment document. This will take several weeks (as timetabled)
but you are also free to work in the lab at other times when it is not being
used by other classes.

Digital Design and Simulation Study/Assignment -

Documents
Documents for use in this study

 Brief Introduction  - A breif overview of the design study - similar

content to this page.
 Intel Quartus/Questasim software walkthrough  - "Walkthough 1" -
This is the first activity in the lab - a general introduction to using the
software.
 Guide to dealing with software error messages and problems  -
Help with debug - use this to help solve problems using the software.
 Design Study and Simulation: RGB LED Driver  - The main study
assignment document.
 RGB LED Board User Manual  - User manual for the custom
electronics board with the RGB LED (for reference)
 DE0-Nano-SoC User Manual  - User manual for the commercial
FPGA development board (for reference).

Assignment Template
 Assignment Submission Template file  (.docx format) - Edit this
and submit it.

Mark Scheme
This assignment comprises a set of tasks which are completed as your
work through the study assignment. These typically involve capturing
screenshots or other evidence of your progress and pasting these in the
template file provided above. Each task is worth 3 to 5 marks (depending
on complexity/number of requirements), which are awarded based on
correctness of completion of the task and presentational aspects (for
example, a waveform screenshot is of an appropriate size and quality and
relevant axes are visible and configured correctly). The state machine
task is worth ten marks, depending on correctness and compliance with
specified requirements. The total mark will be scaled to a percentage
when you receive feedback on the assignment.
Most of the tasks are individualized (typically based on your student
number) as specified in the study document. If you fail to comply with
individual requirement for a task then the mark for that task will be zero,
irrespective of other aspects. For example if the required digits your
student number are not included in waveform name, or if this signal name
is not clearly visible in the submitted screenshot.

Individual Design Files

These are links to all the design files grouped by the section of the study
assignment document in which they are used. Download and use as
instructed.
Section 9. Design and Simulation of the Up/Down Counter

 UDCount.bdf - Up/Down Counter schematic file

 Up/Down counter testbench code snippets  (text file)

Section 10. Design and Simulation of the Count Zero Timer

 CountZero.bdf - Count Zero Timer schematic file

 CountZero.vht - Count Zero Timer testbench VHDL file

Section 12. Design and Simulation of the Clock Generator

(including CZ Load Logic)

 ClockGeneratorSim.bdf - Clock Generator schematic (for simulation)

 ClockGeneratorSim.vht - Clock Generator testbench VHDL file

Section 13. Design and Simulation of the RGB Controller State

Machine

 Mux4Bit2Way.bsf - Multiplexer symbol

 Mux4Bit2Way.cmp - Multiplexer component
 Mux4Bit2Way.qip - Multiplexer Quartus IP
 Mux4Bit2Way.vhd  - Multiplexer VHDL code
 RGBControlSim.bdf - RGB Controller schematic
 RGBControlSim.bsf - RGB Controller symbol
 RGBNextState.bdf - Next State Logic schematic
 RGBNextState.bsf - Next State Logic symbol
 RGBOutputLogic.bdf - Output Logic schematic
 RGBOutputLogic.bsf - Output Logic symbol
 RGBControlSiim1.vht - First RGB Controller test bench
 RGBControlSiim2.vht - Second RGB Controller test bench

Section 14. Full System Design Entry and Simulation

 Rainbow_RGB_LED_Driver_Sim.bdf - Full system schematic (Version

for Simulation)
 UDCount.bsf - Up/Down Counter symbol file
 CountZero.bsf - Count Zero Timer symbol file
 ClockGeneratorSim.bsf - Clock Generator symbol file (for simulation)
 RainbowLED.sdc - Full system SDC file (Version for Simulation)
 Rainbow_RGB_LED_Driver_Sim.vht - Full system test bench
 Rainbow_RGB_LED_Driver_Sim2.vht - Second full system test bench

Section 15. FPGA Implementation

 Rainbow_RGB_LED_Driver.bdf - Full system schematic (Version for

FPGA)
 RainbowLED.sdc - Full system SDC file (Version for FPGA)
 ClockGenerator.bdf - Clock Generator schematic file (for FPGA)
 ClockGenerator.bsf - Clock Generator symbol file (for FPGA)

 All Files in Zipped Collection

The following link is a zipped collection of all the files for the study
assignment (documents and design files). Do not copy/unzip this into a
Quartus project folder. If you download this collection copy the relevant
files from the unzipped collection into the Quartus project when the
instructions ask you to download them. The design files are grouped into
folders related to the section of the study assignment document in which
they are used (e.g. 9UDCounter for Section 9. Design and Simulation of
the Up/Down Counter).

 Study Assignment Files - Zipped collection of all files

Logic Friday Files

You do not need the following files, but they are discussed in the study
assignment document and are provided here for completeness, and for
your reference and experimentation, if interested.

 NextStateTruthTable.txt  - RGB controller next state logic in Logic

Friday format
 OutputTruthTable.txt  - RGB controller output logic in Logic Friday
format