BC66-OpenCPU

Reference Design

LPWA Module Series

Rev. BC66-OpenCPU_Reference_Design_V1.1

Date: 2019-02-26

Status: Released

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 LPWA Module Series
BC66-OpenCPU Reference Design

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BC66-OpenCPU_Reference_Design 1/4
 LPWA Module Series
BC66-OpenCPU Reference Design

About the Document

History

Revision Date Author Description

1.0 2018-08-27 Speed SUN Initial

1. Updated the power supply block diagram (Figure 1).

2. Optimized the notes of “Battery Application” section in
Sheet 2.
1.1 2019-02-26 Speed SUN 3. Added USB interface designs in Sheet 5.
4. Added auto startup circuit design (voltage detector
solution) in “PWRKEY Reference Design” section in
Sheet 6.

BC66-OpenCPU_Reference_Design 2/4
 LPWA Module Series
BC66-OpenCPU Reference Design

Contents

About the Document ................................................................................................................................... 2

Contents ....................................................................................................................................................... 3

1 Reference Design ................................................................................................................................. 4

1.1. Introduction ................................................................................................................................ 4
1.2. Schematics ................................................................................................................................ 4
1.2.1. Power Supply Block Diagram .......................................................................................... 4
1.2.2. Reference Designs........................................................................................................... 4

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 LPWA Module Series
BC66-OpenCPU Reference Design

1 Reference Design

1.1. Introduction

This document provides the reference design for Quectel BC66-OpenCPU module.

1.2. Schematics

1.2.1. Power Supply Block Diagram

Auto Startup Circuit

(through PWRKEY)

USB U502-
MOS Circuit
Interface SGM2019
BC66
Battery VBAT_BC66
S1
Switch
U201- NETLIGHT
5V_DC
SGM6013

UART Voltage Level Translator

VDD_EXT
SPI Voltage Level Translator
BC66

SIM_VDD USIM Card Power Supply

Figure 1: Block Diagram of BC66-OpenCPU Power Supply

1.2.2. Reference Designs

The schematics illustrated in the following pages are provided for your reference only.

BC66-OpenCPU_Reference_Design 4/4
 6 5 4 3 2 1

Module Interfaces

D D

VBAT_BC66

TXD_DBG [4]
RXD_DBG [4]
[1,2,4,6]
VBAT_BC66

A TVS diode is recommended here.

J101 C101 C103 C104 C105

+
44

43

42

41

40

39

38

37

36
RF_ANT D101
Note 1 100uF 100nF 100pF 22pF

VBAT_RF

VBAT_BB
RESERVED

GND

GND

GND

GND
TXD_DBG

RXD_DBG
Capacitance of C101 should be selected
R103
1
GND RF_ANT
35 by debugging to ensure that the input voltage
2
RESERVED GND
34 0R
[5] SPI_MISO 3
SPI_MISO GPIO5
33
C107 after maximum voltage drop during the burst
C106
[5] SPI_MOSI 4 32

transmission is within the normal range.

SPI_MOSI GPIO4

[5] SPI_SCLK 5
SPI_SCLK GPIO3
31
NM NM
BC66-OpenCPU
[5] SPI_CS 6
SPI_CS GPIO2
30

[4,6] PWR_KEY 7
PWRKEY TXD_AUX
29 TXD_AUX [4] Notes: C
C 8
RESERVED RXD_AUX
28 RXD_AUX [4]
[1] ADC
9
ADC0 GND
27 1. The input voltage of VBAT ranges from 2.1V to 3.63V.
10 26
SIM_GND GPIO1

[3] SIM_DATA0
11
SIM_DATA RESERVED
25 2. The width of VBAT trace is recommended to be greater than 0.5mm,
12 24 C102 4.7uF
[3] SIM_RST0 SIM_RST VDD_EXT

[3] SIM_CLK0
13
SIM_CLK RTS_AUX
23 and the longer the trace is, the wider it should be.
VDD_EXT [4,5]
PSM_EINT
NETLIGHT

CTS_AUX

3. The capacitors should be placed in ascending order of the capacitance

SIM_VDD

RESET

Note 2
DCD

U101-A
RXD
TXD

RI

value, and the one with the minimum capacitance should be placed
14

15

16

17

18

19

20

21

22

nearest the VBAT pins. Additionally, all these capacitors should

[3] SIM_VDD0

[6] NETLIGHT
[6] RESET

[4] RXD

[4] RI
[6] PSM_EINT
[4] TXD

be placed as close to the VBAT pins as possible.

58

57

56
RESERVED

RESERVED

RESERVED
45
RESERVED RESERVED
55 ADC Reference Circuit
B B
46 54
RESERVED RESERVED
VOLTAGE_INPUT
BC66-OpenCPU

USB_MODE 47 53
[5]
USB_MODE RESERVED
R101

48
RESERVED U101-B RESERVED
52 ADC [1]

C108
VUSB_3V3

USB_DM
USB_DP

R102
100nF
49

50

51
USB_DM
USB_DP
VUSB_3V3

[5]
[5]
[5]

The maximum input voltage of 10-bit ADC is 1.4V.

Notes:
1. A PI type matching circuit is recommended here. For more details about RF layout, please refer to
A
A Quectel_RF_Layout_Application_Note. Quectel Wireless Solutions
2. VDD_EXT is a 1.8V output power supply and has no voltage output in PSM. It is intended to supply power for the module’s DRAWN BY PROJECT TITLE
Speed SUN BC66-OpenCPU Reference Design
pull-up circuits, and is thus not recommended to be used as the power supply for external circuits. CHECKED BY SIZE VER
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Power Supply
D D

DC Power Supply

Imax = 600mA
Vout = 0.6x(1+R202/R201) = 3.3V
VCC_5V U201
DC input 5V (Vmax=5.5V)
2.2uH
J201
1 1
IN SW
5
VBAT_DCDC

C207

100nF
C208
3 L201 R202

C204
C203
2 C201 3
EN FB
4

+
D201
330K

GND
NM
R203

R204
10K
100nF
100uF

10uF
R201 C202

2
2.2K

4.7uF
73.2K
C

D202
2
18pF
C

1
Q201
[6] POWER_EN

Notes:
1. The output current of power converter should be no less than 0.5A.
2. The recommended power management IC is SGM6013.

B
Battery Application Power Supply Selection B

BAT201 VBAT_BATTERY
47uF

SS-12D02
100nF C206

D203
1 5
VBAT_BATTERY
C205

A TVS diode is recommended here. VBAT_DCDC

2 VBAT_BC66
3 4
Notes: S101

1. The battery voltage shall range between 2.1V and 3.63V to meet the module’s power supply requirements,
Notes:
and the battery's rated output current should be greater than the module's maximum current consumption.
1. S101 is used to switch between an external 5V power supply and battery power supply.
Additionally, it is recommended to do reverse battery protection to avoid damages to the module.
2. VBAT_BC66 ranges from 2.1V to 3.63V, and the typical value is 3.3V.
2. According to battery selection, the capacitance of C205 should be appropriately increased according to debugging results.

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USIM Interface Design

D D

Note 1

100nF
C301
[1]
J401 C
SIM_VDD0 6 VCC GND 1
C
[1] SIM_RST0
5 RST VPP 2
22R R303 4 CLK
[1] SIM_CLK0 I/O 3
22R R304
[1] SIM_DATA0
22R R301

R302
10K

33pF C302

C303

33pF C304
33pF
1

6
2
U301
Note 2

B B

Notes:
1. The value of C301 should be less than 1uF.
2. U301 is used for protecting USIM interface against ESD and the junction capacitance should be less than 50pF.
It should be placed nearby USIM card connector.
3. For more design guidelines, please refer to Chapter 3.10 of Quectel_BC66-OpenCPU_Hardware_Design.

A
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UART Interface Design

D D
UART Level Translation - IC Solution UART Level Translation - Transistor Solution
R405
VDD_EXT 4.7K
VDD_EXT
C403

1.0nF

R406
10K

1
100nF 100nF D401
3 2
C402 C401
BC66 Translator MCU/DTE 2 3
1 VCCA VCCB 20 1 VDD
[1,4,5] VDD_EXT D402
2 OE GND 19

R408
R407

10K
[1,4] RXD 3 A1 B1 18 2 TXD 4.7K
BC66 MCU/DTE
4 A2 B2 17 3 RXD
[1,4] TXD
5 16 4 [1,4,5] 1 VDD
[1,4] RXD_DBG A3 B3 TXD_DBG VDD_EXT
[1,4] 6 A4 B4 15 5 RXD_DBG 1.0nF
TXD_DBG
[1,4] RXD_AUX
7 A5 B5 14 6 TXD_AUX [1,4] RXD C404 2 TXD C
8 13 7 3
C [1,4] TXD_AUX A6 B6 RXD_AUX [1,4] TXD RXD
[1,4] RI 9 12 8 4 TXD_DBG
R403 A7 B7 R402 GPIO [1,4] RXD_DBG
10 11 9 5 RXD_DBG
A8 B8 GND [1,4] TXD_DBG
51K 51K 6 TXD_AUX
[1,4] RXD_AUX
U401 U402 7
[1,4] TXD_AUX RXD_AUX
[1,4] RI 8 GPIO
9 GND
Notes:
Notes: U403
1. When there is a SMS or URC output, the module will inform DTE with the RI pin.
1. When there is a SMS or URC output, the module will inform DTE with the RI pin.
2. Please pay attention to the level matching issue of UART ports during application.
2. Please pay attention to the level matching issue of UART ports during application.
3. Please note that the voltage level translator requires VCCA ≤ VCCB.
3. The circuit design of dotted line section can refer to the design of solid line section,
but please pay attention to the direction of connection.

B
Recommended Test Points for Firmware Upgrade Recommended Test Points for UART Ports B

Debug UART Port Auxiliary UART Port

[1,2,6] VBAT_BC66 1
2 1 1
[1,4] RXD [1,4] RXD_DBG [1,4] RXD_AUX
3 2 2
[1,4] TXD [1,4] TXD_DBG [1,4] TXD_AUX
4 3 3
[1,6] PWR_KEY
5
CON402 CON403
CON401

Please pay attention to the level matching issue of the port during application. Please pay attention to the level matching issue of UART ports during application.

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SPI & USB Interface Designs

D D
SPI Level Translation USB Interface Design
J503
WX455810589X

9
8
GND
GND
[5] VBUS
1
VBUS
2
[1] USB_DM 3
USB_DM
USB_DP
[1] USB_DP 4
USB_ID

PTVSHC3D12VU
5

ESD9L5.0ST5G
GND

ESD9L5.0ST5G
Q505

1
SI2333CDS-T1-GE3

D504

GND
GND
D506
D505

2
[5] VCC_3V3 VUSB_3V3 [1]

6
7
S D

100nF +/-10% 10V

G
100nF 100nF

C534
VBUS VCC_3V3
C2 U502
BC66 C1 TRANSLATOR R526
DTE SGM2019-ADJYN5G/TR
10K +/-5% R527
1 12 1 VDD
[1,4] VDD_EXT
2
VCCAVCCB
11 100K +/-5% 1
IN OUT
5 C
OE GND
C 3 10 2 SPI_CS
3
EN BP
4

GND

100nF +/-10% 10V

[1] SPI_CS A1 B1 R514

2.2uF +/-20% 6.3V

4 9 3 SPI_SCLK R515
[1] SPI_SCLK A2 B2

2
C526 10K +/-5% 75K +/-1%
5 8 4 SPI_MOSI

C529
[1] SPI_MOSI A3 B3 100nF +/-10% 10V
Q509

C528
6 7 5 SPI_MISO [5] VBUS C527
[1] SPI_MISO A4 B4 R520
DTC043ZEBTL 1uF +/-10% 10V
U501 43K +/-1%
U502

USB Download Circuit

S555
SS-12D02

1 5
Pin USB Download Mode Catch Log via USB
Notes: 2 USB_MODE [1]
3 4
B B
1. Please pay attention to the level matching issue of SPI interface during application.
R555
USB_MODE Connect the pin to GND with a 10KΩ pull-down resistor NC
2. Please note that the voltage level translator requires VCCA ≤ VCCB. 10K +/-5%

Notes:
1. The USB interface and thereof signal traces should be kept away from power supply, RF interface and
other sensitive signal traces.
2. The impedance of USB signal traces should be controlled as 90Ω.
3. It is recommended to select TVS diodes with parasitic capacitance less than 3pF for USB signal lines,
and place the them close to the USB connector.

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MCU Control and Drive Circuits

D D

PSM_EINT Reference Circuit PWRKEY Reference Circuit

PSM_EINT can be used to wake up the module from PSM. MCU Application Auto Startup Circuit Design Auto Startup Circuit Design
(Capacitor Solution) (Voltage Detector Solution)
PSM_EINT VBAT_BC66

[1]
[1,4,6] PWR_KEY
[1,2,4,6] VBAT_BC66
Controlled by DTE (e.g. MCU)

RB160M-30TR
Controlled by DTE (e.g. MCU)

1
D605

VIN
Q603 [6] PWRKEY_N Q601
[6] PSM_EINT_N R612
[1,4,6]
0R +/-5%
PWR_KEY
2
VSS VOUT
4 PWR_KEY

NM_0R R666
[1,4,6]

47uF C666
U602
C607 XC6119N21ANR-G C

CD
C Keystroke Application
470nF +/-20% 6.3V
Notes:

3
Note: Note:
1. The voltage domain of PSM_EINT is VBAT. PWR_KEY [1,4,6] When it is intended to reset the module through
When it is intended to reset the module through
2. PSM_EINT supports falling edge triggered interrupt, S601 ESD9L5.0ST5G
disconnecting the power supply, please

2
3
disconnecting the power supply, please

1
D601
WT-1203

2
and thus supports connection to external sensors disconnect VBAT_BC66 for 2s at least before disconnect VBAT_BC66 for 200ms at least

4
with interrupt function. 1 re-apply the power supply. before re-apply the power supply.

Network Status Indication Reset Reference Circuit MCU GPIO

MCU
B The NETLIGHT pin is used to indicate network status. MCU Application B
1 RESET_N [6]
GPIO
VBAT_BC66 RESET [1,6] 2 PWRKEY_N [6]
Controlled by DTE (e.g.MCU) GPIO
GPIO 3 PSM_EINT_N [6]
GPIO 4 POWER_EN [2]
[6] RESET_N Q602
2.2K U601
R601
Note:
D603

OpenCPU is a solution where the module acts as a main

processor, eliminating the demand of an external MCU.
Keystroke Application
[1] NETLIGHT
This document also includes reference designs for
Q604 EMT3
RESET [1,6]
applications with an external MCU so as to meet
D602
2
3

S602
1

customers' varied demands.

WT-1203 ESD9L5.0ST5G
2

A
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4
1

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