ADVANTAGE DISADVANTAGE

Versatile: add devices Creates communication

easily bottleneck
Low cost: single set of Maximum bus speed is
wires shared in limited
multiple ways

Data Lines
Provide path for moving data among system
module
Address Lines
Use to designate the source of destination of the
data on the data bus
Control Lines
Control the access to, the use of the data and
address lines.

Bus types:
Dedicated, Shared
Arbitration method:
Centralized, Decentralized
Timing:
Synchronous, Asynchronous

Centralized:
Hardware (arbiter) that will grant the bus to one of the
requesting devices.
Decentralized:
Isn’t an arbiter, so the IO devices have to decide who goes
next

In case of a write operation, the master places the data on the bus along with the address and
commands at time t0 (reference to positive edge of the clock)
Slave strobes the data into its input buffer at time t2 (again, reference to positive edge of the
clock)
Bus Propagation Delay
 Data transfers are controlled by a handshake Timing Diagram:
between the master and the slave (no common
clock)

Operation based on two timing control:

- Master ready
- Slave ready

Multiple I/O devices will be connected to the

processor and the memory via a bus.
Each I/O device is assigned with a unique
address.
To access I/O device, the processor places the
address on the address lines.
The device recognizes the address, and
responds to the control signals.
 Program controlled i/o Interrupts driven i/o Direct Memory Access
(DMA)
Processor repeatedly Processor has to wait a long Transfer a block of data
monitors a status flag to time for the I/O module to be directly between an I/O
achieve the necessary ready for either reception or device and the main memory,
synchronization. transmission of data. without continuous
intervention by the processor.
i/o commands: Basic operation of interrupt: DMA operation:
- Control - CPU issues read - Processor initiates the
- Test command. DMA process,
- Read - I/O module gets data supplies information
- Write from peripheral whilst to DMA controller
i/o mapping: CPU does other work. - DMA controller
[1] Share the same address - I/O module interrupts performs and manages
space: CPU. data transfer until
- Memory-mapped I/O - CPU requests data. finished
[2] Have different address - I/O module transfers - Interrupt the processor
space: data. to notify transfer is
- Special instructions complete

Advantage: Advantage: Advantage:

- Simple to implement - Fast - High transfer rate
- Very small hardware - Efficient - Fewer CPU cycle for
support Disadvantage: each transfer
Disadvantage: - Can be tricky to write Disadvantage:
- Busy waiting using low level - More expensive
- Ties up CPU for long language system
period with no useful - Can be tough to get
work various pieces to work
together
Process Service routine Latency Acknowledge
Executing the Treatment of an Saving and When a
instruction interrupt-service restoring processor
located at routine is very information can receives an
address ‘I’ when similar to that of be done interrupt-
an interrupt a subroutine automatically by request, it must
occurs. process. the processor or branch to the
explicitly by interrupt service
program routine.
instructions.
Enable/Disable Multiple Polling Interrupt
interrupts identifier
To avoid Multiple I/O When a The device
interruption by devices may be processor requesting an
the same device connected to the receives an interrupt may
during the processor and interrupt request identify itself
execution of an the memory via over this control directly to the
interrupt service a bus, thus can line, the status processor:
routine: generate register of each
1- First multiple device has an
instruction of an interrupt IRQ bit which it
interrupt service requests. sets to 1 when it
routine can be requests an
Interrupt- interrupt.
disable.
2- Last
instruction of an
interrupt service
routine can be
Interrupt-enable.

Interrupt priority i/o device priority Processor priority

If the I/O devices An interrupt Processor’s
are organized in a request from a priority is encoded
priority structure, high-priority in a few bits of the
the processor device is accepted processor status
accepts the while the register.
interrupt request processor is
from a device executing the
with higher interrupt service
priority. routine of a low
priority device.
Interrupt-requests from I/O
devices
Recovery from errors
Debugging
Privilege exception