EET ELECTRONIC SYSTEMS

DEE Test (4 points)

U PC

Surname: Name: 11-04-2012

Marking: right answer +1, wrong answer –1/3, no answer 0.

1. Which one is the right relationship between the functions x, y and z

and the input variables a, and b.
a) x= NAND, y=NOR, z =XNOR a b x a b y a b z
b) x=XOR, y=NAND, z =XNOR 0 0 1 0 0 1 0 0 1
0 1 1 0 1 0 0 1 0
c) x= NAND, y=NOR, z =XOR 1 0 1 1 0 0 1 0 0
d) x=NAND, y=OR, z =XOR 1 1 0 1 1 0 1 1 1
2. How many and which kinds of gates will be required to implement the function X  A·B  AC ?

a) 2 AND gates and 1 OR gate. b) 2 AND gates, 1 OR gate and 1 inverter.

c) 2 OR gates, 1 AND gate and 1 NOT gate. d) 1 AND gate, 1 OR gate and 1 inverter.
3. Spot the right equivalence
a) 11012 1210 0D16 b) 11112 1610 1016
c) 11102 1410 E016 d) 110112 2710 1B16
4. The hexadecimal representation of the octal number 21521578 is…
a) AD46716 b) 8C46F16 c) 8D46F16 d) AE46F16
5. Spot the false statement.
a) A Karnaugh map is an array of cells, each representing a row of the truth table.
b) An n-variable Karnaugh map has 2n cells.
c) A Karnaugh map cell is adjacent to the cells that diagonally touch any of its corners.
d) Adjacent cells differ in the state of one variable.
6. In a 4-variable Karnaugh map, a 2-variable term is derived from:
a) A group of 2 adjacent cells. b) A group of 4 adjacent cells.
c) A group of 6 adjacent cells. d) A group of 8 adjacent cells.
7. What is the shorter form of the function X ( a , b , c , d )   min (0,2,4,5,8,10,12,13) ?
a) X  c d  bc  b d b) X  bc  b d
c) X  c d  b d  bc d d) X  c  b d
8. A BCD to 7 segments decoder has 0100 on its inputs. The active outputs are…
a) a, c, f, g b) b, c, f, g
c) b, c, e, f d) b, d, e, g
9. Which one of the following statements is correct regarding a multiplexer?
a) with n selection inputs there are 2·n data inputs.
b) with 2n selection inputs there are n-1 data inputs.
c) with n selection inputs there are 2n data inputs.
d) with 2n selection inputs there are n data inputs.
10. A J-K Flip-Flop, with J=1, K=0 and a 10kHz clock input. The Q output is:
a) A constant high level. b) A constant low level.
c) A constant previous level. d) A 5kHz square wave.
11. A 4 bit asynchronous counter is made up of flip-flops whose propagation delay is 10ns. The
maximum clock frequency it could handle is:
a) 6,25 MHz b) 25 MHz c) 40 MHz d) 100 MHz
12. A 10MHz clock frequency is applied to a cascaded counter consisting of a module-5 counter, a
module-8 counter and two module-10 counters. The lowest frequency possible is:
a) 10kHz b) 2,5kHz c) 5kHz d) 25kHz
13. Spot the false statement considering an n-bit shift register?
a) It is made up of T Flip-Flops.
b) It can be used to implement counters.
c) It can store n-bit data words.
d) Cannot be made up of J-K Flip-Flops.
14. Spot the false statement.
a) Either static or dynamic RAMs are volatile memories.
b) Output Enable, Chip Enable and Write Enable are ROM control signals.
c) It takes four 256Kbyte-chips to build up a 1Mbyte memory bank
d) When data is read from RAM, the memory location is unchanged.
15. Spot the false statement.
a) In a computer, the address bus is a one way bus from the CPU.
b) Memories can store instructions or data.
c) The ports are connected to the data bus but not to the address bus.
d) The main advantage of the assembly language is that it is fast and efficient
16. How many bits do the data and the address bus have on a 64Kbyte RAM chip?
a) Data (8) Address (16) c) Data (8) Address (64)
b) Data (1) Address (16) d) Data (1) Address (64)
 EET ELECTRONIC SYSTEMS
DEE Problems
U PC
Partial exam. 11-04-2012
P1 (3 points)
Given the logic circuit in the following figure:
1.1 Fill in its truth table in a reasoned way.
A B C D
1.2 Implement the function:

X ( A, B, C , D)   min (0,2,4,5,6,8,10,12,13,14,15)

by means of an 8-channel multiplexer (74LS151)

1.3 Implement it by means of a 3-to-8 decoder, (74LS138).

U 2
U 1
1 15
4 A 5 A Y 0
D D 0 B Y 2 X 14
3 6 3 B Y 1 13
2 D 1 C Y C Y 2
D 2 12
1 6 Y 3 11
15 D 3 D G 1 Y 4
D 4 4 10
14 5 G 2A Y 5 9
13 D 5 G 2B Y 6
D 6 7
12 Y 7
D 7
11 74LS138
A A
10
B B
9
C C
7
G

74LS151

P2(3 points)
A displaying system for a packaging machine has to be
designed. The system will have 3 pulse inputs: START, to
Start
trigger a full cycle; BOX, to receive a pulse every time a new
empty box is available; and BOTTLE, to receive a pulse
Box
whenever a new bottle is ready. Every box will hold six bottles.
The one-digit display will show the number of bottles already
Bottle
placed in the current box. The two-digit display will show the
Done
number of boxes filled so far. Once 27 boxes had been filled, the
system will finish the process by setting the DONE output and going to an idle state, waiting for another
cycle to get started.
It is asked:
a) Full block diagram of the system and overall description of its working.
b) Design the modulus-6 and modulus-27 counters and clearly indicate all clock and reset signals.
Please hand in both problems separately. Thank you.