Digital Circuits: EE/CE 3320 / Spring 2020 / Lecture 11

Digital Circuits
EE/CE 3320 / Spring 2020 / Lecture 11

University of Texas Dallas
Dr. Tooraj Nikoubin Coding
EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 2
Binary-coded decimal
23 22 21 20
A B C D
BCD
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Binary-coded decimal
2 4 2 1 23 22 21 20
A B C D A B C D
Aiken BCD
A B C D A B C D
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 0 0 0 1
2 0 0 1 0 2 0 0 1 0
3 0 0 1 1 3 0 0 1 1
4 0 1 0 0 4 0 1 0 0
5 1 0 1 1 5 0 1 0 1
6 1 1 0 0 6 0 1 1 0
7 1 1 0 1 7 0 1 1 1
8 1 1 1 0 8 1 0 0 0
9 1 1 1 1 9 1 0 0 1
Aiken
A B C D
0 0 0 0 0 self-complementary
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 2 4 2 1
5 1 0 1 1 A B C D
6 1 1 0 0
7 1 1 0 1
8 1 1 1 0
9 1 1 1 1

Aiken
A B C D
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 2 4 2 1
5 1 0 1 1 A B C D
6 1 1 0 0
7 1 1 0 1
8 1 1 1 0
9 1 1 1 1

Aiken
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 2 4 2 1
5 1 0 1 1 A B C D
6 1 1 0 0
7 1 1 0 1
8 1 1 1 0
9 1 1 1 1

Aiken
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 2 4 2 1
5 1 0 1 1 A B C D
6 1 1 0 0
7 1 1 0 1
8 1 1 1 0
9 1 1 1 1

self-complementary
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0 2 4 2 1
5 1 0 1 1 A B C D
6 1 1 0 0
7 1 1 0 1
8 1 1 1 0
9 1 1 1 1

23 22 21 20
A B C D A B C D
Excess _3 BCD
A B C D A B C D
0 0 0 1 1 0 0 0 0 0
1 0 1 0 0 1 0 0 0 1
2 0 1 0 1 2 0 0 1 0
3 0 1 1 0 3 0 0 1 1
4 0 1 1 1 4 0 1 0 0
5 1 0 0 0 5 0 1 0 1
6 1 0 0 1 6 0 1 1 0
7 1 0 1 0 7 0 1 1 1
8 1 0 1 1 8 1 0 0 0
9 1 1 0 0 9 1 0 0 1

self-complementary
A B C D
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0

self-complementary
A B C D
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0

self-complementary
A B C D
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0

self-complementary
A B C D
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0

self-complementary
A B C D
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0

Johnson Code
A B C D
Johnson
A B C D E
0 0 0 0 0 0
1 0 0 0 0 1
2 0 0 0 1 1
3 0 0 1 1 1
4 0 1 1 1 1
5 1 1 1 1 1
6 1 1 1 1 0
7 1 1 1 0 0
8 1 1 0 0 0
9 1 0 0 0 0

2_Out_of_5
A B C D E
2_Out_of_5
A B C D E
0 1 1 0 0 0
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 0
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 1 0 0 0 1
8 1 0 0 1 0
9 1 0 1 0 0

Gray Code
Gray
A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 0 1 0
4 0 1 1 0
5 0 1 1 1
6 0 1 0 1
7 0 1 0 0
8 1 1 0 0
9 1 1 0 1
10 1 1 1 1
11 1 1 1 0
12 1 0 1 0
13 1 0 1 1
14 1 0 0 1
15 1 0 0 0
K_map for BCD, EX-3 and Aiken
BCD A Aiken
A 0 4 6 x
0 4 x 8 1 x 7 x
1 5 x 9 3 x 9
D
5
3 7 x
D C
x 2 x 8 x
C 2 6 x x
B
B
A
x 1 9 5
x 2 x 6
D
Ex-3 0 4 x 8
C x 3 x 7
B
Decimal to BCD Convertor
0 9 8 5 4 3 2 1 0
7 6
1
D
D
Decimal/BCD C
.......
convertor C
B
A B
9
A

1
0 9 8 6 5 4 3 2 1 0
7
1
D
D1
Decimal/BCD C
.......
convertor C1
B
A B1
9
A0

1
0 4 3 0
9 8 7 6 5 2 1
1
D
D1
Decimal/BCD C
.......
convertor C0
B
A B1
9
A0

1
0 9 8 5 4 3 2 1 0
7 6
1
D
D1
Decimal/BCD C
.......
convertor C0
B
A B0
9
A1

BCD to Decimal Convertor
0 9 8 7 6 5 4 3 2 1 0
D 1
C
.......
BCD/Decimal
Convertor D
B
C
A
9 B
A

0 0 0 0 1 0 0 0 0 0
0 9 8 7 6 5 4 3 2 1 0
D 1
C
.......
BCD/Decimal
Convertor D1
B
C0
A
9 B1
A0

0 9 8 7 6 5 4 3 2 1 0
D 1
C
.......
BCD/Decimal
Convertor D
B
C
A
9 B
A

Even Parity
Source Circuit Destination Circuit

Input and Output

Sample of Digital Circuit on the breadboard

Add in BCD code
A+ A3 A2 A1+
B B3 B2 B1

A+ A3 A2 A1+
B B3 B2 B1
b3 b2 b1 b0 a3 a2 a1 a0 b3 b2 b1 b0 a3 a2 a1 a0 b3 b2 b1 b0 a3 a2 a1 a0
4 bit F.A 4 bit F.A 4 bit F.A

A+ A3 A2 A1+
B B3 B2 B1
BCD Correction BCD Correction BCD Correction

A+ A3 A2 A1+
B B3 B2 B1
BCD/7Seg. BCD/7Seg. BCD/7Seg.

Convertor Convertor Convertor

A+ A3 A2 A1+
B B3 B2 B1

-- -- --

Add in BCD code

-- -- --

BCD/7Seg. Convertor
BCD/7Seg.
Convertor
--

7 Seg.
A B C D g f e d c b a
0 0 0 0 0 0 1 1 1 1 1 1
1 0 0 0 1 0 0 0 0 1 1 0
2 0 0 1 0 1 0 1 1 0 1 1
g
3 0 0 1 1 1 0 0 1 1 1 1
4 0 1 0 0 1 1 0 0 1 1 0
5 0 1 0 1 1 1 0 1 1 0 1
6 0 1 1 0 1 1 1 1 1 0 1
7 0 1 1 1 0 0 0 0 1 1 1
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 0 1 1 1 1

Design of BCD/7Seg. Convertor
a
f b
g
e c
d

A B C D a b c d e f g

0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1

0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
a = ∑ m (0, 2, 3, 5, 6, 7,8, 9) D
2 6 7 3
C X X X X
A
8 X X 9
0 4 5 1
B

D
a = ∑ m (0, 2, 3, 5, 6, 7,8, 9)
C X X X X
A
X X

D
a = ∑ m (0, 2, 3, 5, 6, 7,8, 9) 1 1 1 1
C X X X X
A
1 X X 1
1 1
B

D
a = C + A + B D + BD 1 1 1 1
C X X X X
A
1 X X 1
1 1
B

D
a = C + A + B D + BD
b = ∑ m (0,1, 3, 4, 7,8, 9) C X X X X
A
X X

D
a = C + A + B D + BD 1 1
b = ∑ m (0,1, 3, 4, 7,8, 9) C X X X X
A
1 X X 1
1 1 1
B

D
a = C + A + B D + BD 1 1
b =A + CD + C D + B D C X X X X
A
1 X X 1
1 1 1
B

D
a = C + A + B D + BD
A
c = ∑ m (0,1, 3, 4, 5, 6, 7,8) X X

D
a = C + A + B D + BD 1 1 1
A
c = ∑ m (0,1, 3, 4, 5, 6, 7,8) 1 X X
1 1 1 1
B

D
a = C + A + B D + BD 1 1 1
A
c =B + CD + C D + AC 1 X X
1 1 1 1
B

D
a = C + A + B D + BD
A
c =B + CD + C D + AC X X
d = ∑ m (0, 2, 3, 5, 6,8, 9)
B

D
a = C + A + B D + BD 1 1 1
A
c =B + CD + C D + AC 1 X X 1
d = ∑ m (0, 2, 3, 5, 6,8, 9) 1 1
B

D
a = C + A + B D + BD 1 1 1
A
c =B + CD + C D + AC 1 X X 1
d =A + C D + C B + B D + BC D 1 1
B

D
a = C + A + B D + BD
A
d = A + C D + C B + B D + BC D
e = ∑ m (0, 2, 6,8) B

D
a = C + A + B D + BD 1 1
A
c =B + CD + C D + AC 1 X X
d = A + C D + C B + B D + BC D 1
e = ∑ m (0, 2, 6,8) B

D
a = C + A + B D + BD 1 1
A
c =B + CD + C D + AC 1 X X
d =A + C D + C B + B D + BC D 1
B
e CD + B D
=

D
a = C + A + B D + BD
A
d =A + C D + C B + B D + BC D
B
e CD + B D
=
f = ∑ m (0, 4, 5, 6,8, 9)

D
a = C + A + B D + BD 1
A
c =B + CD + C D + AC 1 X X 1
d =A + C D + C B + B D + BC D 1 1 1
B
e CD + B D
=
f = ∑ m (0, 4, 5, 6,8, 9)

D
a = C + A + B D + BD 1
A
c =B + CD + C D + AC 1 X X 1
d =A + C D + C B + B D + BC D 1 1 1
B
=e CD + B D
f =A + BC + C D + B D

D
a = C + A + B D + BD
A
d =A + C D + C B + B D + BC D
B
=e CD + B D
f =A + BC + C D + B D
g = ∑ m (2, 3, 4, 5, 6,8)
D
a = C + A + B D + BD 1 1 1
A
c =B + CD + C D + AC 1 X X
d =A + C D + C B + B D + BC D 1 1
B
=e CD + B D
f =A + BC + C D + B D
g = ∑ m (2, 3, 4, 5, 6,8)
D
a = C + A + B D + BD 1 1 1
A
c =B + CD + C D + AC 1 X X
d =A + C D + C B + B D + BC D 1 1
B
=e CD + B D
f =A + BC + C D + B D
g = C B + B D + A D + BC
Add in BCD code

-- -- --

Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
b3 b2 b1b0 a3 a2 a1a0 0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
4 bit F.A 0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
Co S3 S2 S1 S0
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
b3 b2 b1b0 a3 a2 a1a0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
4 bit F.A 0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
Co S3 S2 S1 S0 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
b3 b2 b1b0 a3 a2 a1a0 0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
4 bit F.A 0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
Co S3 S2 S1 S0 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
b3 b2 b1b0 a3 a2 a1a0 0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
4 bit F.A 0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
Co S3 S2 S1 S0 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
b3 b2 b1b0 a3 a2 a1a0
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
4 bit F.A 0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
Co S3 S2 S1 S0 0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Co S3 S2 S1 S0 Co’ S3’ S2’ S1’ S0’
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
b3 b2 b1b0 a3 a2 a1a0 0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
4 bit F.A 0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
Co S3 S2 S1 S0 0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
+6 0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Add in BCD code
C0 S3 S2 S1 S0
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
Without correction
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1

Add in BCD code
C0 S3 S2 S1 S0
0 1 0 1 0
0 1 0 1 1
correction area
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

Add in BCD code
F=S3.S1
C0 S3 S2 S1 S0
0 1 0 1 0
0 1 0 1 1
correction area
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

Add in BCD code
F=S3.S1
C0 S3 S2 S1 S0 C0 S3 S2 S1 S0
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
correction area
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

Add in BCD code
F=S3.S1+S3.S2
C0 S3 S2 S1 S0 C0 S3 S2 S1 S0
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
correction area
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1

Add in BCD code
F=S3.S1+S3.S2+Co
C0 S3 S2 S1 S0 C0 S3 S2 S1 S0
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
correction area
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1

Add in BCD code
F=S3.S1+S3.S2+Co

Add in BCD code
B0 C0 A0
4bit-F.A
S 3 S 2 S1 S 0
F
0110
4bit-F.A

Design of BCD/Aiken Convertor
A B C D A' B' C' D'

0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 0 1 0 1 1 0 1 1
6 0 1 1 0 1 1 0 0
7 0 1 1 1 1 1 0 1
8 1 0 0 0 1 1 1 0
9 1 0 0 1 1 1 1 1
D
A ′ = ∑ m (5, 6, 7,8, 9)
C X X X X
A
X X

D
A ′ = ∑ m (5, 6, 7,8, 9) 1 1
C X X X X
A
1 X X 1
1
B

D
A ′ =A + CD + BD 1 1
C X X X X
A
1 X X 1
1
B

D
A ′ =A + CD + BD
C
B ′ = ∑ m (4, 6, 7,8, 9) X X X X
A
X X

D
A ′ =A + CD + BD 1 1
C
B ′ = ∑ m (4, 6, 7,8, 9) X X X X
A
1 X X 1
1
B

D
A ′ =A + CD + BD 1 1
C X X X X
B ′ =A + CD + B D A
1 X X 1
1
B

D
A ′ =A + CD + BD
C X X X X
B ′ =A + CD + B D A
X X
C ′ = ∑ m (2, 3, 5,8, 9)
B

D
A ′ =A + CD + BD 1 1
C X X X X
B ′ =A + CD + B D A
1 X X 1
C ′ = ∑ m (2, 3, 5,8, 9) 1
B

D
A ′ =A + CD + BD 1 1
C X X X X
B ′ =A + CD + B D A
1 X X 1
C′=A + BC + B C D 1
B

D
A ′ =A + CD + BD
C X X X X
B ′ =A + CD + B D A
X X
C′=A + BC + B C D
D ′ = ∑ m (1, 3, 5, 7, 9) B

D
A ′ =A + CD + BD 1 1
C X X X X
B ′ =A + CD + B D A
X X 1
C′=A + BC + B C D 1 1
D ′ = ∑ m (1, 3, 5, 7, 9) B
D
A ′ =A + CD + BD 1 1
C X X X X
B ′ =A + CD + B D A
X X 1
C′=A + BC + B C D 1 1
D′ = D B
Hamming with even parity for 4-bit date
p1
p1
p2
p2
A(3) A
A(3) A(3)
A p4
p4
B(5) B
B(5) B(5)
B
C(6) C
C(6) C(6)
C D(7) D
D(7) D(7)
D
c4 c2 c1
0
p4 p2 p1
1
0 2
DEC 3
1
3x8
2 4
A B C p1  ( 3, 5, 7) 7
0 0 0 m0
0 0 1 m1 p2  ( 3, 6, 7)
0 1 0 m2
Parity bit generator 0 1 1 m3
p4  ( 5, 6, 7)
1 0 0 m4 Parity bit checker and correction block
Source 1 0 1 m5 c1  ( 1, 3, 5, 7)
1 1 0 m6 c2  ( 2, 3, 6, 7) Destination
EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding
1 1 1 m7
c4  ( 4, 5, 6, 7) 103

Digital Circuits: EE/CE 3320 / Spring 2020 / Lecture 11

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Digital Circuits

EE/CE 3320 / Spring 2020 / Lecture 11

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 3

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 5

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EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 11

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EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 13

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EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 24

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Source Circuit Destination Circuit

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EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 37

4 bit F.A 4 bit F.A 4 bit F.A

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 38

4 bit F.A 4 bit F.A 4 bit F.A

BCD Correction BCD Correction BCD Correction

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 39

4 bit F.A 4 bit F.A 4 bit F.A

BCD Correction BCD Correction BCD Correction

BCD/7Seg. BCD/7Seg. BCD/7Seg.

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 40

4 bit F.A 4 bit F.A 4 bit F.A

BCD Correction BCD Correction BCD Correction

BCD/7Seg. BCD/7Seg. BCD/7Seg.

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 41

4 bit F.A 4 bit F.A 4 bit F.A

BCD Correction BCD Correction BCD Correction

BCD/7Seg. BCD/7Seg. BCD/7Seg.

EE/CE 3320 / DR. T.Nikoubin / Spring 2020 / Lecture 11/ Coding 42

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