Lab Manual

[VHDL LAB FOR VIth SEM E&C]
SITEC ELECTRONICS
# 13, 1ST Floor, Srinivas Theater Road,
Subramanyapura Post, Bangalore-560061
TeleFax: 91-80-26667618,Cell:9448367618
Email: sitec@vsnl.net, info@chipmaxasia.com
Web: www.chipmaxasia.com
VTU LAB MANUAL
(EC/TC)
Subject Code: EC/TC-L 68 IA marks: 25

Hours per week: 03 Exam Hours: 03
Total Hrs: 42 Exam Marks: 50
Note: Programming can be done using any VHDL compiler. Download the programs on a FPGA/CPLD board and
test performance using 16/32 channel pattern generator and logic analyzer apart from verification by simulation.
Use the pattern generator to generate input signal and truth tables.
PROGRAMMING
1. Write VHDL code to realize all the logic gates
2. Write a VHDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, demultiplexer, comparator
3. Write a VHDL code to describe the functions of a Full Adder Using following modeling styles,
4. Write a model for 32 bit ALU using the schematic diagram shown below.(example only)
A(31:0) B(31:0)
Opcode(3:0)
E bl
Out
ALU should use combinational logic to calculate an output based on the four bit op-code input
ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when
the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below
OPCODE ALU OPERATION

1. A+B
2. A-B
3. A Complement
4. A*B
5. A AND B
6. A OR B
7. A NAND B
8. A XOR B
5. Develop the VHDL codes for the following flip-flops,

SR, D, JK, T.
6. Design 4 bit binary, BCD counters (Synchronous reset and Asynchronous reset) and “any sequence”
counters
©Copyright Reserved 2
VTU LAB MANUAL
INTERFACING
1. Write VHDL code to display messages on the given seven segment display and LCD and accepting Hex key
pad input data.
2 Write a VHDL code to accept 8 channel Analog signal, Temperature sensors and display the data on LCD
panel or Seven segment display.
3. Write VHDL code to simulate elevator operations.
4. Write VHDL code to control external lights using relays.
5. Write VHDL codes to control speed, direction of DC and Stepper motor.
6. Write VHDL Code to generate different waveforms (Sine square Triangle, Ramp etc) using DAC change the
frequency and amplitude.
------------------------------------------------------------- -----------------------------------------------------------------
VTU LAB MANUAL
PREFACE
The semiconductor industry has been experiencing an unprecedented growth fuelled by

the developments in the VLSI industry.
The VLSI industry has already crossed the quarter-micron threshold and devices with 0.18
micron feature-size are already in market. Thus, it becomes extremely difficult to design
complex circuits with the help of conventional designing methods. The computer aided
design tools introduced serve the purpose.
We are very happy to see that VTU has introduced the VHDL Lab into its curriculum so
that students will be studying the emerging and ever-growing technology.
We expect this Manual will make all the students able to work from day one in the industry
and impart their knowledge to expand the information pool for a better life.
To realize the design, programmable logic devices such as CPLDs (Complex Programmable
Logic Devices) and FPGAs (Field Programmable Gate Arrays), come in very handy. Since
these devices are programmable, the user can modify their designs very easily and
conveniently.
This manual is prepared with a purpose of bring out the complete solution to cover the
whole syllabus of the VIth semester Electronics and Communication VHDL LAB as per VTU
Syllabus.
------------------------------------------------ ------------------------------------------------------
VTU LAB MANUAL
Lab manual for the above mentioned vhdl Experiments
Requirement
1.VHDL software with both front-end and backend (Design entry, synthesis, simulation,
implementation and programming.
2. FPGA kit with minimum 100,000 gate density
3.Interfacing cards like LCD,7-segment display, keyboard, ADC, DAC, Stepper Motor, DC Motor &
Relays.
4. Bit pattern generator cum Logic analyzer
Procedure.
Software part
1. Click on the Project navigator icon on the desktop of your PC. Write the vhdl code , check syntax,
perform the functional simulation using ModelsimXE. **
2. Open a new UCF file and lock the pins of the design with FPGA I/O pins.*
3. Implement the design by double clicking on the implementation tool selection.**
4. Check the implementation reports. **
5. Create programming file. **
Note :
* refer FPGA KIT user manual for I/O pins.
** refer ISE flow Manual
Hardware part
Lab session -1
Connect the FPGA kit to the parallel port of the PC through the cable provided along with the Kit.
Connect the FRC cable provided with the kit to the Bit Pattern generator and logic analyzer.
1.For all the combinational experiments

Use FRC1&FRC2 for sending bit patterns to FPGA (pattern generator) and use FRC3 &FRC4 for
receiving the logic from FPGA (logic Analysis).
2. For all sequential circuits

Use FRC 1 for sending bit patterns to FPGA (pattern generator) and use last input pin as the clock
for the design and connect it to the FPGA clock pin through the jumper provided on the Kit. Use FRC2
for receiving the logic from FPGA (logic Analysis).
Hardware part
Lab session -2
3. For interfacing the cards connect the required part of the interfacing card to the FRC connector
Provided on the FPGA kit.
FOR EXP1,3,5 USE GPIO CARD-01

FOR EXP2,4,6 USE GPIO CARD-02
VTU LAB MANUAL
Combinational Circuits
1-- VHDL code for all the basic Gates.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gates is
Port ( Ain : in std_logic; ---- First Input
Bin : in std_logic; ---- Second Input
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
end gates;
architecture Behavioral of gates is
begin
Op_not <= not Ain;
Op_or <= Ain or Bin;
Op_and <= Ain and Bin;
Op_nor <= Ain nor Bin;
Op_nand <= Ain nand Bin;
Op_xor <= Ain xor Bin;
Op_xnor <= Ain xnor Bin;
end Behavioral;
UCF file(User constraint file)
NET "Ain" LOC = "p74";
NET "Bin" LOC = "p75";
NET "Op_and" LOC = "p84";
NET "Op_nand" LOC = "p85";
NET "Op_nor" LOC = "p86";
NET "Op_not" LOC = "p87";
NET "Op_or" LOC = "p93";
NET "Op_xnor" LOC = "p94";
NET "Op_xor" LOC = "p95";
Device utilization summary:
---------------------------
Selected Device : 2s100tq144-6
Number of Slices: 1 out of 1200 0%
Number of 4 input LUTs: 2 out of 2400 0%
Number of bonded IOBs: 9 out of
VTU LAB MANUAL
2-- VHDL code for 2 to 4 Decoder, Synchronous with Enable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Decoder2_4 is
port ( Enable: in STD_LOGIC;
D_IN: in STD_LOGIC_VECTOR (1 downto 0); -- Two Bit Input for the Decoder
D_OUT: out STD_LOGIC_VECTOR (3 downto 0)); -- Four Bit Output for the Decoder
end Decoder2_4;
architecture Decoder_arc of Decoder2_4 is

begin
process (Enable,D_IN)
begin
if (Enable = '1') then

D_OUT <= "0000";
else
case D_IN is
when "00" => D_OUT <= "0001";
when "01" => D_OUT <= "0010";
when "10" => D_OUT <= "0100";
when "11" => D_OUT <= "1000";
when others => NULL;
end case;
end if;
end process;
end Decoder_arc;

NET "Enable" LOC = "p74";
NET "D_IN<0>" LOC = "p75";
NET "D_IN<1>" LOC = "p76";
NET "D_OUT<0>" LOC = "p84";
===============================================================
---------------------------------
Selected Device : 2s100tq144-5/-6
Number of Slices : 2 out of 1200 0%

Number of 4 input LUTs : 4 out of 2400 0%
Number of bonded IOBs : 7 out of 96 7%
===============================================================
VTU LAB MANUAL
3--VHDL code for 8 to 3 Encoder, Synchronous with Reset

library IEEE;
entity Encoder8_3 is
port ( ENABLE: in STD_LOGIC; --Enable Pin to Enable the Encoder

D_IN: in STD_LOGIC_VECTOR(7 downto 0); --Eight Input Lines of the Encoder
D_OUT: out STD_LOGIC_VECTOR(2 downto 0) ); --Three Output Lines of Encoder
end Encoder8_3;
architecture encoder_arch of encoder8_3 is

begin
process(ENABLE,D_IN)
begin
if ( ENABLE = '1') then
D_OUT <= "000";
Else
case D_IN is
when "00000001" => D_OUT <= "000";
when "00000010" => D_OUT <= "001";
when "00000100" => D_OUT <= "010";
when "00001000" => D_OUT <= "011";
when "00010000" => D_OUT <= "100";
when "00100000" => D_OUT <= "101";
when "01000000" => D_OUT <= "110";
when "10000000" => D_OUT <= "111";
end case;
end if;
end process;
end encoder_arch;

NET "Enable" LOC = "p74";
NET "D_IN<0>" LOC = "p75";
NET "D_IN<1>" LOC = "p76";
NET "D_IN<2>" LOC = "p78";
NET "D_IN<3>" LOC = "p77";
NET "D_IN<4>" LOC = "p80";
NET "D_IN<5>" LOC = "p79";
NET "D_IN<6>" LOC = "p83";
NET "D_IN<7>" LOC = "p112";
VTU LAB MANUAL
Synthesis Report
===============================================================
---------------------------

Number of Slice Flip Flops: 3 out of 2400 0%
Number of bonded IOBs: 12 out of 96 12%
===============================================================
VTU LAB MANUAL
4.-- VHDL code for 8:1 MUX
library IEEE;
entity Mux8_1 is
port ( SEL: in STD_LOGIC_VECTOR(2 downto 0); -- Select Lines
A,B,C,D,E,F,G,H :in STD_LOGIC; -- Inputs of the Mux.
MUX_OUT: out STD_LOGIC ); -- OutPut of the Mux.
end Mux8_1;
architecture mux4_1_arch of Mux8_1 is
begin
process (SEL,A,B,C,D,E,F,G,H)
begin
case SEL is
when "000" => MUX_OUT <= A;
when "001" => MUX_OUT <= B;
when "010" => MUX_OUT <= C;
when "011" => MUX_OUT <= D;
when "100" => MUX_OUT <= E;
when "101" => MUX_OUT <= F;
when "110" => MUX_OUT <= G;
when "111" => MUX_OUT <= H;
when others => null;
end case;
end process;
end mux4_1_arch;

NET "SEL<0>" LOC = "p74";
NET "A" LOC = "p78";

NET "B" LOC = "p77";
NET "C" LOC = "p80";
NET "D" LOC = "p79";
NET "E" LOC = "p83";
NET "F" LOC = "p112";
NET "G" LOC = "p114";
NET "H" LOC = "p113";
NET "MUX_OUT" LOC = "p84";

VTU LAB MANUAL
Synthesis Report
===============================================================
---------------------------
Selected Device : 2s100tq144-5 /-6

VTU LAB MANUAL
5.-- Code 4 bit binary to gray converter
library IEEE;
entity Binary_Gray is
port( a: in std_logic_vector(3 downto 0); --Binary Input

b: out std_logic_vector(3 downto 0)); --Gray Output
end binary_gray;
architecture behavioral of Binary_gray is

begin
b(3)<= a(3);
b(2)<= a(3) xor a(2);
b(1)<= a(2) xor a(1);
b(0)<= a(1) xor a(0);
end behavioral;

NET "a<0>" LOC = "p74";
NET "a<1>" LOC = "p75";
NET "a<2>" LOC = "p76";
NET "a<3>" LOC = "p78";
NET "b<0>" LOC = "p84";

NET "b<1>" LOC = "p85";
NET "b<2>" LOC = "p86";
NET "b<3>" LOC = "p87";
Synthesis Report
===============================================================
---------------------------

VTU LAB MANUAL
6.-- VHDL code for 1:4 DEMUX
library IEEE;
entity Demux1_4 is
port ( d_in: in STD_LOGIC; --Input For Demultiplexer
sel: in STD_LOGIC_VECTOR (1 downto 0); --Select Line of Demux
d_out: out STD_LOGIC_VECTOR (3 downto 0)); --Output Lines of Demux
end Demux1_4;
architecture demux1_4_arch of Demux1_4 is
begin
process(d_in,sel)
begin
d_out<="0000";
case sel is
when "00" => d_out(0)<=d_in;
when "01" => d_out(1)<=d_in;
when "10" => d_out(2)<=d_in;
when others => d_out(3)<=d_in;
end case;
end process;
end demux1_4_arch;

NET "SEL<0>” LOC = "p74";
NET "SEL<1>” LOC = "p75";
NET "d_in" LOC = "p76";
NET "d_out<0>" LOC = "p84";

Synthesis Report
===============================================================
---------------------------
VTU LAB MANUAL
7.-- Combinational VHDL Code for N Bit Comparator
library IEEE;
entity comparator is
Generic (N: integer := 3); --- Generalizing the Inputs
Port( A,B: in STD_LOGIC_VECTOR(N downto 0); -- Inputs for Comparison

ALB,AGB,AEB: out STD_LOGIC); -- Output Signals to show Less than, Greater than
-- or Equal.
end comparator;
architecture Comparator_arc of comparator is

begin
process(A,B)
begin
if ( A < B ) then ALB <= '1';
else ALB <= '0'; end if;
if ( A > B ) then AGB <= '1';

else AGB <= '0'; end if;
if ( A = B ) then AEB <= '1';

else AEB <= '0'; end if;
end process;
end Comparator_arc;
NET "A<0>" LOC = "p74";
NET "A<1>" LOC = "p75";
NET "A<2>" LOC = "p76";
NET "A<3>" LOC = "p78";
NET "B<0>" LOC = "p77";
NET "B<1>" LOC = "p80";
NET "B<2>" LOC = "p79";
NET "B<3>" LOC = "p83";
NET "ALB" LOC = "p84";

NET "AGB" LOC = "p85";
NET "AEB" LOC = "p86";
Synthesis Report
===============================================================
---------------------------
VTU LAB MANUAL
8a.--VHDL Code for the implementation of Half Adder
library IEEE;
entity Halfadder is
Port ( Ain, Bin : in std_logic; --2Bit Input
Sum, Carry : out std_logic);--sum& carry
end Halfadder;
architecture Behavioral of Halfadder is
begin
Sum <= Ain xor Bin;
Carry<= Ain and Bin;
end Behavioral;
8b.-- VHDL Code for Full Adder Using Component Instantiation Method.
library IEEE;
entity FullAdder is
Port ( Ain : in std_logic; --Input One
Bin : in std_logic; --Input Two
Cin : in std_logic; --Carry Input
Cout : out std_logic; --Carry Output
Sum : out std_logic); --Sum Output
end FullAdder;
architecture Behavioral of FullAdder is

-- Half Adder Component being Instantiated
Component Halfadder
Port ( Ain : in std_logic;
Bin : in std_logic;
Sum : out std_logic;
Carry : out std_logic);
end Component;
Signal temp1,temp2, temp3: std_logic; -- Signal Declaration
begin
VTU LAB MANUAL
-- Port Mapping of Component (By Positional Mapping Method)
L1: Halfadder port map( Ain, Bin,temp1,temp2);

L2: Halfadder port map( temp1,Cin,Sum,temp3);
Cout <= temp2 or temp3;

end Behavioral;

NET "Ain” LOC = "p74";
NET "Bin” LOC = "p75";
NET "Cin” LOC = "p76";
NET "Cout” LOC = "p84";

NET "Sum” LOC = "p85";
Synthesis Report
===============================================================
VTU LAB MANUAL
9.VHDL Code for 32 bit ALU Model.

-- This ALU is a combinational logic to calculate an out put Based on the four bit Op-code input.
-- ALU passes the result to the out bus when enable line is low.
library IEEE;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity ALU is
Port ( A : in std_logic_vector(15 downto 0); -- First Input
B : in std_logic_vector(15 downto 0); -- Second Input
Opcode : in std_logic_vector(2 downto 0); -- Op-code to select the operations
enb : in std_logic; -- Enable Signal
op : out std_logic_vector(15 downto 0)); -- Output of the ALU
end ALU;
architecture Behavioral of ALU is

begin
process(A,B,Opcode,enb)
begin
if enb= '1' then
case Opcode is
when "000" => op<= A+B;
when "001" => op<= A-B;
when "010" => op<= not A;
when "011" => op<= A*B;
when "100" => op<= A and B;
when "101" => op<= A or B;
when "110" => op<= A nand B;
when others => op<= A xor B;
end case;
else
op <= (others =>'Z');
end if;
end process;
end Behavioral;
VTU LAB MANUAL

NET "A<0>” LOC = "p74";
NET "A<1>” LOC = "p75";
NET "A<2>” LOC = "p76";
NET "A<3>” LOC = "p78";
NET "A<4>” LOC = "p77";
NET "A<5>” LOC = "p80";
NET "A<6>” LOC = "p79";
NET "A<7>” LOC = "p83";
NET "B<0>” LOC = "p112";

NET "B<1>” LOC = "p114";
NET "B<2>” LOC = "p113";
NET "B<3>” LOC = "p115";
NET "B<4>” LOC = "p117";
NET "B<5>” LOC = "p118";
NET "B<6>” LOC = "p121";
NET "B<7>” LOC = "p123";
NET "Opcode<0>” LOC = "p7";

NET "enb” LOC = "p141";
NET "op<0>” LOC = "p40";

NET "op<1>” LOC = "p41";
NET "op<2>” LOC = "p42";
NET "op<3>” LOC = "p48";
NET "op<4>” LOC = "p50";
NET "op<5>” LOC = "p51";
NET "op<6>” LOC = "p56";
NET "op<7>” LOC = "p57";
===============================================================
---Synthesis Report
---------------------------
Number of bonded IOBs: 100 out of 96 104% (*)
VTU LAB MANUAL
Sequential circuits
10.-- VHDL code for SR F/F

library IEEE;
entity SRFF is
port (
s: in bit; -- S Bit Input
r: in bit; -- R Bit Input
clk: in bit; -- Global Clock
q: buffer std_logic );
end SRFF;
architecture s_r_ff_arch of SRFF is
begin
process(clk)
begin
if clk='1' and clk'event then
if(s='0' and r='0')then q<=q;

elsif(s='0' and r='1')then q<='0';
elsif(s='1' and r='0')then q<='1';
elsif (s='1' and r='1')then q<='Z';
end if;
end if;
end process;
end s_r_ff_arch;

NET "s” LOC = "p74";
NET "r” LOC = "p75";
NET "clk” LOC = "p18";
NET "q” LOC = "p84";
========================================================
Synthesis Report
===============================================================
---------------------------
Number of GCLKs: 1 out of 4 25%
===============================================================
VTU LAB MANUAL
11.-- VHDL code for D F/F
library IEEE;
entity DFF is
port (
clk: in STD_LOGIC; --Global Clock as Input
d: in STD_LOGIC; -- Single bit Input
q: out STD_LOGIC ); -- Single bit output
end DFF;
architecture d_ff_arch of DFF is

begin
process(clk)
begin
if(clk'event and clk='1')then
q<=d;
end if;
end process;
end d_ff_arch;
NET "d” LOC = "p74";

Synthesis Report
===============================================================
---------------------------

VTU LAB MANUAL
12.-- VHDL code for JK F/F with async reset
library IEEE;
entity JKFF is
port (
clk : in BIT; -- Global Input Clock Signal.
J : in BIT; -- Single Bit Input J.
K : in BIT; -- Single Bit Input K.
Reset :in BIT; -- Global Input Reset Signal.
Q : buffer BIT ); -- Q as the Buffered Output.
end JKFF;
architecture jkff_arch of JKFF is

begin
process(clk,reset)
begin
if(reset='1')then
q<='0';
elsif(clk'event and clk='1')then
if(j='0' and k='0') then
q<=q;
elsif(j='0' and k='1') then
q<='0';
q<='1';
q<=not q;
end if;
end if;
end process;
end jkff_arch;
NET "j” LOC= "p74";

NET "k” LOC = "p75";
NET "Reset” LOC = "p76";
===============================================================
VTU LAB MANUAL
Synthesis Report
===============================================================
---------------------------

VTU LAB MANUAL
13.-- VHDL code for T F/F
library IEEE;
entity TFF is
port ( T: in STD_LOGIC; -- Input T
clk: in STD_LOGIC; -- Global Clock Signal
q: out STD_LOGIC ); -- Q Output
end TFF;
architecture t_ff_arch of TFF is

begin
process(clk)
begin
if(clk'event and clk='1')then

q<=not t;
end if;
end process;
end t_ff_arch;

NET "T” LOC= "p74";
--Synthesis Report
===============================================================
---------------------------
VTU LAB MANUAL
14.-- 4-bit synchronous counter

library IEEE;
entity sync_counter is
port( CLK: in STD_LOGIC; -- GLOBAL CLOCK SIGNAL
RESET: in STD_LOGIC; -- Global Reset Signal
COUNT: out STD_LOGIC_VECTOR( 3 DOWNTO 0)); --Counter Output
end sync_counter;
architecture counter_arch of sync_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);
begin
process (CLK)
begin
if CLK='1' and CLK'event then

if RESET='1' then --Synchronous reset
TEMP <= (OTHERS=>'0');
ELSE
TEMP <= TEMP + 1;
end if;
COUNT<= TEMP;
end if;
end process;
end counter_arch;

NET "RESET" LOC= "p74";
NET "CLK" LOC = "p18";
NET "COUNT<0>" LOC = "p84";

---Synthesis Report
===============================================================
---------------------------
VTU LAB MANUAL
15.-- 4-bit asynchronous counter
library IEEE;
entity async_counter is
port( CLK: in STD_LOGIC; -- GLOBAL CLOCK SIGNAL
RESET: in STD_LOGIC; -- Global Reset Signal
COUNT: out STD_LOGIC_VECTOR( 3 DOWNTO 0)); --Counter Output
end async_counter;
architecture counter_arch of async_counter is

signal TEMP:STD_LOGIC_VECTOR( 3 DOWNTO 0);
begin
process (CLK,RESET)
begin
if RESET='1' then --asynchronous reset

TEMP <= (OTHERS=>'0');
elsif CLK='1' and CLK'event then
TEMP <= TEMP + 1;
COUNT<= TEMP;
end if;
end process;
end counter_arch;

NET "RESET" LOC= "p74";
NET "CLK" LOC = "p18";
--Synthesis Report
===============================================================
---------------------------

VTU LAB MANUAL
INTERFACING
--Package for LCD Display (This Package must be added to display all the messages on LCD)
-- Package File Template

-- Purpose: This package defines supplemental types, subtypes, constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package LCD_GRAP is
-- THE NUMBERS
constant ONE : std_logic_vector(7 downto 0) := "00110001";
constant TWO : std_logic_vector(7 downto 0) := "00110010";
constant THREE : std_logic_vector(7 downto 0) := "00110011";
constant FOUR : std_logic_vector(7 downto 0) := "00110100";
constant FIVE : std_logic_vector(7 downto 0) := "00110101";
constant SIX : std_logic_vector(7 downto 0) := "00110110";
constant SEVEN : std_logic_vector(7 downto 0) := "00110111";
constant EIGHT : std_logic_vector(7 downto 0) := "00111000";
constant NINE : std_logic_vector(7 downto 0) := "00111001";
constant ZERO : std_logic_vector(7 downto 0) := "00110000";
-- THE CHARACTERS
constant A : std_logic_vector(7 downto 0) := "01000001";

constant B : std_logic_vector(7 downto 0) := "01000010";
constant C : std_logic_vector(7 downto 0) := "01000011";
constant D : std_logic_vector(7 downto 0) := "01000100";
constant E : std_logic_vector(7 downto 0) := "01000101";
constant F : std_logic_vector(7 downto 0) := "01000110";
constant G : std_logic_vector(7 downto 0) := "01000111";
constant H : std_logic_vector(7 downto 0) := "01001000";
constant I : std_logic_vector(7 downto 0) := "01001001";
constant J : std_logic_vector(7 downto 0) := "01001010";
constant K : std_logic_vector(7 downto 0) := "01001011";
constant L : std_logic_vector(7 downto 0) := "01001100";
constant M : std_logic_vector(7 downto 0) := "01001101";
constant N : std_logic_vector(7 downto 0) := "01001110";
constant O : std_logic_vector(7 downto 0) := "01001111";
constant P : std_logic_vector(7 downto 0) := "01010000";
constant Q: std_logic_vector(7 downto 0) := "01010001";
constant R : std_logic_vector(7 downto 0) := "01010010";
constant S : std_logic_vector(7 downto 0) := "01010011";
constant T : std_logic_vector(7 downto 0) := "01010100";
constant U : std_logic_vector(7 downto 0) := "01010101";
constant V : std_logic_vector(7 downto 0) := "01010110";
constant W : std_logic_vector(7 downto 0) := "01010111";
constant X : std_logic_vector(7 downto 0) := "01011000";
constant Y : std_logic_vector(7 downto 0) := "01011001";
constant Z : std_logic_vector(7 downto 0) := "01011010";
VTU LAB MANUAL
-- SMAL LETTERS
constant SA : std_logic_vector(7 downto 0) := "01100001";
constant SB : std_logic_vector(7 downto 0) := "01100010";
constant SC : std_logic_vector(7 downto 0) := "01100011";
constant SD : std_logic_vector(7 downto 0) := "01100100";
constant SE : std_logic_vector(7 downto 0) := "01100101";
constant SF : std_logic_vector(7 downto 0) := "01100110";
constant SG : std_logic_vector(7 downto 0) := "01100111";
constant SH : std_logic_vector(7 downto 0) := "01101000";
constant SI : std_logic_vector(7 downto 0) := "01101001";
constant SJ : std_logic_vector(7 downto 0) := "01101010";
constant SK : std_logic_vector(7 downto 0) := "01101011";
constant SL : std_logic_vector(7 downto 0) := "01101100";
constant SM : std_logic_vector(7 downto 0) := "01101101";
constant SN : std_logic_vector(7 downto 0) := "01101110";
constant SO : std_logic_vector(7 downto 0) := "01101111";
constant SP : std_logic_vector(7 downto 0) := "01110000";
constant SQ : std_logic_vector(7 downto 0) := "01110001";
constant SR : std_logic_vector(7 downto 0) := "01110010";
constant SS : std_logic_vector(7 downto 0) := "01110011";
constant ST : std_logic_vector(7 downto 0) := "01110100";
constant SU : std_logic_vector(7 downto 0) := "01110101";
constant SV : std_logic_vector(7 downto 0) := "01110110";
constant SW : std_logic_vector(7 downto 0) := "01110111";
constant SX : std_logic_vector(7 downto 0) := "01111000";
constant SY : std_logic_vector(7 downto 0) := "01111001";
constant SZ : std_logic_vector(7 downto 0) := "01111010";
---THE SYMBOLS
constant SPACE: std_logic_vector(7 downto 0) := "00100000";
constant SLASH: std_logic_vector(7 downto 0) := "00101111";
constant MINUS: std_logic_vector(7 downto 0) := "00101101";
constant EQUAL: std_logic_vector(7 downto 0) := "00111101";
constant PLUS : std_logic_vector(7 downto 0) := "00101011";
constant STAR : std_logic_vector(7 downto 0) := "00101010";
constant DOT : std_logic_vector(7 downto 0) := "00101110";
end LCD_GRAP;
VTU LAB MANUAL
1a.Write VHDL code to display messages on the given LCD accepting Hex key pad input data.
Aim: To Display the message on the LCD panel by accepting HEX key board data as input.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD Display connector of the
VTU card1.
2. Make the connection between FRC4 of the FPGA board to the Key board connector of the
VTU card1.
3. Make the connection between FRC6 of the FPGA board to the Dip switch connector of the
VTU card1.
4. Connect the downloading cable and power supply to the FPGA board
5. Then open the Xilinx iMPACT software (refer ISE flow) select the slave serial mode and
select the respective BIT file and click program.
6. Make the reset switch on (active low).
7. Press the HEX keys and analyze the data.
VHDL CODING
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
USE WORK.LCD_GRAP.ALL;
entity HEXKEY_lcd is
port (
CLK: in STD_LOGIC; -- 16 MHz clock
RESET: in STD_LOGIC; -- master reset pin
lcd_rw : out std_logic;
lcd_select : out std_logic;
lcd_enable : out std_logic;
ROW: in STD_LOGIC_VECTOR(0 to 3); -- this are the row lines
lcd_data: out STD_LOGIC_VECTOR (7 downto 0); -- gives registered data output
COL: inout STD_LOGIC_VECTOR(0 to 3));
end HEXKEY_lcd;
architecture HEXKEY_BEH of HEXKEY_lcd is

type KEYPAD_STATE_TYPE is (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); --
state names
TYPE STATE_TYPE IS (initial,display,clear,location,putchar);
SIGNAL state,next_state: STATE_TYPE;
VTU LAB MANUAL
-- Clear screen.
constant CLR: std_logic_vector(7 downto 0) := "00000001";
-- Display ON, without cursor.
constant DON: std_logic_vector(7 downto 0) := "00001100";
-- Function set for 8-bit data transfer and 2-line display
constant SET: std_logic_vector(7 downto 0) := "00111000";
--frequency divider
constant big_delay: integer :=16;

constant small_delay: integer :=2;
constant reg_setup: integer :=1;
signal CS, NS: KEYPAD_STATE_TYPE; -- signals for current and next states
signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register
signal DCLK,DDCLK: STD_LOGIC; -- this has the divided clock.
signal COL_REG_VALUE: STD_LOGIC_VECTOR (0 to 3);
signal R1: STD_LOGIC; -- row detection signal
signal KEY_VALUE: STD_LOGIC_VECTOR (7 downto 0);
signal DATA: STD_LOGIC_VECTOR (7 downto 0);
begin
R1 <= ROW(3) or ROW(2) or ROW(1) or ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) ------------------------------------
SYNC_PROC: process (DCLK, RESET, KEY_VALUE) -- This is the synchronous part

begin
if (RESET = '0') then -- you must have a reset for fsm to synthesize properly
CS <= WAIT_R_0;
elsif (DCLK'event and DCLK = '1') then
CS <= NS;
end if;
end process;
COMB_PROC: process (CS, R1, COL_REG_VALUE) -- This is the combinational part

begin
case CS is
---------------------------------------------------------------------------------------------------
when WAIT_R_0 => -- waits till a button is pressed
COL <= "1111"; -- keep all columns activated
if R1 = '1' then -- a button was pressed. but which one?
NS <= C3; -- let's find out
else
NS <= WAIT_R_0;
end if;
---------------------------------------------------------------------------------------------------
when C3 => --
COL <= "0001"; -- activate column 3
if R1 = '0' then -- this means button was not in column 3
NS <= C2; -- so check if it was in column 2
VTU LAB MANUAL
Else NS <= FOUND; -- button was in column 3
end if;
---------------------------------------------------------------------------------------------------
when C2 => --
else
NS <= FOUND; -- button was in column 2
end if;
---------------------------------------------------------------------------------------------------
when C1 => --
else
end if;
---------------------------------------------------------------------------------------------------
when C0 => --
if R1 = '0' then -- this means button was not in column 0 ??
NS <= WAIT_R_0; -- so the button must have been depressed fast
else
end if;
---------------------------------------------------------------------------------------------------
when FOUND => --
COL <= COL_REG_VALUE;
if R1 = '0' then -- this means button is depressed
NS <= WAIT_R_0; -- so go back to initial state
else
NS <= SAMPLE; -- otherwise write the key value to DATA register
end if;
---------------------------------------------------------------------------------------------------
when SAMPLE => -- this state will generate a signal with one clock period for sampling
NS <= WAIT_R_1; -- otherwise wait till button is pressed
---------------------------------------------------------------------------------------------------
when WAIT_R_1 => --
if R1 = '0' then -- this means button was depressed
else
end if;
---------------------------------------------------------------------------------------------------
end case;
end process;
---------------------------------------------------------------------------------------------------
VTU LAB MANUAL
WRITE_DATA: process (DCLK, CS, KEY_VALUE) -- write valid data to register
begin
if DCLK'event and DCLK = '0' then -- on the falling edge
if CS = FOUND then
DATA <= KEY_VALUE;
end if;
end if;
end process; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: process (DCLK, CS, COL) -- this is the column value register
begin
if (DCLK'event and DCLK = '0') then -- register the COL value on the falling edge
if (CS = C3 or CS = C2 or CS = C1 or CS = C0) then -- provided we're in states C3 thru C0 only
COL_REG_VALUE <= COL; -- otherwise the column value is not valid
end if;
end if;
end process; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: process(ROW, COL_REG_VALUE) -- decodes binary value of pressed key from row and
column
variable CODE: STD_LOGIC_VECTOR (0 to 7);
begin
CODE := (ROW & COL_REG_VALUE);
case CODE is
-- COL
-- ROW 0 0123
when "00010001" => KEY_VALUE <= ZERO;--key 0
when "00010010" => KEY_VALUE <= ONE;--key 1
when "00010100" => KEY_VALUE <= TWO;--key 2
when "00011000" => KEY_VALUE <= THREE;--key 3
-- ROW 1
when "00100001" => KEY_VALUE <= FOUR;--key 4
when "00100010" => KEY_VALUE <= FIVE;--key 5
when "00100100" => KEY_VALUE <= SIX;--key 6
when "00101000" => KEY_VALUE <= SEVEN;--key 7
-- ROW 2
when "01000001" => KEY_VALUE <= EIGHT;--key 8
when "01000010" => KEY_VALUE <= NINE;--key 9
when "01000100" => KEY_VALUE <= A;--key A
when "01001000" => KEY_VALUE <= B;--key B
-- ROW 3
when "10000001" => KEY_VALUE <= C;--key C
when "10000010" => KEY_VALUE <= D;--key D
when "10000100" => KEY_VALUE <= E;--key E
when "10001000" => KEY_VALUE <= F;--key F
when others => KEY_VALUE <= SPACE; -- just in case
end case;
end process; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) -----------------------------------------
VTU LAB MANUAL
-- select the appropriate lines for setting frequency

CLK_DIV: process (CLK, DIV_REG) -- clock divider
begin
if (CLK'event and CLK='1') then
DIV_REG <= DIV_REG + 1;
end if;
end process;
DCLK <= div_reg(8);
DDCLK<=DIV_REG(10);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
lcd_rw<='0';
process (DDclk,rEsEt)
variable count: integer range 0 to big_delay;
variable c1 : std_logic_vector(7 downto 0);
begin
IF rEsEt = '0' THEN
state<=initial;
count:=0;
lcd_enable<='0';
lcd_select<='0';
c1 := "01111111";
elsIF DDclk'EVENT AND DDclk = '1' THEN
case state is
WHEN initial => -- to set the function
if count=reg_setup then
lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=SET;
lcd_select<='0';
if count=small_delay then
state<=display;
count:=0;
else
count:=count+1;
end if;
WHEN display => -- to set display on
lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=DON;
lcd_select<='0';
state<=clear;count:=0;
else
count:=count+1;
VTU LAB MANUAL
end if;
WHEN clear => -- clear the screen
lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=CLR;
lcd_select<='0';
if count=big_delay then
state<=location;
count:=0;
else
count:=count+1;
end if;
WHEN location => -- clear the screen

lcd_enable<='1';
else
lcd_enable<='0';
end if;
IF COUNT=0 THEN
if c1="10001111" then
c1:="11000000";
elsif c1="11001111" then
c1:="10000000";
else
c1:=c1+'1';
end if;
END IF;
lcd_data <= c1 ;
lcd_select<='0';
state<=putchar;
count:=0;
else
count:=count+1;
end if;
when putchar=> -- display the character on the LCD

lcd_enable<='1';
else
lcd_enable<='0';
end if;
case c1 is
VTU LAB MANUAL
when "10000000" => lcd_data<= H ;--SIGLE LINE
when "10000001" => lcd_data<= E ;--SIGLE LINE
when "10000010" => lcd_data<= X ;--SIGLE LINE
when "10000011" => lcd_data<= SPACE ;--SIGLE LINE
when "10000101" => lcd_data<= K ;--SIGLE LINE
when "10000111" => lcd_data<= Y ;--SIGLE LINE
when "10001000" => lcd_data<= B ;
when "10001001" => lcd_data<= O ;
when "10001010" => lcd_data<= A ;
when "10001011" => lcd_data<= R ;
when "10001100" => lcd_data<= D ;
when "10001101" => lcd_data<= SPACE ;
when "10001111" => lcd_data<= SPACE;
when "11000000" => lcd_data<= K ;--SIGLE LINE

when "11000010" => lcd_data<= Y ;--SIGLE LINE
when "11000011" => lcd_data<= P ;--SIGLE LINE
when "11000100" => lcd_data<= R ;--SIGLE LINE
when "11000110" => lcd_data<= S ;--SIGLE LINE
when "11001000" => lcd_data<= E ;
when "11001001" => lcd_data<= D ;
-- when "11001011" => lcd_data<= RIGHT_ARROW ;
when "11001101" => lcd_data<= DATA ;
WHEN OTHERS => NULL;
end case ;
lcd_select<='1';
state<=location;
count:=0;
else
count:=count+1;
end if;
end case;
end if;
end process;
end HEXKEY_BEH;
VTU LAB MANUAL

NET "CLK" LOC = "P18" ;
NET "COL<0>" LOC = "P139" ;
NET "COL<1>" LOC = "P134" ;
NET "COL<2>" LOC = "P136" ;
NET "COL<3>" LOC = "P132" ;
NET "lcd_data<0>" LOC = "P21" ;
NET "lcd_enable" LOC = "P19" ;
NET "lcd_rw" LOC = "P20" ;
NET "lcd_select" LOC = "P4" ;
NET "RESET" LOC = "P41" ;
NET "ROW<0>" LOC = "P126" ;
NET "ROW<1>" LOC = "P129" ;
NET "ROW<2>" LOC = "P124" ;
NET "ROW<3>" LOC = "P122" ;

---------------------------
Selected Device : 2s100tq144-5/6

=========================================================================
VTU LAB MANUAL
1b. Write VHDL code to display messages on the given seven segment display accepting Hex key
pad input data.
Aim: To Display the message on the Seven Segment Display by accepting HEX key pad input
Data.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the Seven Segment connector of
the VTU card1.
2. Make the connection between FRC4 of the FPGA board to the Key board connector of the
VTU card1.
VTU card1.
4. Connect the downloading cable and power supply to the FPGA board.
VHDL CODING
------------------------------------
--Code for simulating 16 keys using
--keyboard provided on spartan board
------------------------------------
library IEEE;
entity key_40 is
Port ( scan_l : out std_logic_vector(3 downto 0);
read_l_in : in std_logic_vector(3 downto 0);
clk : in std_logic;
disp_cnt: out std_logic_vector(3 downto 0);
disp : out std_logic_vector(6 downto 0));
end key_40;
architecture Behavioral of key_40 is

signal disp1 : std_logic_vector(6 downto 0);
signal scan_l_sig : std_logic_vector(3 downto 0);
signal clk_div : std_logic_vector( 11 downto 0);
signal clk_4k : std_logic;
signal cnt_2bit : std_logic_vector(1 downto 0);
signal read_l : std_logic_vector(3 downto 0);
VTU LAB MANUAL
begin
---------------------------
--clock division to 4kHz
--------------------------
process(clk)
begin
clk_div <= clk_div + '1';
end if;
end process;
---------------------------
clk_4k <= clk_div(11);
---------------------------
-- 2 bit counter
--------------------------
process(clk_4k)
begin
if clk_4k = '1' and clk_4k'event then
cnt_2bit <= cnt_2bit + '1';
end if;
end process;
--------------------------
-- scanning the lines
--------------------------
process(cnt_2bit)
begin
case cnt_2bit is
when "00" => scan_l_sig <= "0001";
when "01" => scan_l_sig <= "0010";
when "10" => scan_l_sig <= "0100";
when "11" => scan_l_sig <= "1000";
when others => null;
end case;
end process;
------------------------------
--read_l <= not read_l_in;
--scan_l <= not scan_l_sig;
read_l <= read_l_in;
scan_l <= scan_l_sig;
disp_cnt <= "1110";
--reading the lines
-------------------------------
VTU LAB MANUAL
process(scan_l_sig,read_l)
begin
case scan_l_sig is
when "0001" => case read_l is
when "0001" => disp1 <= "1111110";
when "0010" => disp1 <= "0110011";
when "0100" => disp1 <= "1111111";
when "1000" => disp1 <= "1001110";
when others=> disp1 <= "0000000";
end case;

when "0001" => disp1 <= "0110000";
when "0010" => disp1 <= "1011011";
when "0100" => disp1 <= "1111011";
when "1000" => disp1 <= "0111101";
end case;

when "0001" => disp1 <= "1101101";
when "0010" => disp1 <= "1011111";
when "0100" => disp1 <= "1110111";
when "1000" => disp1 <= "1001111";
end case;

when "0001" => disp1 <= "1111001";
when "0010" => disp1 <= "1110000";
when "0100" => disp1 <= "0011111";
when "1000" => disp1 <= "1000111";
end case;
when others=> null;

end case;
end process;
disp<= disp1;
end Behavioral;
VTU LAB MANUAL
-------------------------------------------------------------------------------------------------------------------------------
NET "clk" LOC = "p18";

NET "disp_cnt<0>" LOC = "p30";
NET "disp<0>" LOC = "p26";
NET "read_l_in<0>" LOC = "p122";
NET "scan_l<0>" LOC = "p132";

---------------------------
Selected Device : 2s100tq144-5/6

=========================================================================
VTU LAB MANUAL
2a. Write a VHDL code to accept 8 channel Analog signal, Temperature sensors and display the
data on LCD panel or Seven segment display.
Aim: To accept 8 channel Analog signal, and display the data on LCD panel display.
.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the LCD Display connector of
the VTU card1.
2. Make the connection between FRC10 of the FPGA board to the ADC connector of the
VTU card1.
VTU card1.
4. Short the Jumper J1 to the Vin to get the analog signal.
VHDL CODING
Library IEEE;
Library UNISIM;
use UNISIM.vcomponents.all;
entity ADC_lcd is
port ( CLK: in STD_LOGIC; -- 4 MHz clock
intr: in std_logic;
adc_out: in std_logic_vector(7 downto 0);
cs,rd,wr:out std_logic;
VTU LAB MANUAL
lcd_data: out STD_LOGIC_VECTOR (7 downto 0)); -- gives registered data output
end ADC_lcd;
architecture ADC_BEH of ADC_lcd is

-- Clear screen.
--frequency divider
signal counter : std_logic_vector(18 downto 0);
signal clk_div :std_logic;

signal digital_data1,data1,data2: std_logic_vector(7 downto 0);
signal digital_data : integer range 0 to 255;
signal ntr :std_logic;
begin
IBUF_inst : IBUF
-- Edit the following generic to specify the I/O standard for this port.
generic map (
IOSTANDARD => "LVCMOS25")
port map (
O => ntr, -- Buffer output
I => intr -- Buffer input (connect directly to top-level port));
process(clk)
begin
counter<=counter+'1';
end if;
end process;
clk_div<=counter(7);
cs <='0';
wr <=ntr;
digital_data1 <= adc_out ;
rd <='0';
digital_data<=CONV_INTEGER(digital_data1) ;
process(digital_data)
VTU LAB MANUAL
begin
case (digital_data) is
when 0 to 100 => data1 <= one ; data2 <= nine ;
when 101 to 110 => data1 <= two ; data2 <= zero ;
when 111 to 120 => data1 <= two ; data2 <= one ;
when 121 to 130 => data1 <= two ; data2 <= two ;
when 131 to 140 => data1 <= two ; data2 <= three ;
when 141 to 150 => data1 <= two ; data2 <= four ;
when 151 to 160 => data1 <= two ; data2 <= five ;
when 161 to 170 => data1 <= two ; data2 <= six ;
when 171 to 180 => data1 <= two ; data2 <= seven ;
when 181 to 190 => data1 <= two ; data2 <= eight ;
when 191 to 200 => data1 <= two ; data2 <= nine ;
when 201 to 205 => data1 <= three ; data2 <= zero ;
when 206 to 210 => data1 <= three ; data2 <= one ;
when 211 to 215 => data1 <= three ; data2 <= two ;
when 216 to 220 => data1 <= three ; data2 <= three ;
when 221 to 225 => data1 <= three ; data2 <= four ;
when 226 to 230 => data1 <= three ; data2 <= five ;
when 231 to 235 => data1 <= three ; data2 <= six ;
when 236 to 240 => data1 <= three ; data2 <= seven ;
when 241 to 245 => data1 <= three ; data2 <= eight ;
when 246 to 250 => data1 <= three ; data2 <= nine ;
when others => data1 <= four ; data2 <= zero ;
end case;
end process;
lcd_rw<='0';
process (clk_div,rEsEt)
begin
IF rEsEt = '1' THEN
state<=initial;
count:=0;
lcd_enable<='0';
lcd_select<='0';
c1 := "01111111";
elsIF clk_div'EVENT AND clk_div = '1' THEN
case state is

lcd_enable<='1';
else
lcd_enable<='0';
end if;
VTU LAB MANUAL
lcd_data<=SET;
lcd_select<='0';
state<=display;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=DON;
lcd_select<='0';
state<=clear;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=CLR;
lcd_select<='0';
state<=location;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
IF COUNT=0 THEN
if c1="10001111" then
c1:="10000000";
else
VTU LAB MANUAL
c1:=c1+'1';
end if;
END IF;
lcd_data <= c1 ;
lcd_select<='0';
state<=putchar;
count:=0; else
count:=count+1;
end if;

lcd_enable<='1';
else lcd_enable<='0';
end if;
case c1 is
when "10000000" => lcd_data<= A ;
when "10000001" => lcd_data<= D ;
when "10000010" => lcd_data<= C ;
when "10000100" => lcd_data<= V ;
when "10000101" => lcd_data<= O ;
when "10000110" => lcd_data<= L ;
when "10000111" => lcd_data<= T ;
when "10001000" => lcd_data<= A ;
when "10001001" => lcd_data<= G ;
when "10001010" => lcd_data<= E ;
when "10001100" => lcd_data<= EQUAL ;
when "10001101" => lcd_data<= data1 ;
when "10001110" => lcd_data<= Dot ;
when "10001111" => lcd_data<= data2;
when "11000000" => lcd_data<= space ;
when "11000010" => lcd_data<= space;
VTU LAB MANUAL
end case ;
lcd_select<='1';
state<=location;
count:=0;
else
count:=count+1;
end if;
end case;
end if;
end process;
end ADC_BEH;
NET "RESET" LOC = "p40" ;

NET "CLK" LOC = "p18" ;
NET "cs" LOC = "p6" ;
NET "intr" LOC = "p12" ;
NET "adc_out<0>" LOC = "p13" ;
NET "wr" LOC = "p11";
NET "rd" LOC = "p10";
NET "lcd_rw" LOC = "p20";
NET "lcd_select" LOC = "p4";
NET "lcd_enable" LOC = "p19" ;
NET "lcd_data<0>" LOC = "p21" ;
Device utilization summary:---------------------------
VTU LAB MANUAL
2b. Write a VHDL code to accept 8 channel Analog signal, Temperature sensors and display the
data on LCD panel or Seven segment display.
Aim: To accept Temperature sensors, and display the data on LCD panel display.
.
Procedure:
the VTU card1.
2. Make the connection between FRC10 of the FPGA board to the ADC connector of the
VTU card1.
VTU card1.
4. Short the Jumper J1 to the TC to sense the temperature.
VHDL CODING
Library IEEE;
Library UNISIM;
entity temp_lcd is
intr: in std_logic;
adc_out: in std_logic_vector(7 downto 0);
cs,rd,wr:out std_logic;
VTU LAB MANUAL
lcd_data: out STD_LOGIC_VECTOR (7 downto 0)); -- gives registered data output
end temp_lcd;
architecture temp_BEH of temp_lcd is

-- Clear screen.
--frequency divider
signal counter : std_logic_vector(18 downto 0);
signal clk_div :std_logic;
--signal c: std_logic_vector(7 downto 0);

signal digital_data1,data1,data2: std_logic_vector(7 downto 0);
signal digital_data : integer range 0 to 255;
signal ntr :std_logic;
begin
IBUF_inst : IBUF
-- Edit the following generic to specify the I/O standard for this port.
generic map (
IOSTANDARD => "LVCMOS25")
port map (
O => ntr, -- Buffer output
I => intr -- Buffer input (connect directly to top-level port));
process(clk)
begin
counter<=counter+'1';
end if;
end process;
clk_div<=counter(7);
cs <='0';
wr <=ntr;
digital_data1 <= adc_out ;
rd <='0';
digital_data<=CONV_INTEGER(digital_data1) ;
process(digital_data)
begin
VTU LAB MANUAL
case (digital_data) is
when 0 to 60 => data1 <= zero ; data2 <= nine ;
when 61 to 65 => data1 <= one ; data2 <= zero ;
when 66 to 70 => data1 <= one ; data2 <= one ;
when 71 to 75 => data1 <= one ; data2 <= two ;
when 76 to 80 => data1 <= one ; data2 <= three ;
when 81 to 85 => data1 <= one ; data2 <= four ;
when 86 to 90 => data1 <= one ; data2 <= five ;
when 91 to 95 => data1 <= one; data2 <= six ;
when 96 to 100 => data1 <= one ; data2 <= seven ;
when 101 to 105 => data1 <= one ; data2 <= eight ;
when 106 to 110 => data1 <= one ; data2 <= nine ;
when 111 to 115 => data1 <= two ; data2 <= zero ;
when 116 to 120 => data1 <= two ; data2 <= one ;
when 121 to 125 => data1 <= two ; data2 <= two ;
when 126 to 130 => data1 <= two ; data2 <= three ;
when 131 to 135 => data1 <= two ; data2 <= four ;
when 136 to 140 => data1 <= two ; data2 <= five ;
when 141 to 145 => data1 <= two ; data2 <= six ;
when 146 to 150 => data1 <= two ; data2 <= seven ;
when 151 to 155 => data1 <= two ; data2 <= eight ;
when 156 to 160 => data1 <= two ; data2 <= nine ;
when 161 to 165 => data1 <= three ; data2 <= zero ;
when 166 to 170 => data1 <= three ; data2 <= two ;
when 171 to 175 => data1 <= three ; data2 <= three ;
when 176 to 180 => data1 <= three ; data2 <= four ;
when 181 to 185 => data1 <= three ; data2 <= five ;
when 186 to 190 => data1 <= three ; data2 <= six ;
when 191 to 195 => data1 <= three ; data2 <= seven ;
when 196 to 200 => data1 <= three ; data2 <= eight ;
when 201 to 205 => data1 <= three ; data2 <= nine ;
when 206 to 210 => data1 <= four ; data2 <= zero ;
when 211 to 214 => data1 <= four ; data2 <= one ;
when 215 to 219 => data1 <= four ; data2 <= two ;
when 220 to 224 => data1 <= four ; data2 <= three ;
when 225 to 229 => data1 <= four ; data2 <= four ;
when 230 to 234 => data1 <= four ; data2 <= five;
when 235 to 239 => data1 <= four ; data2 <= six ;
when 240 to 244 => data1 <= four ; data2 <= seven ;
when 245 to 249 => data1 <= four ; data2 <= eight;
when 250 to 255 => data1 <= four; data2 <= nine ;
when others => data1 <= five ; data2 <= zero ;
end case;
end process;
lcd_rw<='0';
process (clk_div,rEsEt)
begin
VTU LAB MANUAL
IF rEsEt = '1' THEN
state<=initial;
count:=0;
lcd_enable<='0';
lcd_select<='0';
c1 := "01111111";
elsIF clk_div'EVENT AND clk_div = '1' THEN
case state is
lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=SET;
lcd_select<='0';
state<=display;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=DON;
lcd_select<='0';
state<=clear;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
lcd_data<=CLR;
lcd_select<='0';
state<=location;
count:=0;
else
VTU LAB MANUAL
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
IF COUNT=0 THEN
if c1="10001111" then
c1:="10000000";
else
c1:=c1+'1';
end if;
END IF;
lcd_data <= c1 ;
lcd_select<='0';
state<=putchar;
count:=0;
else
count:=count+1;
end if;

lcd_enable<='1';
else
lcd_enable<='0';
end if;
case c1 is
when "10000000" => lcd_data<= T ;
when "10000001" => lcd_data<= E ;
when "10000010" => lcd_data<= M ;
when "10000011" => lcd_data<= P ;
when "10000100" => lcd_data<= E ;
when "10000101" => lcd_data<= R ;
when "10000110" => lcd_data<= A ;
when "10000111" => lcd_data<= T ;
when "10001000" => lcd_data<= U ;
when "10001001" => lcd_data<= R ;
when "10001010" => lcd_data<= E ;
VTU LAB MANUAL
when "10001111" => lcd_data<= C;
end case;
lcd_select<='1';
state<=location;
count:=0;
else
count:=count+1;
end if;
end case;
end if;
end process;
end temp_BEH;
VTU LAB MANUAL

NET "cs" LOC = "p6" ;

NET "intr" LOC = "p12" ;
NET "wr" LOC = "p11";
NET "rd" LOC = "p10";
NET "lcd_rw" LOC = "p20";

NET "lcd_select" LOC = "p4";
NET "lcd_enable" LOC = "p19" ;

=========================================================================
---------------------------

VTU LAB MANUAL
3. Write a VHDL code to simulate Elevator operations.
Aim: To operate elevator and observe the simulation results on LCD.

.
Procedure:
the VTU card1.
2. Make the connection between FRC1 of the FPGA board to the Keyboard connector of the
VTU card1.
VTU card1.
VHDL CODING
Library IEEE;
entity elevator is
generic(bits : integer := 8 ); -- number of bits used for duty cycle.
-- Also determines pwm period.
RESET,EN: in STD_LOGIC; -- master reset pin
pwm : out std_logic_VECTOR(1 DOWNTO 0);
ROW: in STD_LOGIC_VECTOR(0 to 3); -- this are the row lines
lcd_data: out STD_LOGIC_VECTOR (7 downto 0); -- gives registered data output
COL: inout STD_LOGIC_VECTOR(0 to 3));
end elevator;
VTU LAB MANUAL
architecture rtl of elevator is
signal counter : std_logic_vector(bits - 1 downto 0):="00000000";
type KEYPAD_STATE_TYPE is (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1);
-- state names
-- Clear screen.
--frequency divider

signal CS, NS: KEYPAD_STATE_TYPE; -- signals for current and next states
signal duty_cycle,duty_cycle1 : std_logic_vector(bits - 1 downto 0);
signal DCLK,DDCLK: STD_LOGIC; -- this has the divided clock.
signal COL_REG_VALUE: STD_LOGIC_VECTOR (0 to 3);
signal R1,CLK_D,START,STOP: STD_LOGIC; -- row detection signal
signal KEY_VALUE1,FLOOR,KEY_VALUE: integer range 0 to 15;
signal DATA,data1,FLOOR_NUM: STD_LOGIC_VECTOR (7 downto 0);
signal TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 downto 0);
signal TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 downto 0);
begin
--CLK_OUT <= DCLK;
R1 <= ROW(3) or ROW(2) or ROW(1) or ROW(0);
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) ------------------------------------
SYNC_PROC: process (DCLK, RESET, KEY_VALUE) -- This is the synchronous part
begin
if (RESET = '0') then -- you must have a reset for fsm to synthesize properly
CS <= WAIT_R_0;
elsif (DCLK'event and DCLK = '1') then
CS <= NS;
end if; end process;
COMB_PROC: process (CS, R1, COL_REG_VALUE) -- This is the combinational part
begin
case CS is
when WAIT_R_0 => -- waits till a button is pressed
COL <= "1111"; -- keep all columns activated
if R1 = '1' then -- a button was pressed. but which one?
NS <= C3; -- let's find out
else
VTU LAB MANUAL
NS <= WAIT_R_0;
end if;
---------------------------------------------------------------------------------------------------
when C3 => --
Else NS <= FOUND; -- button was in column 3
end if;
---------------------------------------------------------------------------------------------------
when C2 => --
else
end if;
---------------------------------------------------------------------------------------------------
when C1 => --
else
end if;
---------------------------------------------------------------------------------------------------
when C0 => --
if R1 = '0' then -- this means button was not in column 0 ??
NS <= WAIT_R_0; -- so the button must have been depressed fast
else
end if;
---------------------------------------------------------------------------------------------------
when FOUND => --
if R1 = '0' then -- this means button is depressed
else
NS <= SAMPLE; -- otherwise write the key value to DATA register
end if;
---------------------------------------------------------------------------------------------------
when SAMPLE => -- this state will generate a signal with one clock period for sampling
---------------------------------------------------------------------------------------------------
when WAIT_R_1 => --
if R1 = '0' then -- this means button was depressed
VTU LAB MANUAL
else
end if;
---------------------------------------------------------------------------------------------------
end case;
end process;
---------------------------------------------------------------------------------------------------
WRITE_DATA: process (DCLK, CS, KEY_VALUE) -- write valid data to register
begin
if DCLK'event and DCLK = '0' then -- on the falling edge
if CS = FOUND then
KEY_VALUE <= KEY_VALUE1;
end if;
end if;
end process; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: process (DCLK, CS, COL) -- this is the column value register
begin
if (DCLK'event and DCLK = '0') then -- register the COL value on the falling edge
if (CS = C3 or CS = C2 or CS = C1 or CS = C0) then -- provided we're in states C3 thru C0 only
COL_REG_VALUE <= COL; -- otherwise the column value is not valid
end if;
end if;
end process; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: process(ROW, COL_REG_VALUE) -- decodes binary value of pressed key from row and
column
variable CODE: STD_LOGIC_VECTOR (0 to 7);
begin
CODE := (ROW & COL_REG_VALUE);
case CODE is
-- COL
-- ROW 0 0123
when "00010001" => KEY_VALUE1 <= 0;
when "00010010" => KEY_VALUE1 <= 1;
when "00010100" => KEY_VALUE1 <= 2;
when "00011000" => KEY_VALUE1 <= 3;
-- ROW 1
when "00100001" => KEY_VALUE1 <= 4;
when "00100010" => KEY_VALUE1 <= 5;
when "00100100" => KEY_VALUE1 <= 6;
when "00101000" => KEY_VALUE1 <= 7;
-- ROW 2
when "01000001" => KEY_VALUE1 <= 8;
when "01000010" => KEY_VALUE1 <= 9;
when "01000100" => KEY_VALUE1 <= 10;
when "01001000" => KEY_VALUE1 <= 11;
-- ROW 3
VTU LAB MANUAL
when "10000001" => KEY_VALUE1 <= 12;
when "10000010" => KEY_VALUE1 <= 13;
when "10000100" => KEY_VALUE1 <= 14;
when "10001000" => KEY_VALUE1 <= 15;
when others => KEY_VALUE1 <= 0;
end case;
end process; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) -----------------------------------------
begin
end if;
end process;
DCLK <= div_reg(8);
DDCLK<=DIV_REG(10);
CLK_D<=DIV_REG(22);
lcd_rw<='0';
process (DDclk,rEsEt)
begin
IF rEsEt = '0' THEN
state<=initial;
count:=0;
lcd_enable<='0';
lcd_select<='0';
c1 := "01111111";
elsIF DDclk'EVENT AND DDclk = '1' THEN
case state is
lcd_enable<='1';
end if;
lcd_data<=SET;
lcd_select<='0';
state<=display;
count:=0;
else count:=count+1;
end if;

lcd_enable<='1';
end if;
VTU LAB MANUAL
lcd_data<=DON;
lcd_select<='0';
state<=clear;
count:=0;
end if;

lcd_enable<='1';
end if;
lcd_data<=CLR;
lcd_select<='0';
state<=location;
count:=0;
end if;

lcd_enable<='1';
end if;
IF COUNT=0 THEN
if c1="10001111" then
c1:="11000000";
elsif c1="11001111" then
c1:="10000000";
else c1:=c1+'1';
end if;
END IF;
lcd_data <= c1;

lcd_select<='0';
state<=putchar;
count:=0;
end if;

lcd_enable<='1';
end if;
case c1 is
VTU LAB MANUAL
when "10000000" => lcd_data<= F ;--SIGLE LINE
when "10000001" => lcd_data<= L ;--SIGLE LINE
when "10000010" => lcd_data<= O ;--SIGLE LINE
when "10000011" => lcd_data<= O ;--SIGLE LINE
when "10000100" => lcd_data<= R ;--SIGLE LINE
when "10000110" => lcd_data<= N ;--SIGLE LINE
when "10000111" => lcd_data<= U ;--SIGLE LINE
when "10001000" => lcd_data<= M ;
when "10001001" => lcd_data<= B ;
when "10001010" => lcd_data<= E ;
when "10001011" => lcd_data<= R ;
when "10001110" => lcd_data<= FLOOR_NUM ;

when "11000001" => lcd_data<= T ;--SIGLE LINE
when "11000010" => lcd_data<= A ;--SIGLE LINE
when "11000011" => lcd_data<= T ;--SIGLE LINE
when "11000100" => lcd_data<= U ;--SIGLE LINE
when "11000111" => lcd_data<= TEMP1 ;--SIGLE LINE
when "11001000" => lcd_data<= TEMP2 ;
end case ;
lcd_select<='1';
state<=location;
count:=0;
end if; end case; end if; end process;
PROCESS(CLK_D,RESET)
VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE START,STOP: STD_LOGIC; -- row detection signal
BEGIN
IF RESET='0' THEN
COU:="00";
TEMP1 <= L ;
VTU LAB MANUAL
TEMP2 <= I ;
TEMP3 <= F ;
TEMP4 <= T ;
TEMP5 <= I ;
TEMP6 <= D ;
TEMP7 <= L ;
TEMP8 <= E ;
FLOOR_NUM <= ZERO ;
ELSIF RISING_EDGE(CLK_D) THEN
CASE KEY_VALUE IS
WHEN 0 => FLOOR_NUM <= ZERO ;
FLOOR <=0;
WHEN 1 => FLOOR_NUM <= ONE ;
FLOOR <=1;
WHEN 2 => FLOOR_NUM <= TWO ;
FLOOR <=2;
WHEN 3 => FLOOR_NUM <= THREE ;
FLOOR <=3;
WHEN 4 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= O ;
TEMP6 <= P ;
TEMP7 <= E ;
TEMP8 <= N ;
WHEN 5 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= C ;
TEMP6 <= L ;
TEMP7 <= O ;
TEMP8 <= S ;
WHEN 6 =>
START:='1';
STOP:='0';
WHEN 7 =>
STOP:='1';
START:='0';
WHEN OTHERS =>
TEMP1 <= I ;
TEMP2 <= D ;
TEMP3 <= L ;
TEMP4 <= E ;
TEMP5 <= K ;
TEMP6 <= E ;
VTU LAB MANUAL
TEMP7 <= Y ;
TEMP8 <= SPACE ;
END CASE;
IF START='1' THEN
IF COU=FLOOR THEN
START := '0';
COU:=COU;
TEMP7 <= "001100" & COU ;
ELSIF COU<=FLOOR THEN
COU:=COU + '1';
TEMP1 <= U ;
TEMP2 <= P ;
TEMP3 <= SPACE ;
TEMP4 <= SPACE ;
TEMP5 <= SPACE ;
TEMP6 <= "01111110" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
ELSIF COU>=FLOOR THEN
COU:=COU-'1';
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= W ;
TEMP4 <= N ;
TEMP5 <= SPACE ;
TEMP6 <= "01111111" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
END IF; END IF; END IF;
END PROCESS;
end rtl;
VTU LAB MANUAL
UCF file(User constraint File)
NET "CLK" LOC = "P18" ;

NET "RESET" LOC = "P40" ;
NET "COL<0>" LOC = "P83" ;

NET "COL<1>" LOC = "P79" ;
NET "COL<2>" LOC = "P80" ;
NET "COL<3>" LOC = "P77" ;
NET "ROW<0>" LOC = "P78" ;
NET "ROW<1>" LOC = "P76" ;
NET "ROW<2>" LOC = "P75" ;
NET "ROW<3>" LOC = "P74" ;
NET "lcd_enable" LOC = "P19" ;

NET "lcd_rw" LOC = "P20" ;
NET "lcd_select" LOC = "P4" ;
=========================================================================
---------------------------

=========================================================================
VTU LAB MANUAL
4. Write a VHDL code to control external lights using relays.
Aim: To control external lights using relays.

.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the External light connector of
the VTU card2.
VTU card2.
5. Make the reset switch on (active low) and analyze the data.
VHDL CODING
library IEEE;
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is

begin
light<= cntrl1 OR cntrl2 ;
end Behavioral;
UCF file(User constraint

NET "cntrl1" LOC = "P74";
NET "cntrl2" LOC = "P75";
NET "light" LOC = "P7";
=========================================================================
---------------------------
VTU LAB MANUAL
5a. Write a VHDL code to control speed, direction of DC motor.
Aim: To control Speed and Direction of DC motor.

.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the DC motor connector of
the VTU card2.
VTU card2.
VTU card2.
7. Press the HEX keys and analyze the speed changes.
VHDL CODING
Library IEEE;
Library UNISIM;
entity dcmotor is
generic(bits : integer := 8 );-- number of bits used for duty cycle.
-- Also determines pwm period.
RESET,EN: in STD_LOGIC; -- master reset pin
pwm : out std_logic_VECTOR(1 DOWNTO 0);
rly: out std_logic;
ROW: in STD_LOGIC_VECTOR(0 to 3) ); -- this are the row lines
end dcmotor;
architecture dcmotor1 of dcmotor is

signal counter : std_logic_vector(bits - 1 downto 0):="11111110";
signal DCLK,DDCLK,datain,tick: STD_LOGIC; -- this has the divided clock.
VTU LAB MANUAL
signal duty_cycle: integer range 0 to 255;
signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines
begin
begin
end if;
end process;
DDCLK<=DIV_REG(12);
tick <= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when "1110" => duty_cycle <= 255 ; --motor speed 1
when others => duty_cycle <= 100;
end case;
end if;
end process;
process(DDCLK, reset)
begin
if reset = '0' then
counter <= (others => '0');
PWM<="01";
elsif (DDCLK'event and DDCLK = '1') then
counter <= counter + 1;
if counter >= duty_cycle then
pwm(1) <= '0';
else
pwm(1) <= '1';
end if; end if;
end process;
-- rly<='1'; --motor direction control- clock wise
rly<='0';--motor direction control- counter clock wise
end dcmotor1;
VTU LAB MANUAL

NET "pwm<0>" LOC = "p5" ;

NET "pwm<1>" LOC = "p141" ;
NET "rly" LOC = "p3" ;
NET "ROW<0>" LOC = "p64" ;

NET "ROW<1>" LOC = "p63" ;
NET "ROW<2>" LOC = "p60" ;
NET "ROW<3>" LOC = "p58" ;
=========================================================================
---------------------------

VTU LAB MANUAL
5b. Write a VHDL code to control speed, direction of Stepper motor.
Aim: To control Speed and Direction of Stepper motor.

.
Procedure:
1. Make the connection between FRC9 of the FPGA board to the Stepper motor connector of
the VTU card2.
VTU card2.
VTU card2.
7. Press the HEX keys and analyze the speed changes.
VHDL CODING
library IEEE;
entity STEPPER is
Port ( dout : out std_logic_vector(3 downto 0);
clk,reset : in std_logic);
end STEPPER;
architecture Behavioral of STEPPER is

signal clk_div : std_logic_vector(20 downto 0);
signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
VTU LAB MANUAL
end if;
end process;
clk_int <= clk_div(16);

process(reset,clk_int)
begin
if reset='0' then
shift_reg <= "0001";
elsif rising_edge(clk_int) then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
end if;
end process;
dout <= shift_reg;
end Behavioral;

NET "clk" LOC = "P18";
NET "dout<0>" LOC = "P7";
NET "reset" LOC = "P74";
=========================================================================
---------------------------

=========================================================================
VTU LAB MANUAL
6.a. Write a VHDL code to generate Sine waveforms using DAC change the frequency and
amplitude.
Aim: To generate Sine wave using DAC change the frequency and amplitude.
.
Procedure:
1. Make the connection between FRC5 of the FPGA board to the DAC connector of
the VTU card2.
VTU card2.
VHDL CODING
library IEEE;
entity digital_sine_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end digital_sine_wave ;
architecture Behavioral of digital_sine_wave is

signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
VTU LAB MANUAL
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter <= counter + 31 ;
en<='0';
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter - 31;
end if;
end if;
end process;
dac_out <=counter;
end Behavioral;

NET "clk" LOC = "p18" ;
NET "dac_out<0>" LOC = "p27" ;
NET "rst" LOC = "p74" ;

---------------------------

=========================================================================
VTU LAB MANUAL
6.b. Write a VHDL code to generate Square waveforms using DAC change the frequency and
amplitude.
Aim: To generate Square wave using DAC change the frequency and amplitude.
.
Procedure:
the VTU card2.
VTU card2.
VHDL CODING
library IEEE;
entity square_wave is
rst : in std_logic;
end square_wave;
architecture Behavioral of square_wave is

begin
process(clk)
begin
end if;
end process;
VTU LAB MANUAL
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
if counter<255 and en='0' then
en<='0';
dac_out <="00000000";
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter-1;
dac_out <="11111111";
end if;
end if;
end process;
end Behavioral;


---------------------------

=========================================================================
VTU LAB MANUAL
6.c. Write a VHDL code to generate Traingular waveforms using DAC change the frequency and
amplitude.
Aim: To generate Triangular wave using DAC change the frequency and amplitude.
.
Procedure:
the VTU card2.
VTU card2.
VHDL CODING
library IEEE;
entity triangular_wave is
rst : in std_logic;
end triangular_wave ;
architecture Behavioral of triangular_wave is

begin
process(clk)
begin
end if;
end process;
process(temp(3))
begin
VTU LAB MANUAL
if rst='1' then
counter <= "000000000";

if counter(0)='1' then
dac_out <=counter(1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;
end if;
end process;
end Behavioral;


---------------------------

=========================================================================
VTU LAB MANUAL
6.d. Write a VHDL code to generate Ramp waveforms using DAC change the frequency and
amplitude.
Aim: To generate Ramp wave using DAC change the frequency and amplitude.
.
Procedure:
the VTU card2.
VTU card2.
VHDL CODING
library IEEE;
entity ramp_wave is
rst : in std_logic;
end ramp_wave;
architecture Behavioral of ramp_wave is

begin
process(clk)
begin
end if;
end process;
VTU LAB MANUAL
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
end if;
end process;
dac_out <=counter;
end Behavioral;


---------------------------

=========================================================================
VTU LAB MANUAL
6.e. Write a VHDL code to generate Sawtooth waveforms using DAC change the frequency and
amplitude.
Aim: To generate Sawtooth wave using DAC change the frequency and amplitude.
.
Procedure:
the VTU card2.
VTU card2.
VHDL CODING
library IEEE;
entity swatooth_wave is
rst : in std_logic;
end swatooth_wave;
architecture Behavioral of swatooth_wave is

begin
process(clk)
begin
end if;
end process;
VTU LAB MANUAL
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
end if;
end process;
dac_out <=counter;
end Behavioral;


---------------------------

=========================================================================
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[VHDL LAB FOR VIth SEM E&C]

Subject Code: EC/TC-L 68 IA marks: 25

OPCODE ALU OPERATION

5. Develop the VHDL codes for the following flip-flops,

3. Write VHDL code to simulate elevator operations.

4. Write VHDL code to control external lights using relays.

5. Write VHDL codes to control speed, direction of DC and Stepper motor.

The semiconductor industry has been experiencing an unprecedented growth fuelled by

Lab manual for the above mentioned vhdl Experiments

1.For all the combinational experiments

2. For all sequential circuits

FOR EXP1,3,5 USE GPIO CARD-01

1-- VHDL code for all the basic Gates.

-- Uncomment the following lines to use the declarations that are

2-- VHDL code for 2 to 4 Decoder, Synchronous with Enable.

architecture Decoder_arc of Decoder2_4 is

if (Enable = '1') then

UCF file(User constraint file)

Number of Slices : 2 out of 1200 0%

3--VHDL code for 8 to 3 Encoder, Synchronous with Reset

port ( ENABLE: in STD_LOGIC; --Enable Pin to Enable the Encoder

architecture encoder_arch of encoder8_3 is

UCF file(User constraint file)

Number of Slices: 7 out of 1200 0%

4.-- VHDL code for 8:1 MUX

architecture mux4_1_arch of Mux8_1 is

UCF file(User constraint file)

NET "A" LOC = "p78";

NET "MUX_OUT" LOC = "p84";

Number of Slices: 2 out of 1200 0%

5.-- Code 4 bit binary to gray converter

port( a: in std_logic_vector(3 downto 0); --Binary Input

architecture behavioral of Binary_gray is

UCF file(User constraint file)

NET "b<0>" LOC = "p84";

Number of Slices: 2 out of 1200 0%

6.-- VHDL code for 1:4 DEMUX

architecture demux1_4_arch of Demux1_4 is

UCF file(User constraint file)

NET "d_out<0>" LOC = "p84";

Port( A,B: in STD_LOGIC_VECTOR(N downto 0); -- Inputs for Comparison

architecture Comparator_arc of comparator is

if ( A > B ) then AGB <= '1';

if ( A = B ) then AEB <= '1';

NET "ALB" LOC = "p84";

8a.--VHDL Code for the implementation of Half Adder

architecture Behavioral of Halfadder is

architecture Behavioral of FullAdder is

-- Port Mapping of Component (By Positional Mapping Method)

L1: Halfadder port map( Ain, Bin,temp1,temp2);

Cout <= temp2 or temp3;

UCF file(User constraint file)

NET "Cout” LOC = "p84";

9.VHDL Code for 32 bit ALU Model.

architecture Behavioral of ALU is

UCF file(User constraint file)

NET "B<0>” LOC = "p112";

NET "Opcode<0>” LOC = "p7";

NET "op<0>” LOC = "p40";

10.-- VHDL code for SR F/F

architecture s_r_ff_arch of SRFF is

if clk='1' and clk'event then

if(s='0' and r='0')then q<=q;