PHY340 : ELECTRONICS

LABORATORY REPORT
GROUP : AS1204-E

LECTURER’S NAME : SIR RAFAEL JULIUS

DATE OF SUBMISSION : 14/12/2018

NAME STUDENT NUMBER

NUR AIN NAZURAH BINTI MOHD NOOR 2016789305

SITI FAUZIAH BINTI ABU BAKAR 2016798839

SITI SURAINI BINTI AHMAD 2016107743

NOR SYAZWANI BINTI SHAHNUN 2016975079

SEPT 18/JAN 19
Experiment 1: Basic Logic Gates

Objective:

To study the truth table of various basic logic gate.

Materials required:

1) Hex Inverter IC (7404) – 1

2) Quad 2 Inputs AND gate IC (7408) – 1
3) Quad 2 Inputs OR gate IC (7432) – 1
4) Digital logic trainer –1

Procedure:

Part A: AND Gate

1) The AND gate circuit have connected in Figure 1.1.

2) The power supply was turned ON.
3) Both input were set up to the ‘0’ level and observe the LED output.
4) The output for the various inputs combinations were recorded as shown in Table 1.
5) The power supply was turned OFF.

Part B: OR Gate

1) The OR gate circuit was connected as shown in Figure 1.2.

2) The power supply was turned ON.
3) The Table 2 was completed recorded.
4) The power supply was turned OFF.

Part C: NOT Gate or Inverter

1) The inverter circuit was connected as shown in Figure 1.3

2) The power supply was turned ON.
3) The Table 3 was completed recorded.
4) The power supply was turned OFF.
Part D: Gate Conversions

1) The circuit was connected as shown in Figure 1.4

2) The power supply was turned ON.
3) The Table 4 was completed recorded.
4) The power supply was turned OFF.
5) The circuit was connected as shown in Figure 1.5.
6) The power supply was turned ON.
7) The Table 5 was completed recorded.
8) The power supply was turned .
AND Gate
OR Gate
NOT Gate or Inverter
Gate Conversions
Results :
Table 1:
INPUTS OUTPUTS

A B X=A.B

0 0 0

0 1 0

1 0 0

1 1 1

Table 2:
INPUTS OUTPUTS

A B X=A+B

0 0 0

0 1 1

1 0 1

1 1 1

Table 3:
INPUTS OUTPUTS

A X = inverse A

0 1

1 0
Table 4:
INPUTS OUTPUTS

A B X

0 0 1

0 1 1

1 0 1

1 1 0

Table 5:
INPUTS OUTPUTS

A B X

0 0 1

0 1 0

1 0 0

1 1 0
Questions
1.The output of an AND gate will be high if none of its inputs is/are high.
2. The output of an OR gate will be low if both of its input is/are high.
3. The logic equation for a 3-inputs AND gate is Y = A.B.C
4. The logic equation for a 4-inputs OR gate is Y = A + B + C + D
5. The output of the logic circuit shown below is Y = inverse A
6. The NAND gate is formed by inverting the inputs and output of an AND gate.
7. The NOR gate is formed by inverting the inputs and output of an OR gate.
8. The power supply voltage for TTL ICs is typically 5 volts.
9.Show the output waveform of the OR gate shown below.

10.Show the output waveform of the AND gate shown below.

Discussion

In this experiment, the implementation of universal gates in logic circuits has been
made. There are two functions required to observe and F1 is in the SOP form while F2 is in the
POS form. In electronics, a logic gate is an idealized or physical device implementing a Boolean
function that performs a logical operation on one or more binary inputs and produces a single
binary output. There are four variables which is A, B, C and D or in other words, four inputs that
carry out in their 16 possible combinations by connecting toggle switches for each and one
toggle switch that was always on to represent each of combinations output.The power supply
voltage that required for TTL ICs is typically 5 volts. The circuit diagram composed mainly
of the AND, OR and an inverter logic gate for each of the two functions and listed every output
voltages we measured from the VOM. The ICs that required for AND and OR gate are 7404 and
7408 respectively. The inverter are required in order to prove why the NAND and NOR gates are
so called universal gates. The previous diagrams were converted into circuits that were
composed mainly of NAND and NOR gates and followed the same procedure. In the first circuit
the Sum of Products form (SOP) and therefore can be easily implemented using NAND gates.
Thus, a equivalent circuit using NAND gates only was constructed. Then, in the second circuit it
can be easily seen that it is in Product of Sums form (POS) and therefore it can be easily
implemented using NOR gates. Then, the corresponding output voltages were measured for each
of the combinations and compared it with computed or expected values. The results were exactly
the same as what had been obtained from the first procedure.After the experiment, it can say that
using Universal gates the implement any gate like AND,OR and NOT, or any combination of
these basic gates and obtained the same output. This experiment also proved that its most
important advantage compared to circuits using basic gates, and that is it minimizes the logic ICs
being used. Therefore NAND and NOR gates really deserves for its title as the Universal gates.
Conclusion
As the conclusion, each basic gate works in their own unique way, which is proved
during this experiment. The truth table were used to examine the operation of the basic logic gate.
It is proved from experiment that logic gates work in basis of Boolean Algebra.

References

1. Advances in Electronics and Electron Physics, Volume 49, L Marton and C Marton, New
York London Toronto Sydney San Fransisco.

2. The fields of electronics: understanding electronics using basic physics, Ralph Morrison, John
Wiley & Sons, 2002.

3. Foundations of Analog and Digital Electronic Circuits, by Anant Agarwal, Jeffrey Lang,
Derise E.M. Penrose.

4. How to Use a Breadboard!, by Sean Michael Ragan, Jody Culkin

5. Complete Digital Design, by Mark Balch.

EXPERIMENT 2 : NAND & OR Gates

Objective :

1. To determined output of NAND Gate

2. To determined output of NOR Gate
3. To determined output for Gate Conversion

Materials Required:

 Hex Inverter IC (7404) –1

 Quad input NAND gate IC (7400) –1
 Quad input NOR gate IC (7402) –1
 Digital logic trainer -1

Part A: NAND Gate

A 1

3 X = AB to logic indicator

B 2

Fig. 2-1

Procedure:

1. 2 input NAND gate circuit was connected as shown in Fig. 2-1.

2. The power supply was turned ON.
3. The input of switches was setup to each of the 4 possible states and the output was recorded in
table 1.
4. The power supply was turned OFF.

Table 1

INPUTS OUTPUTS

A B X = AB
0 0 1
0 1 1
1 0 1
 1 1 0

PART A
Part B: NOR gate

A 2 1

x= A+B to logic indicator

B 3

Fig. 2-1

Procedure:

1. The 2 input NOR gate circuit was connected as shown in Fig.2-2.

2. The power supply was turned ON.
3. Table 2 was completed.
4. The power supply was turned OFF.

Table 2

INPUTS OUTPUTS

A B X = A+B
0 0 1
0 1 0
1 0 0
1 1 0
PART B
Part C: Gate Conversion

A 1

from data 8 10 X to logic indicator

switches 4 9 9

B 5

Fig. 2-3

A 1 3

2 9

from data 8 X to logic indicator

switches 4 10

Fig. 2-4

Procedure:

1. The circuit was connected as shown in Fig. 2-3

2. The power supply was turned ON.
3. Table 3 was completed.
4. The power supply was turned OFF.
5. The circuit was connected as shown in Fig.2-4.
 6. The power supply was turned ON.
7. Table 4 was completed.
8. The power supply was turned OFF.

Table 3 Table 4

INPUTS OUTPUTS
INPUTS OUTPUTS
A B X
A B X
0 0 1
0 1 1 0 0 1
1 0 1 0 1 0
1 1 0 1 0 0
1 1 0
PART C (TABLE 3 & 4)
 QUESTION

1. Which logic gate can be used to replace the circuit as shown in Fig. 2-3 & Fig.2-4.
 For Figure 2-3, it can be replaced with the NAND gate and Hex inverter.
 For Figure 2-4, it can be replaced with the NOR gate and Hex inverter.

2. The OR gate can be obtained by inverting the inputs of a NOR gate.

3. Inverting the output of a NOR gate will produce a/an OR gate.

4. With logic diagram and equation, show how 1 2-input NAND gate can be used as an inverter.

A Y= A.A

5. The output of the logic gate as shown below is 0100100. .

11 1 1 1 A X

0 0 B

6. Construct a 2-input NOR gate by using only 2-input NAND gate.

Y = A+B
7. Draw the electrical equivalent circuit of the 2-input NAND and 2-input NOR gate using only
switches and lamps.

NAND GATE

NOR GATE
DISCUSSION

In the experiment 2, the title is NAND and NOR gates. In this experiment, when a "NAND" Gate
is a logical gate which is the opposite of an AND logic gate. It is a combination of "AND" and "NOT"
gates and is a commonly used logic gate. It is considered as a "universal" gate in Boolean algebra as it is
capable of producing all other logic gates. Then, in this experiment also was used NOR gate, when the
NOR gate is a type of logic gate that works on the principle of “neither this nor that.” This type of digital
logic gate produces a high output only if two binary results are satisfied by a zero or low input. Next, in
this experiment also, was used the gate conversion. Gate coversion is the gate that used is more than one
gate, but the gate that was used is same. For example in this experiment for part c ( gate conversion ) used
two type of gate. First for this part, for figure 2-3 the gate that used is NOR. But for this part the NOR
gate was used three NOR gate. Next, for this part also was used NAND gate, for the NAND gate also was
used three type of NAND gate as shown in figure 2-4.

In this experiment, was consist 3 part which is part A, part B and part C. After that, the output;
(X = AB) for part A that was get, by using the NAND gate is 1110. Next, for part B the output (X=
A+B) that was get is 1000. The last, the output that was get for part C was consist two table which is table
3 and table 4. The output for table 3 is 1110 and the output for table 4 is 1000.

CONCLUSION

In this experiment, this experiment is to determined output of NAND Gate, to determined output
of NOR Gate and to determined output for Gate Conversion. In this experiment for part A, that was used
the NAND gate. The output was gate form this gate is 1110. Next, for part B the output that was gate is
1000 by using the NOR gate. Lastly, for part C was consist two output from NAND gate and NOR
gate. The output was gate from both of gate which is table 3 is 1110 and for table 4 is 1000.

REFERENCE

1. https://www.techopedia.com
2. https://www.electronics-tutorials.ws/logic/logic_5.html
3. Introduction to Boolean Algebras by Steven Givant, Paul Halmos, published by Springer
Science & Business Media, 2 Dec 2008.
Experiment 3:

Boolean Algebra

Materials Required :

 Hex inverter IC (7404) -1

 Quad 2 inputs AND gate IC (7408) -1

 Quad 2 inputs OR gate IC (7432) -1

 Quad 2 inputs NAND gate IC (7400) -1

 Quad 2 inputs NOR gate IC (7402) -1

 Digital logic trainer -1

Part A : Boolean Algebra

Figure 6.1

Figure 6.2
Procedure:

1. Refer to the circuit in Figure 6.1

a) The expression for the output of gate A = A + B

b) The expression for the output of gate B = B +C

c) The expression for the output of gate C = C’ + D

d) The expression for the output of gate D = (A + B) (B + C)

e) The expression for the output of gate E = A’ ( C’ + D)

f) The expression for the output of gate F = (A + B) ( B + C) + A’ (C’ + D)

2. Figure 6.2 can be used to implement the simplified logic equation of Figure 6.1.

3. F = B (A +C ) + A’ (C’ + D)

4. The output of Figure 6.2 can be used to implement the simplified the logic equation
of Figure 6.1.

5. There are two logic gates that had been eliminated from the circuit by
simplification using Boolean algebra.
Part B : DeMorgan’s Theorem

Figure 6.3

Figure 6.4

Procedure:

1. Both of the circuit were connected as shown in Figure 6.3.

2. The power supply was turned on.

3. Table 1 was completed.

4. The power supply was turned off.

5. Both of the circuits were connected as shown in Figure 6.4.

6. The power supply was turned on.

7. Table 2 was completed.

8. The power supply was turned off.

 Figure 6.5

Figure 6.6

9. The Boolean equation for the logic circuit in Figure 6.6 is Y = (A + BC’) + (AC + BD)’.

10. The Boolean equation for the logic circuit in Figure 6.5 is Y = (A + BC)’ + ( AC + BC)’

11. The circuits in Figure 6.5 and Figure 6.6 perform different logic function.

12. Both of the circuits were connected as shown in Figure 6.5.

13. The power supply was turned on.

14. Table 3A was completed.

15. The power supply was turned off.

16. Both of the circuits were connected as shown in Figure 6.6.

17. The power supply was turned on.

18. Table 3B was completed.

19. The power supply was turned off.

Data and Result:

Table 1

FIGURE 3 A FIGURE 3 B
INPUTS OUTPUTS INPUTS OUTPUTS

A B Y = AB A B Y = A+ B

0 0 1 0 0 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 0 1 1 0

Table 2

FIGURE 4 A FIGURE 4 B
INPUTS OUTPUTS INPUTS OUTPUTS

A B Y = A+ B A B Y=A .B

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 0 1 1 0
Table 3

(A) FIGURE 5 (B) FIGURE 6

INPUTS OUTPUTS INPUTS OUTPUTS

A B C D A B C D 0

0 0 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 1 0

0 0 1 0 0 0 0 1 1 0

0 0 1 1 0 0 1 0 0 0

0 1 0 0 0 0 1 0 1 0

0 1 0 1 0 0 1 1 0 0

0 1 1 0 0 0 1 1 1 0

0 1 1 1 1 1 0 0 0 0

1 0 0 0 0 1 0 0 1 0

1 0 0 1 0 1 0 1 0 1

1 0 1 0 1 1 0 1 1 1

1 0 1 1 1 1 1 0 0 0

1 1 0 0 0 1 1 0 1 0

1 1 0 1 1 1 1 1 0 1

1 1 1 0 1 1 1 1 1 1

1 1 1 1 1
Table 4

INPUTS OUTPUTS

A B X

0 0 0

0 1 1

1 0 1

1 1 1

Table 5

INPUTS OUTPUTS

A B X

0 0 0

0 1 1

1 0 1

1 1 1
Questions:

1) Do the result in Table 1 and Table 2 prove the two Demorgan’s theorem?

I. NOR GATE II. NAND GATE

㤵 㤵 t

h h h h

㤵 h㤵h h t t h h t

h h t t t 㤵 t㤵 h h㤵t t

㤵 㤵

2) What can you conclude from Table 3 ?

The result from table 3 which is from Figure 5 and Figure 6 are different because
NAND circuit to operate as an OR gate, and to use NOR circuit to operate as an AND
gate.

3) Simplify the equation:

a) 㤵 㤵
㤵 㤵 㤵
㤵 㤵 㤵 t
㤵

b) 㤵t 㤵
㤵 㤵t 㤵t
㤵 㤵t 㤵

4) Simplify the expressions and draw the logic circuit for the simplified expression.
a) t㤵 t
t㤵 㤵t
t㤵 㤵 t
t㤵 t
 A
t
A
t

C t㤵 t
ABC

b) t 㤵 t 㤵 t
t 㤵 t 㤵 t

A t

t 㤵 t 㤵 t

t
B

t
C

D
Result:

Figure 3A

A= 0, B=0

A=0, B=1
A=1, B= 0

A= 1, B=1
Figure 3B

A= 0, B=0

A= 0, B=1

A=1, B=0
A=1, B=1

Figure 4A

A=0, B=0
A=0, B=1

A=1, B=0
A=1, B=1

Figure 4B

A=0, B=0
A=0, B=1

A=1, B=0
A= 1, B=1

Figure 5A

A= 0, B= 0, C= 0, D= 0
A=0, B=0, C=0, D=1

A=0, B=0, C=1, D=0

A=0, B=0, C=1, D=1

A=0, B=1, C=0, D=0

A=0, B=1, C=0, D=1

A=0, B=1, C=1, D=0

A=0, B=1, C=1, D=1
A=1, B=0, C=0, D=0

A=1, B=0, C=0, D=1

A=1, B=0, C=1, D=0

A=1, B=0, C=1, D=1

A=1, B=1, C=0, D=0

A=1, B=1, C=0, D=1

A=1, B=1, C=1, D=0

A=1, B=1, C=1, D=1

Figure 6

A= 0, B=0, C=0, D= 0

A=0, B=0, C=0, D=1

A=0, B=0, C=1, D=0

A=0, B=0, C=1, D=1

A=0, B=1, C=0, D=0

A=0, B=1, C=0, D=1

A=0, B=1, C=1, D=0

A=0, B=1, C=1, D=1

A=1, B=0, C=0, D=0

A=1, B=0, C=0, D=1

A=1, B=0, C=1, D=0

A=1, B=0, C=1, D=1

A1, B=1, C=0, D=0

A=1, B=1, C=0, D=1

A=1, B=1, C=1, D=0

A=1, B=1, C=1, D=1

Discussion

Combinational logic is a type of digital logic which is implemented byBoolean circuits,

where the output is a pure function depending on the inputs. It isused in computers circuits to do
Boolean algebra on the inputs and stored data. The experiment enables us to verify De Morgan’s
theorem, to used NAND circuit to operate as an OR gate, and to use NOR circuit to operate as an
AND gate. The first part is focus in verifying De Morgan’s Theorem. It states that negation of a
Boolean expression maybe accomplished by negating each variable and changing each AND to
OR and vice versa. For verifying the OR expression and building the required circuit, the LED is
turned off when both the input is grounded or have a logic of 0 otherwise it is turned on which
represent logic 0 for the output. For verifying the AND expression and building the required
circuit, the LED is turned on when both the input voltage is 5V so the logic is 1 otherwise the
LED is turned off wherein the logic is 0. Based on the data in the truth table, the output is low
when both the input is low for the OR gate. For the AND gate, the output is high when both the
input is high. The second part is focus on universal logic gates. NAND and NOR gates were used
in this part. For the NOR gate, the LED is turned on when both the input is 5V or have a logic of
1 otherwise the LED is turned off wherein the logic is 0. For the NAND gate, the LED is turned
off only when both the inputs were grounded or have a logic of 0 otherwise the LED is turned on
wherein the logic is 1. Based on the data in the truth table of the NOR gate, the output is high
only when both the inputs are high or having a logic of 1. For the NAND gate, the output is low
when both the inputs were low. Based in our data, when the NOR gate circuit is simplified it is
equivalent to an AND gate. For the NAND gate, the simplified circuit expression for it is an OR
gate.
Conclusion

This experiment is about De Morgan’s Theorem and universal logic gates. The objectives
of the experiment is to verify De Morgan’s Theorem, to use NAND circuit to operate as an OR
gate, and to use NOR circuit to operate as an AND gate. For the first part of the experiment, the
AND and OR expressions were performed. It is verified that AND and OR gates are related.
When it is negate the AND gate, the equivalent operation is an OR gate. Negating OR gate is
equivalent to an AND gate. This approves with principle of negation and De Morgan’s Theorem.
For the second part, universal logic gates were performed. Based in the data, the NAND gate is
an inverted AND gate. Since AND gate is inverted or negated, NAND gate operation is
equivalent to OR gate operation. For the NOR gate, it is an inverted OR gate. An inverted OR
gate operation is equivalent to an AND gate operation. This part shows that universal logic gates
are used to obtain the function of other logic gates with the use of the principle of negation.
Instead of using many gates, it can be lessen to a universal logic gate. With the help of the data,
it has fulfilled the objectives of the experiment. This makes the data reliable and make this
experiment a success.

References:

1) Boolean Algebra and Its Applications by J. Eldon Whitesitt, published by Courier

Corporation, 24 May 2012.
2) Boolean Algebra by R. L. Goodstein, published by Courier Corporation, 15 Aug 2012.
3) Logic and Boolean Algebra by Bradford Henry Arnold, published by Courier
Corporation, 2011.
4) Introduction to Boolean Algebras by Steven Givant, Paul Halmos, published by Springer
Science & Business Media, 2 Dec 2008.
5) Boolean Algebras in Analysis by D.A. Vladimirov, published by Springer Science &
Business Media, 17 Apr 2013.
EXPERIMENT 4: DECODING COUNTERS AND DIGITAL DISPLAY

OBJECTIVE:

i. To test a seven-segment LED display

ii. To connect and operate a decoder with a seven-segment LED display

METHODOLOGY:

Figure 4.1 A. Pin layout of IC 7447

Figure 4.1 C. KYX-5161BS Common-Anode 7-Segment LED Pin Layout

Figure 4.1 B. Pin connection of IC 7447

 1. The circuit was connected as shown in Figure 4.1 B & C.
2. The power supply was turned ON.
3. Table 1 was completed.
4. The power supply was turned OFF.

RESULT:

INPUT OUTPUT
SW1 SW2 SW3 SW4 a b c d e f g Binary
0 0 0 0 1 1 1 1 1 1 0 0
0 0 0 1 0 1 1 0 0 0 0 1
0 0 1 0 1 1 0 1 1 0 1 2
0 0 1 1 1 1 1 1 0 0 1 3
0 1 0 0 0 1 1 0 0 1 1 4
0 1 0 1 1 0 1 1 0 1 1 5
0 1 1 0 1 0 1 1 1 1 1 6
0 1 1 1 1 1 1 0 0 0 0 7
1 0 0 0 1 1 1 1 1 1 1 8
1 0 0 1 1 1 1 1 0 1 1 9
1 0 1 0 0 0 0 1 1 0 1 10
1 0 1 1 0 0 1 1 0 0 1 11
1 1 0 0 0 1 0 0 0 1 1 12
1 1 0 1 1 0 0 1 0 1 1 13
1 1 1 0 0 0 0 1 1 1 1 14
1 1 1 1 0 0 0 0 0 0 0 15
OBSERVATION:

Binary 0

Binary 1
Binary 2

Binary 3
Binary 4

Binary 5
Binary 6

Binary 7
Binary 8

Binary 9
Binary 10

Binary 11
Binary 12

Binary 13
Binary 14

Binary 15
DISCUSSION:

This experiment is about seven segment LED display. Seven segment LED display provide a
very convenient way of displaying information or digital data in form of number, letters or even
alpha-numerical characters. Seven-segment LED allow the display of alpha numerical 7-segment
decoders consist of 7 rectangular LEDs segments arranged together in shape of 8. In order to
produce the required number or character, a specific combination of LED segments needs to be
illuminated.

Seven segment LED display consist of two types. There are cathode display and anode
display. For cathode display all the connection of LED’s are joined together to logic 0 or ground.
The zero mean LOW signal. Then the LED display will not appear any numerical display. For
anode display all the connection of LED’s are joined together to logic 1. Logic 1 mean the HIGH
signal. Then the LED that produce output high will display the number.

This experiment used IC 7447 as a solid-state devices. Four switches was used as the
input. For zero binary all the switch was turned off. All the signal become low, but the input
voltage is high then the high output for segment a, b, c, d, e and f will become high and all the
segment will light and the 0 binary output will appear. For 15 binary all the switch is turned on
and the signal become high. Because the input voltage is high the output become low. Then the 7
segment for a, b, c, d, e, f and g will produce the light and display 15 binary. Same goes to
another binary. The segment that contain high output will light on and display the number while
the low output will light off the LED display.

There are a few error involve in this experiment. Firstly, the common anode seven
segment LED is broken. This cause the g segment is not light on. Other error is the wire
connected to digital logic trainer is broken. It will caused the input received is not complete. The
precaution step was taken to avoid the error happen during handling the experiment. Before
started the experiment make sure the material used is in good condition. Moreover, make sure
the wires inserted to the digital logic trainer is correctly inserted in the pit to make sure the input
received perfectly.
 CONCLUSION:

In conclusion, seven-segment LED display will display input depend on HIGH and LOW
signal. The input will activated the seven segment and display the binary number starting from 0
until 15. 0 to 9 will appear like normal number while 10 to 15 have their own shape of binary
outputs. Foe every binary outputs produce the switch turned on also difference depend on the
input key in on the switch.

REFERENCE:

i. https://www.electronics-tutorials.ws/combination/comb_6.html
ii. https://tolotra.com/2018/04/11/lab-report-on-binary-coded-decimal-bcd-to-a-7-segment-
decoder/#2_BRIEF_INTRODUCTION_AND_THEORETICAL_BACKGROUND
iii. Introduction to Boolean Algebras by Steven Givant, Paul Halmos, published by Springer
Science & Business Media, 2 Dec 2008.
EXPERIMENT 5 : CLOCKED-R-FLIP-FLOP AND D TYPE FLIP-FLOP

Materials Required

 Quad 2 inputs NAND Gate IC (7400) -1

 Digital logic trainer -1

Figure 10-1

Procedure

1. An SN7400 was plugged into the trainer unit and wired the circuit shown in Figure 10-1.

2. The logic switches was used to SET and RESET data combinations given in Table 1. A single
clock pulse was entered by depressed and released PULSER one time for each data entry. The
connection from the CLOCK input NORMALLY “0” output.

3. Depressed and released, it cause this output to go from “0” to “1” and back to “0”. The output
logic levels Q and Q were recorded that resulted from each R and S input combination
immediately followed the CLOCK pulse.
Table 1

Inputs at tn Outputs at tn + 1

Reset Set Q Q’

0 0 0 1

0 1 1 0

1 0 0 1

1 1 1 1
D TYPE FLIP-FLOP

Materials Required

 Quad 2 Inputs NAND gate IC (7400) - 2

 Digital logic trainer -1

Procedure

Figure 11-1

1. 2 SN7400 were plugged into the trainer unit and wire the circuit shown in Figure 11-1.

2. Input conditions D was enter as shown in Table 1. Each entry were followed with a CLOCK
pulse and the resultant output conditions at Q and Q were observed. The observations were
recorded in the table.

3. The CLOCK input was disconnect and then connected it to the CLOCK OUTPUT. The clock
rate was set at 1 Hz. A LED Monitor was connected to the CLOCK INPUT so that the input and
output transitions simultaneously with the LED MONITORS can observed.

LED7 …CLOCK INPUT

LED6 …Q OUTPUT

LED5 …Q’ OUTPUT

TABLE 1

Inputs at tn Outputs at tn + 1

D Q Q’

0 0 1

1 1 0
Discussion

SR flip flop circuit using NAND gate. There are two input named S and R as shown in
circuit diagram. To understand the working one must know the truth table of NAND gate. In
NAND gate we will get output as 0 only if both the inputs are high and if any of the input is high
or both the input is low we will receive logic 1. If it has applied S (NOT) =1 and R (NOT) =1 at
the input of the flip flop the flip flop will not change its state and it will remain in its present
state while if S (NOT) =0 and R (NOT)=1, the output of upper NAND gate become high. Thus
both the inputs of lower NAND gate is high, output will be low. Therefore, it will receive 1 at
reset input it will switch the flip flop to stable state where Q=1and Q(NOT) =0. In this state flip
flop will set itself and at this time yellow LED will glow. Next, if S (NOT) =1 and R (NOT)=0,
now output of lower NAND gate become high making both the inputs of upper NAND gate high,
Output will be low. Hence, it can be say that a 1 at S (NOT) input sets the flip flop and flip flop
switches to a stable state where Q=0 and Q(NOT) =1. In this state flip flop will set itself and at
this time red LED will glow, after that, if both S (NOT) =0 and R (NOT)=0 at this time output of
both the NAND gates to become high, both the output will be Q=1 and Q(NOT) =1 and this
violates the definition of flip flop which says that both the outputs of a flip flop are complement
of each other. Hence practically this condition is not possible in this both LED will not glow.
The latch is a type of bistable storage device that is normally placed in a category separate from
that of flip-flops. Latches are basically similar to flip-flops because they are bistable devices that
can reside in either of two states by virtue of a feedback arrangement, in which the outputs are
connected back to the opposite inputs. The basic difference between latches and flip-flops is the
way in which they are changed from one state to the other. This type of digital circuitry is called
sequential logic, because it is controlled by and is used for controlling other circuitry in a
specific sequence dictated by a control clock or enable/disable control signals. The flip-flop is a
basic building for counters, registers, and other sequential control logic .The D Flip Flop is by far
the most important of the clocked flip-flops as it ensures that ensures that inputs S and R are
never equal to one at the same time. The D-type flip flop are constructed from a gated SR flip-
flop with an inverter added between the S and the R inputs to allow for a single D (Data) input.
Then this single data input, labelled “D” and is used in place of the “Set” signal, and the inverter
is used to generate the complementary “Reset” input thereby making a level-sensitive D-type
flip-flop from a level-sensitive SR-latch.A simple SR flip-flop requires two inputs, one to “SET”
the output and one to “RESET” the output. By connecting an inverter (NOT gate) to the SR flip-
flop we can “SET” and “RESET” the flip-flop using just one input as now the two input signals
are complements of each other. This complement avoids the ambiguity inherent in the SR latch
when both inputs are LOW, since that state is no longer possible. Thus this single input is called
the “DATA” input. If this data input is held HIGH the flip flop would be “SET” and when it is
LOW the flip flop would change and become “RESET”. However, this would be rather pointless
since the output of the flip flop would always change on every pulse applied to this data input.To
avoid this an additional input called the “CLOCK” or “ENABLE” input is used to isolate the
data input from the flip flop’s latching circuitry after the desired data has been stored. The effect
is that D input condition is only copied to the output Q when the clock input is active. This then
forms the basis of another sequential device called a D Flip Flop.The “D flip flop” will store and
output whatever logic level is applied to its data terminal so long as the clock input is HIGH.
Once the clock input goes LOW the “set” and “reset” inputs of the flip-flop are both held at logic
level “1” so it will not change state and store whatever data was present on its output before the
clock transition occurred. In other words the output is “latched” at either logic “0” or logic “1”.
CONCLUSION:

In conclusion, the output of the NAND gates is 0 and 1 for 00 input. 1 and 0 output is for
01 inputs. 0 and 1 output from the input 10 and output 11 from the input 11. All the output
produces is depending on the input given.

REFERENCES

1. The fields of electronics: understanding electronics using basic physics, Ralph Morrison,
John Wiley & Sons, 2002.

2. Foundations of Analog and Digital Electronic Circuits, by Anant Agarwal, Jeffrey Lang,
Derise E.M. Penrose.

3. How to Use a Breadboard!, by Sean Michael Ragan, Jody Culkin

4. Complete Digital Design, by Mark Balch.

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