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OF gm/ID CHARACTERISTICS

Instituto de Informática

Porto Alegre - RS - Brazil

{girardi, bampi}@inf.ufrgs.br

usage of these tools is that they require appropriate

This paper presents a transistor sizing methodology for modeling of both devices (technology dependence) and

analog CMOS circuits that combines the physics-based circuit in order to achieve the design objectives in a

gm/ID characteristics provided by the ACM compact reasonable processing time. The choice of different circuit

model and the simulated annealing technique for the topologies to support in a method or tool is also a

circuit optimization. The methodology exploits different problem, since most approaches work with topology-based

transistor widths and lengths and provides good solutions equations, which limits the application range. The

in a reasonable CPU time, with a single technology- addition of new block topologies to the CAD system has to

dependent curve and accurate expressions for be supported, since it is a critical and often slow process

transconductance and current in all operation relgions. that requires again expert designer knowledge. The use of

The advantage of constraining the optimization within a optimization algorithms combined with design techniques

power budget is of great importance for the designer. As seems to be a good solution when applied to specific

an example, we show the optimization results obtained for applications, since a general solution most often proves to

the design of a two-stage operational amplifier. have shortcomings for fully exploiting the capabilities of

the analog CMOS technology. The main requirements of

an analog synthesis tool are: interactivity with the user,

1. INTRODUCTION flexibility for multiple topologies and reasonable response

time. The interface with an electrical simulator is also

The design of CMOS analog integrated circuits needs convenient.

skilled specialists that often used detailed knowledge of This paper describes a methodology for analog design

the device technology and models to complete the design automation that combines the simulated annealing

of blocks containing tens of transistors. The task is optimization technique, a physics-based transconductance-

demanding due to the complex relations between the to-current ratio characteristics and the electrical

design objectives (multiple and complex performance simulation in the same environment, providing even to a

specifications to be met, like bandwidth, gain, power, non-expert user a very flexible tool that is able to size

maximum offset voltage, power-supply rejection ratio, analog circuits including a broad range of constraints

etc.) and the multiple design variables (transistor sizes such as total power dissipation. The paper is organized as

and bias currents) to be set. Previous work has been done follows: Section 2 describes the proposed methodology

in the field of analog design automation to enable fast and explains the relationship between the simulated

design at the block level. Different strategies and annealing algorithm, the gm/ID technique and the ACM

approaches have been used, such as spice simulation [12], MOSFET model; in Section 3 the synthesis of a two-stage

symbolic simulation [6], artificial intelligence [4], operational amplifier is shown in order to demonstrate the

manually derived design equations [3], hierarchy and capabilities of the methodology; finally, in Section 4 we

topology selection [7] and geometric programming [8] present some conclusions.

1

where βi is the weighting coefficient for performance

parameter pˆ i ( X ) which is a normalized function of the

vector of independent design parameters X. This function

allows the designer to set the relative importance of

competing performance parameters, such as, for example,

a weighted relation between power and noise.

For the transistor sizing, knowledge-based equations

that describe the relations between the transistors and

specifications are needed. These equations are topology-

specific and can be used within a synthesis methodology

for the resolution of a system of non-linear equations. This

system usually has more independent variables than

equations, returning infinite solutions. If a set of design

parameters has to be minimized, then the simulated

annealing algorithm is a good option, since it exploits

most of the design space, including different transistor

Fig. 1 – gm/ID x I curve for 0.35 m CMOS technology.

lengths, which are kept fixed in most design tools.

For the circuit performance evaluation, we use a

methodology called gm/ID. The gm/ID method considers

2. OPTIMIZATION METHODOLOGY

the relationship between the ratio of the transconductance

gm over DC drain current ID and the normalized drain

Simulated annealing (SA) is a well known random search

current I = ID/(W/L) as a fundamental design tool [13],

technique which exploits an analogy between the way in

which a metal cools and freezes into a minimum energy

characteristic is related to the performance of analog

crystalline structure (the annealing process) and the

circuits, gives a clear indication of the device operation

search for a minimum of a cost function in a more general

region and provides a way for automating the calculation

system. It forms the basis of an optimization technique for

of transistors dimensions. The main advantage of this

combinatorial and other problems [9]. The use of

simulated annealing in the synthesis of analog circuits method is that only the gm/ID x I curve must be related to

was reported in previous works [5][11]. SA’s major the fabrication technology parameters, a feature that

advantage over other methods is the ability to avoid facilitates the migration to another CMOS technology. In

becoming trapped in local minima. The algorithm this work, the gm/ID x I curve is generated by electrical

employs a random search which does not only accept simulation using the ACM compact MOSFET model [2],

solutions that decrease the objective cost function fc which is also implemented in the commercial simulator

(assuming a minimization problem), but also some SMASH. This model is composed by simple expressions

changes that increase it. The latter are accepted with a to describe all regions of operation in a continuous

probability representation of the transistor current and small-signal

parameters.

∆f c The symmetry of the MOSFET drain-source is

−

p=e T

(1) observed and a reduced number of model parameters is

used. Moreover, all the parameters have a strong physical

basis. The proposed methodology joins the SA algorithm,

where ∆fc is the increase in fc and T is a control the gm/ID technique and the ACM MOSFET model in the

parameter, which by analogy to the annealing is known as same environment in order to optimize the design of

the system ”temperature” irrespective of the objective analog circuits based on the transistor inversion

function involved. The analog circuit modeling for coefficient. The main advantage of using the SA over the

simulated annealing is straightforward. The design crude gm/ID technique is that the design space is explored

objective (e.g. minimum power and area) is called the cost in a more effective way, combining operation in weak and

function which has to be minimized and should be strong inversion to achieve optimum low-power design.

formulated appropriately. In this work we propose and use Figure 2 shows the design flow. The user enters the design

the following cost function: specifications, technology parameters and configures the

cost function according to the required design objectives.

n

fc = β i pˆ i ( X )

(2)

i =1

2

Fig. 3 – Schematics of a two-stage operational amplifier

Tab. 1 – Specifications and simulated results for the two-

The optimization loop starts with a random stage amplifier

perturbation on the design variables, whose amplitude is

defined by the current temperature. These variables are

defined by the user, and are always related to the

transistor geometry, large and small-signal parameters,

such as W, L, ID, gm and gm/ID. Following, the design

properties evaluation is performed by the calculation of

the circuit characteristics such as gain, cut-off frequency,

phase margin, power, noise, etc. This is done using circuit

specific analytical equations, the gm/ID versus I curve

transconductances and currents. At this point, the cost

function can be evaluated and the solution is accepted if

the cost decreased or else if the cost increased with a

probability given by equation 1. If the circuit is feasible,

i.e., transistor sizes are within an allowed range, the new 3. DESIGN EXAMPLE

solution is accepted. Otherwise, it is discarded. The next

iteration starts with a new temperature, which is The proposed design methodology was implemented in

calculated by MATLAB and applied to the synthesis of a two-stage

operational amplifier, shown in figure 3. This amplifier is

Tk +1 = αTk (3) composed by an input differential pair with active load in

the first stage and an inverter amplifier in the second

where α is a constant less than 1 and very close to this stage. A compensation capacitor is necessary for stability.

value. The index k indicates the iteration step. The process The analytical equations that describe the behavior of

ends when the temperature achieves a minimum value or this circuit are well-known [1]. In this example, we want

the variation in the cost function does not suffer relevant to size the transistors in order to achieve the design

modification related to the perturbation in the variables. specifications given in Table 1. The design objective (fc) is

The temperature schedule can be configured through the to minimize the relative area, low-frequency gain and

choice of the α parameter in order to achieve the best total DC current in the following way:

relation between time response and solution refinement.

A I DD Av0

fc = + + (4)

A0 I DD 0 Av

3

The drain current for these transistors can be

calculated with the information about the

transconductance-to-current ratio, which is an

independent variable:

gm1

I D1 =

(6)

gm

ID

W I D1

=

(7)

L 1 I1

W1 = ⋅ L1

(8)

L 1

procedure where I 1 is the normalized current given by the gm/ID x

I curve.

The same approach is done for the remaining

transistors. For example, the size of the transistors in the

current mirror load is:

W I D1

=

(9)

L 3 I 3

W

W3 = ⋅ L3

!"

(10)

L 3

straightforward. The low-frequency gain is given by

% %

gm gm

Av =

&'( # &'( #

& # & #

ID ID

$ $

1 5

model according to the transistor length. In this example,

the technology used is 0.35 m CMOS, the power supply

voltage is ±1.65V and the load capacitance is 10pF. The

Fig. 5 – Probability function independent variables subjected to perturbations by the

simulated annealing algorithm are: L1 = L2, L3 = L4, L5,

+ 1 7 1

gm ) 234

gm / 89:

gm 5 234

gm /

L6, L7, = , = ,

, ) 2 / 8 5 2 /

ID 1 ID 2

ID 3

ID 4

7 1 1

gm 5 234

gm / 234

gm /

8 5 2 / 2 /

ID 5

ID 6

ID 7

gm1 = GBW ⋅ C f (5) parameters are W1 = W2, W3 = W4, W5, W6, W7 = W8, Cf

and bias current. The conditions L > Lmin, W > Wmin and

4

= = =

gm gm gm

≤ ≤

>?@ ; >?@ ; >?@ ;

> ; > ; > ;

ID min

ID ID max

[4] F. El-Turky and E. E. Perry. BLADES: An artificial

solutions, with Lmin = 0.3 m, Wmin = 0.6 m, (gm/ID)min =

A A

0.1 and (gm/ID)max = 25. Transactions on Computer-Aided Design, 8(6):680–692, June

The optimization process for the example took 158 1989.

iterations and 91 million floating point operations. The

final transistors sizes obtained by the iterations with the [5] G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen.

analytical models are shown in table 2. The second Analog circuit design optimization based on symbolic simulation

column of table 1 shows the performance of the optimized and simulated annealing. IEEE Journal of Solid-State Circuits,

solution, as estimated by electrical simulations with 25(3):707–713, June 1990.

SMASH. Figure 4 shows the evolution of the cost

[6] G. G. E. Gielen, H. C. C. Walscharts, and W. M. C. Sansen.

function. We can note the convergence of the cost function

ISAAC: A symbolic simulator for analog integrated circuits.

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freezes. In figure 5 is shown the probability function, December 1989.

which decreases as the number of iterations increase. A

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Computer Aided Design, 8(12), 1989.

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Transactions on Computer-Aided Design of Integrated Circuits

In this work we presented a sizing method that

and Systems, 20(1):1–21, January 2001.

combines simulated annealing algorithm, the gm/ID

technique and the ACM MOSFET model in the same [9] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization

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