Jordan University of Science and Technology Department of Computer Engineering

CPE 352: Computer Architecture Second Exam – 2nd Semester 2013/2014 10/5/2014

Question 1:
Assume the following Code segment is to be executed by the MIPS pipelined
machine. The LW instruction enters the pipeline at cycle 1.

SW $3,4($31)
J 0xCC012
LW $3,0($31)
ADDI $1,$2,4
BEQ $3,$1,0xFFFC

At cycle all 5 instructions have entered the pipeline. During this cycle,
show the status of all control signals in the pipeline.

Question 2:
Consider the following program which represents a loop that will execute
100 times on a MIPS pipelined processor.

1: LOOP: LW $10,0($1)
2: ANDI $11,$10,0X01
3: LW $20,0($2)
4: BEQ $20,$0,EVEN //Pattern T,NT,T,NT,NT
5: ODD: ADD $20,$20,$10
6: BEQ $0,$20,FSH //always not taken
7: EVEN: SUB $20,$20,$10
8: ADDI $20,$20,4
9: FSH: ADDI $30,$30,-1
10: BNE $30,$0,LOOP //Taken 99 times and last one is not taken

Assume the following penalties:

Two cycles for immediate data dependency if forwarding is not used
One cycle for immediate dependency on a load if forwarding is used
Two cycles for a wrong branch prediction or a no prediction (stall).

1- For this part assume a 2-bit branch history is used.

a. What is the prediction at iteration 11 of branch4? Is it correct?
b. What is the prediction at iteration 13 of branch4? Is it correct?
c. What is the percentage of correct prediction of branch4?

2- What is the percentage of correct prediction of branch6 if static

prediction not-taken is used?

3- What is the percentage of correct prediction of branch10 if 1-bit

history is used?

4- How many times each of instruction 5 and 6 are executed?

5- How many cycles per iteration are consumed due to data hazards if
NO forwarding is used, and branches are correctly predicted?

6- How many cycles per iteration are consumed due to data hazards if
forwarding is used, and branches are correctly predicted?

7- If 1-bit history prediction is used and data hazards are resolved by

forwarding, compute the number of cycles required to execute the
above loop. Ignore startup cycles.
Jordan University of Science and Technology Department of Computer Engineering
CPE 352: Computer Architecture Second Exam – 2nd Semester 2013/2014 10/5/2014

Question 3:
Assume the following cache configuration, 32-bit physical address, direct
mapped 16MB cache size, 256 block size.
a. how many bits are required for the tag, the block index, and the
byte offset?
b. Identify the cache hit/miss for each of the following addresses.
(Assume startup conditions and the addresses appear in sequence.)
No. Address Hit/Miss
1 AA A01B 04 miss
2 AA B01B 08 Miss
3 AA A01B 0C Hit
4 BB B01B 18 Miss
5 AA C01B 60 Miss
6 BB A01B 04 Miss
7 AA B01B 08 miss
8 CC A01B 0C miss
9 AA A01B 18 miss
10 AA C01B 60 hit
11 CC A01B 90 miss

Question 4:
Assume a 2-level cache configuration with the following parameters
1st level cache is split into instruction cache and data cache
2nd level cache is unified for both instruction and data
1st level cache hit time= 1 cycle
Each 1st level cache is connected to the 2nd cache through a wide bus
of 128 lines with a bus cycle time of 5 processor cycles
The memory is composed of 4 banks connected to the 2nd cache via a
32-bit bus. The bank latency is 20 processor cycles and the bus cycle time
is 5 processor cycles.
1st instruction cache hit rate = 0.9
1st data cache hit rate = 0.8
2nd cache hit rate (when a miss occurs in 1st level) = 0.7

a. What is the first cache miss penalty

b. What is the 2nd cache miss penalty
c. What is the average time to fetch an instruction?
d. What is the average time to read an operand?
e. If 20% of the instructions are load/store, what is the average CPI?
Ignore data and control hazards.