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CAT24WC256
256K-Bit I2C Serial CMOS E2PROM
FEATURES
■ 1MHz I2C Bus Compatible* ■ Write Protect Feature
■ 1.8 to 6 Volt Operation – Entire Array Protected When WP at VIH
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS E2PROM CAT24WC256 features a 64-byte page write buffer. The
internally organized as 32,768 words of 8 bits each. device operates via the I2C bus serial interface and is
Catalyst’s advanced CMOS technology substantially available in 8-pin DIP or 8-pin SOIC packages.
reduces device power requirements. The
512
SOIC Package (K) SDA START/STOP
LOGIC
A0 1 8 VCC
A1 2 7 WP
E2PROM
NC 3 6 SCL XDEC 512 512X512
VSS 4 5 SDA CONTROL
24WC256 F01 WP LOGIC
PIN FUNCTIONS
Pin Name Function
DATA IN STORAGE
A0, A1 Address Inputs
SDA Serial Data/Address
HIGH VOLTAGE/
SCL Serial Clock TIMING CONTROL
WP Write Protect
SCL STATE COUNTERS
VCC +1.8V to +6.0V Power Supply
A0 SLAVE
VSS Ground A1 ADDRESS
COMPARATORS
NC No Connect
24WC256 F02
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
Limits
Symbol Parameter Min. Typ. Max. Units Test Conditions
ICC1 Power Supply Current - Read 1 mA fSCL = 100 KHz
VCC=5V
ICC2 Power Supply Current - Write 3 mA fSCL = 100KHz
VCC=5V
ISB(5) Standby Current 0 µA VIN = GND or VCC
VCC=5V
ILI Input Leakage Current 1 µA VIN = GND to VCC
ILO Output Leakage Current 1 µA VOUT = GND to VCC
VIL Input Low Voltage –1 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA
VOL2 Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min. Max. Min. Max. Min. Max. Units
FSCL Clock Frequency 100 400 1000 kHz
tAA SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 0.05 0.55 µs
and ACK Out
tBUF(2) Time the Bus Must be Free Before 4.7 1.2 0.5 µs
a New Transmission Can Start
tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs
tLOW Clock Low Period 4.7 1.2 0.6 µs
tHIGH Clock High Period 4.0 0.6 0.4 µs
tSU:STA Start Condition Setup Time 4.0 0.6 0.25 µs
(for a Repeated Start Condition)
tHD:DAT Data In Hold Time 0 0 0 ns
tSU:DAT Data In Setup Time 100 100 100 ns
tR(2) SDA and SCL Rise Time 1.0 0.3 0.3 µs
tF(2) SDA and SCL Fall Time 300 300 100 ns
tSU:STO Stop Condition Setup Time 4.7 0.6 0.25 µs
tDH Data Out Hold Time 100 50 50 ns
tWR Write Cycle Time 10 10 5 ms
The write cycle time is the time from a valid stop interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
program/erase cycle. During the write cycle, the bus address.
tLOW tLOW
SCL
tSU:STA tHD:DAT
tHD:STA tSU:DAT tSU:STO
SDA IN
tBUF
tAA tDH
SDA OUT
SCL
SDA
SCL
SCL FROM 1 8 9
MASTER
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START ACKNOWLEDGE
1 0 1 0 0 A1 A0 R/W
terminates data transmission and waits for a STOP If the Master transmits more than 64 bytes before sending
condition. the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
Byte Write has been sent by the Master, the internal programming
In the Byte Write mode, the Master device sends the cycle begins. At this point, all received data is written to
START condition and the slave address information the CAT24WC256 in a single write cycle.
(with the R/W bit set to zero) to the Slave device. After
Acknowledge Polling
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the Disabling of the inputs can be used to take advantage of
address pointers of the CAT24WC256. After receiving the typical write cycle time. Once the stop condition is
another acknowledge from the Slave, the Master device issued to indicate the end of the host's write operation,
transmits the data to be written into the addressed CAT24WC256 initiates the internal write cycle. ACK
memory location. The CAT24WC256 acknowledges polling can be initiated immediately. This involves issu-
once more and the Master generates the STOP condi- ing the start condition followed by the slave address for
tion. At this time, the device begins an internal program- a write operation. If CAT24WC256 is still busy with the
ming cycle to nonvolatile memory. While the cycle is in write operation, no ACK will be returned. If
progress, the device will not respond to any request from CAT24WC256 has completed the write operation, an
the Master device. ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
The CAT24WC256 writes up to 64 bytes of data, in a WRITE PROTECTION
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as The Write Protection feature allows the user to protect
the byte write operation, however instead of terminating against inadvertent programming of the memory array.
after the initial byte is transmitted, the Master is allowed If the WP pin is tied to VCC, the entire memory array is
to send up to 63 additional bytes. After each byte has protected and becomes read only. The CAT24WC256
been transmitted, CAT24WC256 will respond with an will accept both slave and byte addresses, but the
acknowledge, and internally increment the six low order memory location accessed is protected from program-
address bits by one. The high order bits remain un- ming by the device’s failure to send an acknowledge
changed. after the first byte of data is received.
S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA O
T P
SDA LINE S P
*
A A A A
C C C C
K K K K
24WC256 F08
*=Don't Care Bit
Figure 7. Page Write Timing
S
T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS T
MASTER R ADDRESS A15–A8 A7–A0 DATA DATA n DATA n+63 O
T P
SDA LINE S P
*
A A A A A A A
C C C C C C C
K K K K K K K
24WC256F09
*=Don't Care Bit
S
T S
BUS ACTIVITY: A SLAVE T
MASTER R ADDRESS DATA O
T P
SDA LINE S P
A N
C O
K A
C
K
SCL 8 9
S S
T T S
BUS ACTIVITY: A SLAVE BYTE ADDRESS A SLAVE T
MASTER R ADDRESS A15–A8 A7–A0 R ADDRESS DATA O
T T P
SDA LINE S
* S P
A A A A N
C C C C O
K K K K A
C
K
24WC128 F11
A A A A N
C C C C O
K K K K
A
C
K
5020 FHD F12
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 24WC256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)