Transistor Transistor Logic – TTL

(74xx and 54xx series chips)

1
 Transistor Transistor Logic
• DTL was able to improve fan-out compared to
RTL. However, that was done at the expense of:
– Transient response.
– Chip area.

• A solution for the problem was proposed in the

form of a new logic family which utilizes only
transistors and resistors.
– BJTs are smaller than diodes.

2
 Logic Families on a Glance

TTL Families:

 74 Standard
 74L Low power
 74H High speed
 74S Schottky
 74LS Low power Schottky
 74AS Advanced Schottky
 74ALS Advance Low power Schottky
 Standard, 74 series - introduced by Texas Instruments in 1964
 Low-power, 74L series - large resistor values reduce power dissipation
 High-speed, 74H series - small resistor values & Darlington pair reduce propagation delay
 Schottky, 74S series - Schottky barrier diode is used to reduce time delay
 Low-power Schottky, 74LS series - like 74S but uses larger resistor values
 Advanced Schottky, 74AS series - improved version of 74S
 Advanced low-power Schottky, 74ALS – has the lowest power-speed product

3
 Logic Families on a Glance

CMOS Families:

 40xx/45xx Metal-gate CMOS

 74C TTL-compatible CMOS
 74HC High speed CMOS
 74ACT Advanced CMOS-TTL compatible
 4000/14000 series - introduced by RCA/Motorola
 74C series - pin for pin and function for function compatible with TTL
 devices having the same number, e.g. CMOS 74C74 and TTL 7474
 74HC series - high speed (comparable with TTL) and higher output current
 74HCT series - voltage levels compatible with that of TTL devices, i.e. a TTL
device can directly drive a 74HCT device
 Compared to TTL families ; lower power dissipation and slower speed

4
 Logic Families on a Glance

Advanced CMOS Logic:

 First-Generation Devices
 No output slew rate control
 Serious noise!

 Second-Generation Devices
 Output slew rate control or TTL level output voltages

 Third-Generation Devices
 Vcc : 3.3V
 Logic families optimized

5
 Logic Families on a Glance

Advanced CMOS Logic

Logic Family Manufactures

First Generation, 5V
54/74 AC, ACT National, Motorola, Harris
54/74 AC11, ACT11 Texas Instruments, Philips
54/74FCT, FCT-A IDT, Cypress, Harris
29C800 AMD
Second Generation, 5V
54/74ACQ, ACTQ National
54/74FCT-T, FCT-AT, FCT-CT IDT
Third Generation, 3.3V
54/74LVQ National
54/74FCT3 IDT
74LVC Texas Instruments

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 Logic Families on a Glance

Logic family letter designator:

 5V family: AC, ACT, FCT, etc

 With T, TTL compatible input threshold at normal TTL supply
voltage levels

 Low-voltage: LVC, LVQ, FCT3, etc

 TTL compatible input threshold

 FCT and 29C800 families

 Bus interface families

 They are not true logic families since they don’t have NANDs,
NORs, etc

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 Logic Families on a Glance

BiCMOS Logic:

• BiCMOS technology
 CMOS input structure + CMOS internal logic + Bipolar
output structure.

• High speed, high drive, low power.

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 Basic TTL Inverter

VCC

RB RC

Vout
Vin Qo
QI

9
 TTL vs. DTL
• If we compare the basic DTL and TTL gates, we
find that the input and level-shifting diodes of
DTL can be combined into the input BJT of TTL.
VCC V CC

RB RC RB RC

Vout V out
Vin
Qo V in Qo
QI
DI DL

– The advantage is that the BJT requires less silicon area and the
propagation delay is improved by a factor of 10.

10
 Calculating the VTC
• VOH:
– For Vin very low, the base-emitter junction of QI will be
forward biased.
– The base-collector junction will also be forward biased.
– Therefore, QI will be saturated.
V
CC

– The base-emitter voltage of QO is:

VBE,O = VCE,I(Sat) + Vin R
B
R
C

– Therefore, QO will be cut-off

V
out
V
in Q
Q o
I
– Therefore,
Vout = VOH = VCC

11
 Calculating the VTC (Contd.)
• VIL:
– As Vin is increased, VB of QO will also increase. V
CC

Eventually, QO will turn on.

– This happens when: R
B
R
C

V
out
Vin = VIL = VBE,O (FA) – VCE,I (Sat) V
in Q
Q
o
I

• VOL:
– As Vin is increased even more, QO comes
V
out

V =V
closer to Saturation and eventually saturates. OH CC

– At that point:
V = V (Sat)
OL CE

Vout = VOL = VCE,O (Sat) VIL = VBE,O (FA) – VCE,I (Sat)

VIn

VIH = VBE,O (Sat) – VCE,I (Sat)

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 Calculating the VTC (Contd.)
• VIH:
– The point where QO is just saturating:
Vin = VIH = VBE,O (Sat) – VCE,I (Sat)

V out V
CC

V OH = V CC R R
B C

V
V out
in Q Q
I o

V OL = V CE (Sat)
VIn
VIH = VBE,O (Sat) – VCE,I (Sat)

VIL = VBE,O (FA) – VCE,I (Sat)

13
 What about the currents?
• If we look at the currents in the circuit, we find that
QI and QO cannot both remain saturated at the
same time.
• If QI is saturated, a positive IC,I must flow into the
collector of QI.
• IF QO is saturated, a positive IB,O must flow into the VCC
base of QO.
RC
• Impossible!!!! RB

V out
Vin Qo
•
QI
If we look at the voltages, we find that right after
QO saturates, the base-emitter junction of QI will
become reverse biased while the base-collector
junction is still forward biased.
– Therefore, QI will turn into Reverse Active mode.
• Under reverse active mode, IC,I flows out of the
collector of QI.
• This current will flow into the base of QO maintaining it
in saturation.

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 The Currents

• If both QI and VCC

QO are
saturated, then
both IC,I and RB RC
IB,O need to be Vout
positive.
Vin > VIH IB,O
QI QO Sat
Sat IC,I

• Impossible!!

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 The Voltages
VIH = VBE,O (Sat) – VCE,I (Sat) = ~0.6 V

V CC

R R C
B
Vout

VBE,I < ~ 0.8 VBC,I (FB) ~ 0.6

Vin > VIH > ~0.6 V QO Sat

QI cannot remain QI
in Saturation VBE,O (Sat)
~ 0.8

VB,I = ~1.4 V

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 The VTC
V
Vout CC

R R
VOH = VCC B C

V
V out
in Q Q
I o

VOL = VCE,O (Sat)

VIn
VIL = VBE,O (FA) – VCE,I (Sat)
VIH = VBE,O (Sat) – VCE,I (Sat)

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 The TTL NAND Gate
• For DTL, a NAND gate was built as shown below on the left.
– The same thing can be implemented in TTL by combining the input
diodes and the level shifting diode into multiple transistors.
– Or, the input transistors can be combined into a “multi-emitter” BJT
as shown in the figure on the right.

VCC VCC

RB RC RB RC
VCC

Vout Vout
VA VA
Qo RB RC Qo
VB
DA DL
VB Vout VC
VA
Qo
DB
VC
VB
DC
VC

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 The Multi-Emitter BJT
B E3 E2 E1 B C

E3 E2 E1 C

Circuit Symbol Physical Structure

• All three emitters share the same base and

collector.
– The only difference is that instead of having one
IE, we now have IE.
– So, for a multi-emitter BJT, the basic current
relationship becomes:
IE = IE1 + IE2 + IE3 = IC + IB
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 The TTL NAND Operation
• If any input is low:
– The corresponding B-E junction will be forward biased.
– This allows a large base current to flow in RB and makes
QI saturate.
VCC
– QO will turn off and the output will be high.
RB RC

• If all inputs are high: Vout

VA
– All B-E junctions are reverse biased. VB
Qo

– The B-C junction is forward biased. VC

– QI will operate in reverse active mode.

– A large current will flow into the base of QO sending it into
saturation.
– The output voltage will be low.

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 TTL with Totem-Pole Output

VCC Element Purpose

QI Multi-emitter input BJT.

RB RC RCP RB Limits IIL
QS Drive splitter, base
driving current to QO
QP
RC Together with QS provide
VA QS logic inversion.
QI DL
VB QO Output inverting BJT,
active pull-down.
Vout
DL Level-shifting diode.
DCA DCB QO RD Discharge path for QO
QP Active pull-up
RCP Part of active pull-up
RD
DCA, DCB Input clamping diodes to
limit the negative swing
of the inputs.

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 TTL with Totem-Pole Output (Contd.)
• The combination of RCP and QP provide active pull-up.
– This increases the amount of sourcing current available for
turning the load gates on when the output is changing from
low to high.

• QS acts as an emitter follower increasing the amount of

current going into the base of QO ensuring that it will
saturate.
– It also provides logic inversion to make sure that QP and QO
are not on at the same time.

• Diode DL is also used to ensure that the transistors do not

operate at the same time.

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 The VTC of the Basic TTL Gate
• VOH:
– For a low Vin, IB,I will be large.
– However, IC,I will only be the leakage current flowing out of the
base of QS.
• Therefore, IC,I << IB,I and QI is saturated. VCC

– The voltage at the base of QS is RB RC RCP

VB,S = Vin + VCE,I (Sat) FA

IB,I VB,P
– This is not enough to turn QS on, QP
 QS is cut-off. Vin
QI VB,S
QS
DL ON
Sat IC,I off
– IE,S = 0  IB,O = 0  QO is also cut-off. IE,S Vout
IB,O
– VB,P = VCC QO
– Therefore, off
RD
Vout = VOH = VCC – VBE,P (FA) – VD,L (ON)

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 The VTC of the Basic TTL Gate
• VIL:
– As Vin is increased, so will VB,S.
– This will continue until VBE,S = VBE (FA).
• At that point QS will be at Edge Of Conduction.
VCC

– Vin at this point is: RB RC RCP

VIL = VBE,S (FA) – VCE,I (Sat)
FA
QP
QI VB,S
VA
QS
VB
Sat DL ON
E. O. C
IE,S Vout
IB,O
DCA DCB QO
off
RD

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 The VTC of the Basic TTL Gate
• VIB:
– As Vin is increased even more, QS goes into forward active mode.
– IE,S is no longer 0. But IB,O is still 0.
VCC
– The current will go through RD.
This creates a voltage difference across RD.
I RCP
– As Vin rises, so will the voltage across RD. RB RC RC

– Eventually, this will be enough to put QO IB,P FA

at edge of conduction. IC,S QP
QI
– The input voltage needed for that is: VA
QS
VB
Sat DL Off
VIB = VBE,O (FA) + VBE,S (FA) – VCE,I (Sat) FA
IE,S Vout
IB,O
• What about QP and DL? DCA DCB QO
E. O. C
– As IE,S  0, IC,S cannot be 0.
IRD
– Most of IRC will go to IC,S and IB,P will RD

approach 0.
– Therefore, QP and DL will start to go into cutoff mode.

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 The VTC of the Basic TTL Gate
• VOB: VCC

– At that point,
RCP
Vout = VCC – IRC * RC – VBE,P (FA) – VD,L (ON) RB RC

FA
VBE ,O ( FA)
I RC  I RD 
QP
QI VB,S
VA
RD Sat
QS
DL ON
VB
FA
IE,S Vout
IB,O
DCA DCB QO
E. O. C
IRD RD

Therefore,
R 
Vout  VOB  VCC  VBE ,( FA )  C  1  VD ,(ON )
 RD 

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 The VTC of the Basic TTL Gate
• VIH:
– As Vin is increases still more, QS and QO will both saturate.
– The input voltage needed for that is:
VIH = VBE,O (Sat) + VBE,S (Sat) – VCE,I (Sat) V CC

• VOL: RB RC RCP

– At that point: VB,P

QP
Vout = VOL = VCE,O (Sat) QI
VA VB,S
QS
VB
Sat DL
Sat
IE,S Vout
IB,O
DCA DCB QO
E. O. S

IRD RD

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 Will QI Switch to Reverse Active?
• Yes.
– For QI to switch to reverse active, we need
– VBE,I < 0.7

– For Vin > VIH

– VB,I = VBC,I (FB) + VBE,S (Sat) + VBE,O (Sat)
• For typical values, VB,I = 0.6 + 0.8 +0.8 = 2.2 V

– Therefore, QI will switch to RA mode when

Vin > 1.5 V

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 Example
• Calculate the VTC using typical values:
– VOH = VCC – VBE,P (FA) – VD,L (ON) = 5 – 0.7 – 0.7 = 3.6 V
– VIL = VBE,S (FA) – VCE,I (Sat) = 0.7 – 0.2 = 0.5 V

 RC 

– VOB  VCC  VBE ,O ( FA)  1  VD , L (ON )
 RD 
 1.6k 
– VOB  5  0.7    1  0.7  2.5 V
 1k 
– VIB = VBE,O (FA) + VBE,S (FA) – VCE,I (Sat) = 0.7 + 0.7 – 0.2 = 1.2 V

– VOL = VCE,O (Sat) = 0.2 V

– VIH = VBE,O (Sat) + VBE,S (Sat) – VCE,I (Sat) = 0.8 + 0.8 – 0.2 = 1.4 V

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 The VTC
Vout Region Element State
QI Sat
QS Off
1
QP & DL FA, On
QO Off

1 QI Sat
VOH = 3.6 V QS FA
2 2
QP & DL FA, On
QO Off
VOB = 2.5 V
QI Sat

3 3
QS FA

4 QP & DL Off, Off

QO FA
QI Sat
5
QS Sat
VOL = 0.2 V Vin 4
QP & DL Off, Off
QO Sat
VIH = 1.4 V QI RA

VIB = 1.2 V QS Sat

5
VIL = 0.5 V QP & DL Off, Off
QO Sat

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 TTL Fan-out
VCC

VCC
R’CP
VCC
RB RC RCP
Q’P
RB RC
QP
D’L

QI QS
DL

QI QS
Q’O

DCA QO

DCA
RD

RD

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 IIL
• The low input comes from the saturated Q’O of a
previous similar gate.
– Therefore, Vin = VCE,O’ (Sat)
– QI will be saturated VCC

– VB,S will be R’CP

VCC

VCE (Sat) + VCE (Sat) RB RC

Q’P IB,I
– QS is off.
D’L
– IIL = IE,I
VB,S
QI QS
Sat IIL IC,I Off
– IE,I = IC,I + IB,I Q’O
Sat

– IC,I = 0. DCA

VCC  VBE , I ( Sat )  VCE ,O ' ( Sat )

I IL  I B , I 
RD

RB
32
 IOL
• The low output comes from QO being saturated and both QP and
DL being off.
– IOL = IC,O
– IC,O = sbFIB,O VCC
• Max fan-out, when s = 1
– IB,O = IE,S – IRD RB RC RCP

VBE ,O ( Sat ) Off

I RD  QP
RD
– IE,S = IC,S + IB,S QI QS
DL
Off
RA Sat
VCC  VCE , S ( Sat )  VBE ,O ( Sat ) IOL
I C ,S  DCA QO
RC
Sat
– IB,S = IC,I RD
– QI is R.A., therefore,
• IC,I = (1 + bR) IB,I
VCC  VBC , I ( RA)  VBE , S ( Sat )  VBE ,O ( Sat )
I B,I 
RB
33
 Example
• Calculate output-low fan-out using typical values.
VCC  VBE , I ( Sat )  VCE ,O ' ( Sat ) 5  0.8  0.2
I IL    1 mA
RB 4k
VBE ,O ( Sat ) 0.8
I RD    0.8 mA
RD 1k
VCC  VCE , S ( Sat )  VBE ,O ( Sat ) 5  0.2  0.8
I C ,S    2.5 mA
RC 1.6k
VCC  VBC , I ( RA)  VBE , S ( Sat )  VBE ,O ( Sat ) 5  0.7  0.8  0.8
I B,I    .675 mA
RB 4k

IB,S = IC,I = (1 + 0.1) .675 m = .743 mA

61 mA
IE,S = .743 m + 2.5 m = 3.243 mA N OL   61
IB,O = 3.24 m – 0.8 m = 2.44 mA 1 mA
IOL = IC,O = 1 X 25 X 2.44 m = 61 mA

34
 IIH
• The high input comes from QP and DL of the
driving gate both being on.
– This makes QI RA, and QS and QO both saturated.
– We can determine
VB,I = VBE,O (Sat) + VBE,S (Sat) + VBC,I (RA) VCC

VCC
VCC  VB , I R’CP
I B,I  FA RC RCP
RB RB
Q’P IB,I
ON QP
D’L VB,I
QI QS
– Since QI is RA, IIH RA Sat
DL

Q’O
• IIH = IE,I = bR IB,I DCA QO
Sat
RD

35
 IOH
• Since the QI’s of the load gates must be kept in RA mode,
– Vout > VB,I – VBE,I (FA)
VCC

RC RCP

FA
QP RB

QS
DL
ON
VB,I
OFF
QI
IOH
RA
• Therefore,
QO
Off
– VB,P > VB,I – VBE,I (FA) – VD,L (ON) – VBE,P (FA)

VCC  VB , P
I B,P 
RC

• IOH = IE,P = (1 + bF) IB,P

36
 Example
• Calculate output-high fan-out using typical values.

– VB,I = VBE,O (Sat) + VBE,S (Sat) + VBC,I (RA) = 0.8 + 0.8 + 0.7 = 2.3 V

VCC  VB , I 5  2.3
I B,I    0.675 mA
RB 4k

– IIH = IE,I = bR IB,I = 0.1 X 0.675 m = 0.0675 mA

– VB,P > VB,I – VBE,I (FA) – VD,L (ON) – VBE,P (FA)

– VB,P > 2.3 – 0.7 – 0.7 – 0.7 = 0.2 V

VCC  VB , P 5  0.2
I B,P    3 mA
RC 1.6k

– IOH = IE,P = (1 + bF) IB,P = (1 + 25) X 3 m = 78 mA

 78 mA 
N OH     1155
 0.0675 mA 

37
 TTL Power Dissipation
• Output Low State: VCC

– ICC (OL) = IRCP + IRC + IRB IRB RB IRC RC

IRCP RCP

Off
QP

– QP is cut off QI QS
DL
Off
RA Sat
IRCP = 0.
DCA QO
Sat
– QS and QO are Sat. RD

VCC  VCE , S ( Sat )  VBE ,O ( Sat )

I RC 
RC

– QI is RA, therefore
VCC  VCB , I ( RA)  VBE , S ( Sat )  VBE ,O ( Sat )
I RB (OL) 
RB
38
 TTL Power Dissipation
• Output High State: VCC

– ICC (OH) = IRCP + IRC + IRB IRB RB IRC RC

IRCP RCP

FA
QP

– If we assume no loads QI QS
DL
ON
Sat Off
IRCP = 0, IRC = 0.
DCA QO
Off
– QI is saturated and this gate RD

is driven by a similar gate,

therefore

VCC  VBE , I ( Sat )  VCE ,O ' ( Sat )

I RB (OH ) 
RB
39
 Example: TTL Power Dissipation
RC
• Calculate the average power dissipation of the TTL VCC VCC
gate using typical values
IRC IRCP RCP
RCP IRB
RB = 4KΩ RC = 1.6KΩ
– The high input comes from QP and DL of the FA Off
QP QP
driving gate both being on.
ON QI QS
DL
Off
DL
– This makes QI RA, and QS and QO both RA Sat
saturated QP is cut off
QO DCA QO
– QP is cut off  IRCP = 0. Off Sat
RD
– ICC (OL) = IRC + IRB

VCC  VCE , S ( Sat )  VBE ,O ( Sat ) 5  0.2  0.8

I RC    2.5 mA
RC 1.6k

VCC  VCB , I ( RA)  VBE , S ( Sat )  VBE ,O ( Sat ) 5  0.7  0.8  0.8
I RB (OL)    0.675 mA
RB 4k

ICC (OL) = 2.5 m + 0.675 m = 3.175 mA

40
• Output High State: VCC VCC

– ICC (OH) = IRCP + IRC + IRB IRCP

RCP IRB RB IRC RC RCP

– If we assume no loads Off FA

IRCP = 0, IRC = 0. QP QP

Off QI QS ON
– ICC (OH) = IRB DL DL
Sat Off
– QI is saturated and this gate is driven by a
similar gate, therefore QO
QO
Sat Off
VCC  VBE , I ( Sat )  VCE ,O ' ( Sat ) 5  0.8  0.2
I RB (OH )    1 mA RD
RB 4k

ICC (OH) = 1 mA

I CC (OL)  I CC (OH ) 3.175 m  1 m

PDisp  VCC  5  10.4 mW
2 2

Should there be loads connected, ICC (OH) will increase and so will the power dissipation.
TTL NOR Gate

42
TTL OR Gate

43
 Open Collector TTL
• If we remove the active pull-up section, we end
up with a gate that can be used for connecting to
a common bus. VCC

• For a low output, QO

RC
RB
saturates and pulls the
bus line low.
• For a high output,
VA
VB
QI QS

an external pull-up Vout

resistor is added to DCA DCB QO
the bus line.
RD

44
 Open Collector NAND gates
• If any NAND gate produces a low, the whole line
is drawn low.
• The NAND gates cannot produce a logic high.
– They will basically produce a high impedance
state.
– The pull-up resistor will pull the line up to VCC.
VCC

45
 Typical TTL Values (74xx)
• VOH = 3.6 V VCC
• VIL = 0.5 V
• VOB = 2.5 V 4 kW 1.6 kW 120 W

• VIB = 1.2 V
• VOL = 0.2 V QP

• VIH = 1.4 V Vin

QI QS
DL
Vout

• IIL = 1 mA
• IOL = 100 mA DCA QO
– Max N = 100
1 kW
• Ave. PDisp = 10 mW

• Propagation Delay = 10 nS

• PDP = 100

46
 Low Power TTL – LTTL (74Lxx)
• To reduce the power,
we need to reduce ICC. VCC

– The easiest way is to 500 W

40 kW 20 kW
increase the sizes of
the resistors. QP
Vin
– Ave PDisp = 0.9 mW QI QS
DL
Vout

• The price is a DCA QO

reduction in Fan-out 12 kW

and switching speed.

– N = 50

47
 High Speed TTL – HTTL (74Hxx)
• To increase the transition Darlington Pair
speed, we need to increase
the currents. VCC

– The easiest way is to reduce

the sizes of the resistors. 2.8 kW 760 W 58 W

• In addition, a combination QP
known as the Darlington Pair QP2
Vin
replaces QP to increase the QI QS 4 kW
amount of current that can be
supplied to the load when the Vout
output is switching from low DCA QO
to high.
470 W
• Of course, the price is
increased power dissipation.
– Ave. PDisp = 20 mW

48
49