PD - 97322

IRFP4368PbF
Applications
l High Efficiency Synchronous Rectification in
SMPS HEXFET® Power MOSFET
l Uninterruptible Power Supply D VDSS 75V
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
RDS(on) typ. 1.46mΩ
max. 1.85mΩ
G
ID (Silicon Limited) 350Ac
Benefits S ID (Package Limited) 195A
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and D
Avalanche SOA
l Enhanced body diode dV/dt and dI/dt
Capability S
D
G

TO-247AC

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 350c
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited) 250c A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Wire Bond Limited) 195
IDM Pulsed Drain Current d 1280
PD @TC = 25°C Maximum Power Dissipation 520 W
Linear Derating Factor 3.4 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery f 13 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)

Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy e 430 mJ
IAR Avalanche Currentd See Fig. 14, 15, 22a, 22b A
EAR Repetitive Avalanche Energy g mJ

Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case k ––– 0.29
RθCS Case-to-Sink, Flat Greased Surface 0.24 ––– °C/W
RθJA Junction-to-Ambient jk ––– 40

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IRFP4368PbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.077 ––– V/°C Reference to 25°C, ID = 5mAd
RDS(on) Static Drain-to-Source On-Resistance ––– 1.46 1.85 mΩ VGS = 10V, ID = 195A g
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 75V, VGS = 0V
––– ––– 250 VDS = 75V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 650 ––– ––– S VDS = 50V, ID = 195A
Qg Total Gate Charge ––– 380 570 nC ID = 195A
Qgs Gate-to-Source Charge ––– 79 ––– VDS = 38V
Qgd Gate-to-Drain ("Miller") Charge ––– 105 ––– VGS = 10V g
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 275 ––– ID = 195A, VDS =0V, VGS = 10V
RG(int) Internal Gate Resistance ––– 0.80 ––– Ω
td(on) Turn-On Delay Time ––– 43 ––– ns VDD = 49V
tr Rise Time ––– 220 ––– ID = 195A
td(off) Turn-Off Delay Time ––– 170 ––– RG = 2.7Ω
tf Fall Time ––– 260 ––– VGS = 10V g
Ciss Input Capacitance ––– 19230 ––– pF VGS = 0V
Coss Output Capacitance ––– 1670 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 770 ––– ƒ = 100kHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)i ––– 1700 ––– VGS = 0V, VDS = 0V to 60V i
Coss eff. (TR) Effective Output Capacitance (Time Related)h ––– 1410 ––– VGS = 0V, VDS = 0V to 60V h

Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 350c A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 1280 integral reverse G

(Body Diode)di p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 195A, VGS = 0V g
trr Reverse Recovery Time ––– 130 200 ns TJ = 25°C VR = 64V,
––– 140 210 TJ = 125°C IF = 195A
Qrr Reverse Recovery Charge ––– 450 680 nC TJ = 25°C di/dt = 100A/µs g
––– 530 800 TJ = 125°C
IRRM Reverse Recovery Current ––– 9.1 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. Refer to App Notes (AN-1140).
‚ Repetitive rating; pulse width limited by max. junction
temperature.
ƒ Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
„ ISD ≤ 195A, di/dt ≤ 1740A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
… Pulse width ≤ 400µs; duty cycle ≤ 2%.
† Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
‡ Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
‰ Rθ is measured at TJ approximately 90°C.

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 IRFP4368PbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
4.8V 4.8V
BOTTOM 4.5V BOTTOM 4.5V
4.5V
100 100

4.5V

≤60µs PULSE WIDTH ≤60µs PULSE WIDTH

Tj = 25°C Tj = 175°C
10 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
VDS = 25V ID = 195A

RDS(on) , Drain-to-Source On Resistance

≤60µs PULSE WIDTH VGS = 10V
ID, Drain-to-Source Current (A)

2.0
100
(Normalized)

1.5
T J = 175°C
T J = 25°C
10
1.0

1.0 0.5
1 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180

VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

1E+006 12.0
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
ID= 195A
Crss = Cgd 10.0
VGS , Gate-to-Source Voltage (V)

VDS= 60V
Coss = Cds + Cgd
100000 VDS= 38V
C, Capacitance (pF)

8.0
Ciss

10000 6.0
Coss

4.0
Crss
1000
2.0

100 0.0
1 10 100 0 50 100 150 200 250 300 350 400
VDS, Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFP4368PbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 175°C

ID, Drain-to-Source Current (A)

ISD, Reverse Drain Current (A)

100 1000

100µsec

10 T J = 25°C 100
1msec

10msec
1 10
Tc = 25°C
Tj = 175°C
VGS = 0V
Single Pulse DC
0.1 1
0.0 0.4 0.8 1.2 1.6 2.0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

350 95
Id = 5.0mA
300 Limited By Package
90
250
ID, Drain Current (A)

85
200

150
80

100
75
50

0 70
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10. Drain-to-Source Breakdown Voltage

6.0 2000
ID
EAS , Single Pulse Avalanche Energy (mJ)

5.0 TOP 33A

53A
1500 BOTTOM 195A
4.0
Energy (µJ)

3.0 1000

2.0
500
1.0

0.0 0
10 20 30 40 50 60 70 80 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRFP4368PbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50
0.1
0.20
0.10
0.05
0.01
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.02 τJ 0.0145 0.000024
τC
τJ τ
0.01 0.0661 0.000148
τ1 τ2 τ3 τ4
τ1 τ2 τ3 τ4 0.1257 0.002766
0.001 Ci= τi/Ri 0.0838 0.017517
SINGLE PULSE Ci i/Ri
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
0.01
Avalanche Current (A)

Tstart =25°C (Single Pulse)

100

0.05
0.10

10

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming ∆Τj = 25°C and
Tstart = 150°C.
1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth

500 Notes on Repetitive Avalanche Curves , Figures 14, 15:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
400 ID = 195A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
300 4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
200 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
100 tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)

0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFP4368PbF
4.0 30
IF = 72A
VGS(th) , Gate threshold Voltage (V)

3.5 V R = 64V
25
TJ = 25°C
3.0
TJ = 125°C
20
2.5

IRR (A)
ID = 250µA
2.0 ID = 1.0mA 15
ID = 1.0A
1.5
10
1.0

0.5 5
-75 -50 -25 0 25 50 75 100 125 150 175 200 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

30 1000
IF = 108A IF = 72A
920
V R = 64V V R = 64V
25 840
TJ = 25°C TJ = 25°C
TJ = 125°C 760 TJ = 125°C
20 680
Q RR (A)
IRR (A)

600

15 520

440

10 360

280

5 200
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)

Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt
1000
IF = 108A
920
V R = 64V
840
TJ = 25°C
760 TJ = 125°C
680
Q RR (A)

600

520

440

360

280

200
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFP4368PbF
Driver Gate Drive
D.U.T P.W.
Period D=
P.W.
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚
-
„ +
Recovery
Current
Body Diode Forward
Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 21a. Unclamped Inductive Test Circuit Fig 21b. Unclamped Inductive Waveforms

LD
VDS VDS
90%
+
VDD -

D.U.T 10%
VGS VGS
Pulse Width < 1µs
Duty Factor < 0.1% td(on) tr td(off) tf

Fig 22a. Switching Time Test Circuit Fig 22b. Switching Time Waveforms
Id
Vds

Vgs

L
VCC
DUT Vgs(th)
0
1K

Qgs1 Qgs2 Qgd Qgodr

Fig 23a. Gate Charge Test Circuit Fig 23b. Gate Charge Waveform
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IRFP4368PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)

TO-247AC Part Marking Information

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TO-247AC package is not recommended for Surface Mount Application.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/08
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