ARM

Interrupt Processing
Reason for exception
Exception Priorities
Vector table

2k17/EC/146
 Interrupts
●
ARM commonly uses interrupt to mean interrupt signal. On ARM A-profile and R-profile
processors, that means an external IRQ or FIQ interrupt signal. The architecture does not
specify how these signals are used. FIQ is often reserved for secure interrupt sources.
●
ARM processors define two types of “interrupts”:
●
IRQs (Interrupt Requests). These are the “normal” type of interrupt.
●
FIQs (Fast Interrupt Requests). These are an feature that software can optionally use to
increase the speed and/or priority of interrupts from a specific source. For simplicity,
Embedded Xinu does not use FIQs. However, FIQs could be useful for those looking to design
real-time and embedded software on top of or instead of the base Embedded Xinu kernel.
●
Both IRQs and FIQs are examples of exceptions supported by the ARM. Beware that the term
“IRQ” is often used generically, whereas here it specifically refers to the ARM-architecture IRQ
exception.
●
Receiving an IRQ or FIQ
●
When the ARM receives an IRQ, it will enter a special IRQ mode and, by default, begin
execution at physical memory address 0x18. Similarly, when the ARM receives a FIQ, it will
enter a special FIQ mode and, by default, begin execution at physical memory address 0x1C.
Before enabling IRQs or FIQs, software is expected to copy ARM instructions to the
appropriate address. In the case of IRQs, there is only room for one ARM instruction, so it
needs to be a branch instruction to a place where the full handler is stored.
●
Banked registers
●
In IRQ mode and FIQ modes, some registers are banked, meaning that their contents are
dependent on the current processor mode. The advantage of such registers is that their original
values do not need to be explicitly saved by the interrupt handling code. FIQ mode banks more
registers than IRQ mode, but both IRQ mode and FIQ mode bank the stack pointer (sp), which
essentially means that each mode can use its own stack.
 Extended
●
Assembly language handler
 Normal Program Flow vs Exceptions
●
Normally, programs execute sequentially and execute in user mode
●
Exceptions and interrupts break the sequential flow and jump to architecturally defined memory
locations
Exception number IRQ number Secure Vector Non-secure Vector Offset
●
SoftWare Interrpt (SWI) is the system call exception 463 479 IRQ479 . IRQ479 0x7BC
.
. . .
●
Types of ARM exceptions are .
.
. .
. . .

- reset when Cpu reset pin is asserted 18

17
2
1
IRQ2
IRQ1
IRQ2
IRQ1
0x48
0x44
0x40
– Undefined instruction CPU executes undefined op-code 16
15
0
-1
IRQ0
SysTick _S
IRQ0
SysTick_NS 0x3C

– Software interrput SWI instruction 14

13
-2 PendSV_S
Reserved
PendSV_NS
Reserved
0x38
0x30

– Prefetch abort prefetch from an illegal address 12

11
-3
-5
DebugMonitor
SVCall _S
DebugMonitor
SVCall_NS 0x2C

– Data abort read or write at an illegal address 10

9 Reserved
Reserved
– IRQ external interrupt request pin is asserted 8
7 -9 SecureFault 0x1C

– FIQfast interrput request pin is asserted 6

5
-11
-12
UsageFault_S
BusFault_S
UsageFault_NS
BusFault_NS
0x18
0x14
4 -13 MemManage_S MemManage_NS 0x10
3 -13 HardFault _S HardFault_NS 0x0C
2 -14 NMI _S NMI_NS 0x08
1 Reset 0x04
Initial SP value 0x00
 SWI
●
SWIs are also called software traps and allow a user program to call the OS
●
When SWI executes, the processor changes modes from user to supervision and
disables interrupts
●
Types of SWIs in ARM Angel:
– SWI_WriteC write a byte to debug
– SWI_Write0 write null terminated string to debug channel
– SWI_ReadC Read a byte from debug channel
– SWI_Exit Halt emulation
– SWI_EnterOS Put the processor in supervisor mode
– SWI_Clock Return number in centi seconds
– SWI_Time Return the number of secs since JAN1. 1970
–
 Exception Priorities
●
When multiple exceptions are valid at the same time (i.e. more than one exception occurs during execution of an instruction),
they are handled by the core (after completing the execution of the current instruction) according to the following priority
scheme.
●
Reset
●
Data Abort
●
FIQ
●
IRQ
●
Prefetch Abort
●
Undefined Instruction, SWI
The Undefined Instruction and SWI cannot occur at the same time because they are both caused by an instruction entering
the execution stage of the ARM instruction pipeline, so are mutually exclusive and thus they have the same priority.

Please note the difference between prioritization of exceptions (when multiple exceptions are valid at the same time), and the
actual exception handler code. Exception handlers are themselves liable to interruption by exceptions, and so you must be
careful that your exception handlers do not cause further exceptions.
 Exceptions in Detail
●
Reset
●
This is the highest priority interrupt and will be taken whenever it is signalled. The reset handler should initialize the system, and so there is no
need to worry about state preservation etc. When reset is entered, IRQ and FIQ are disabled, and should not be enabled until all interrupt
sources have been initialized to avoid spurious interrupts.
●
Reset is handled in Supervisor (SVC) mode. One of the very first things that a reset handler should do is to set up the stack pointers for all the
other modes, in case of an exception occurring. Note that an exception is not likely to occur in the first few instructions of the reset handler, and
indeed no code should be here to provoke such an event. It would be uncommon to have a SWI, an Undefined instruction, or a memory
access occur when in the reset handler. It is reasonable to assume that your reset handler has been hand crafted to map on to your system
exactly so as to avoid any exceptions taking place during the handling of reset.
●
Data Abort
●
The Data Abort has a higher priority than FIQ so that if both occur simultaneously the Data Abort mode is entered first, before immediately
processing the FIQ exception. When the FIQ handler returns, it will return to the Data abort vector to handle the data abort.
●
A Data Abort exception disables IRQ, and so the data abort handler can not be interrupted by an IRQ unless IRQs have been specifically re-
enabled.
●
Again, it is unlikely that a SWI or an Undef instruction will be executed as part of your handler (though it is possible, and the ARM will enter the
relevant mode and deal with that exception, before returning to the abort handler). If you have a prefetch abort, caused by a read error in your
abort handler (e.g. the handler was placed in an area of memory that is not currently paged in by the memory controller), then the abort
handler will be re-entered. Thus your abort handler should not cause further aborts.
 Exception in detail
●
FIQ
●
With the exception of Reset, this is the highest priority interrupt in terms of being handled. The FIQ exception will disable all IRQs
and FIQs and the handler should be hand crafted to execute as quickly as possible. The same arguments as above apply to
Aborts, SWIs etc interrupting the handler.
●
Similarly, when an FIQ is detected, the ARM core automatically disables further FIQs and IRQs (the F and I bits in the CPSR are
set for the duration of the FIQ handler). This means that an FIQ handler will not be interrupted by another FIQ or an IRQ, unless
you specifically re-enable FIQ or IRQ.
●
For IRQ and FIQ, the default behaviour of the ARM core is to avoid nested (reentrant) interrupts.
●
IRQ
●
When an IRQ occurs, it will be dealt with provided an FIQ or data abort has not been raised at the same time. IRQs are disabled
(and should only be re-enabled after this current source has been cleared*), and are dealt with in the usual manner. As above, the
handler code execution is prone to exceptions as per any other code.
●
*Please note that you must be very careful when re-enabling IRQs inside your IRQ handler. See ADS Developer Guide (3MB
PDF),"Handling Processor Exceptions" chapter or SDT 2.50 User Guide (7MB PDF), section 9.5.2 for information.
●
When an IRQ is detected, the ARM core automatically disables further IRQs (the I bit in the CPSR is set for the duration of the IRQ
handler). This means that an IRQ handler will *not* be interrupted by another IRQ, unless you specifically re-enable IRQ.
●
 Exception in detail
●
Prefetch Abort
●
If the instruction being executed was read in error, then it is flagged as causing a Prefetch Abort, but this exception is only taken
if the instruction reaches the execution stage of the pipeline, and if none of the above exceptions have gone off at this point.
IRQs will be disabled, but other exception sources are enabled, and can be taken during the exception handler if necessary.
●
SWI
●
If the instruction has been fetched (and decoded) successfully, and none of the other exceptions have been flagged, and this
instruction is a SWI instruction, then the ARM will enter SVC mode, and go into the SWI handler code. If the SWI calls another
SWI, then the LR must be stacked away before the "child" SWI is branched to. This can be done in C code in SDT 2.50 by
compiling with the -fz option. See section 9.4.3 of the SDT 2.50 User Guide (7MB PDF) for information. In ADS, -fz is the default
behaviour.
●
Undefined Instruction
●
If the instruction has been fetched (and decoded) successfully, and none of the other exceptions have been flagged, and this
instruction is an undefined instruction, then the ARM will enter Undef mode, and go into the undefined instruction handler code.
The undefined instruction handler will generally either offer the instruction to any co-processors in the system, or flag an error in
the system if none are present. SWI and Undefined Instruction have the same level of priority, as they cannot occur at the same
time. The instruction being executed cannot be both a SWI and an Undefined instruction.
 Important
The undefined instruction and SWI exceptions are mutually exclusive. Each
corresponds to a particular, non-overlapping, decoding of the current instruction.
When FIQs are enabled, and a Data Abort occurs at the same time as an FIQ, the
ARM7TDMI processor enters the Data Abort handler, and proceeds immediately to
the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Data Aborts must have higher priority than FIQs to ensure that the transfer error
does not escape detection. You must add the time for this exception entry to the
worst-case FIQ latency calculations in a system that uses aborts to support virtual
memory.
 Terminology
●
Excpetion refers to internal CPU event like floating point
overflow, MMU fault, trap
●
Interrput refers to external I/O event like device request, reset
 Vector Table
The vector table contains the reset value of the stack pointer, and the start
addresses, also called Exception number IRQ number Secure Vector Non-secure Vector Offset

exception vectors, for all 463 479 IRQ479 .

.
IRQ479 0x7BC

. . .

exception handlers.
.
. . .
. . .
18 2 IRQ2 IRQ2 0x48
17 1 IRQ1 IRQ1 0x44
16 0 IRQ0 IRQ0 0x40

Fig shows the order of the exception 15 -1 SysTick _S SysTick_NS 0x3C

14 -2 PendSV_S PendSV_NS 0x38

vectors in the vector table. The 13 Reserved Reserved 0x30

12 -3 DebugMonitor DebugMonitor

least-significant bit of each vector must 11

10
-5 SVCall _S SVCall_NS 0x2C

be 1, indicating that the exception 9

8
Reserved
Reserved

7 -9 SecureFault 0x1C
handler is Thumb code 6 -11 UsageFault_S UsageFault_NS 0x18
5 -12 BusFault_S BusFault_NS 0x14
4 -13 MemManage_S MemManage_NS 0x10
3 -13 HardFault _S HardFault_NS 0x0C
2 -14 NMI _S NMI_NS 0x08
1 Reset 0x04
Initial SP value 0x00