Received July 4, 2019, accepted July 11, 2019, date of publication July 15, 2019, date of current version

August 9, 2019.
Digital Object Identifier 10.1109/ACCESS.2019.2928693

Experimental Investigation and Comparative

Evaluation of Standard Level Shifted Multi-Carrier
Modulation Schemes With a Constraint GA Based
SHE Techniques for a Seven-Level PUC Inverter
ATIF IQBAL 1 , (Senior Member, IEEE), MOHAMMAD MERAJ 1 , (Member, IEEE),
MOHD TARIQ 2 , (Member, IEEE), KAIF AHMED LODI2 , (Student Member, IEEE),
ALI I. MASWOOD3 , (Senior Member, IEEE), AND SYED RAHMAN 1
1 Department of Electrical Engineering, Qatar University, Doha, Qatar
2 Department of Electrical Engineering, Zakir Husain College of Engineering and Technology, Aligarh Muslim University, Aligarh 202002, India
3 School of Electrical and Electronics Engineering, Nanyang Technological University, Singapore

Corresponding author: Atif Iqbal (atif.iqbal@qu.edu.qa)

This work was supported in part by the Qatar University under High Impact Grant QUHI-CENG-19/20-2, and in part by the Qatar National
Library, Doha, Qatar.

ABSTRACT This paper investigates a reduced switch count topology for seven-level single-phase voltage-
source inverter, nomenclatures as asymmetrical holding capacitor or also known as asymmetrical flying
level capacitor or packed U-cell (PUC). Modular configuration of the inverter consists of one U-cell, four
additional power switches, and one dc link. U-cell network is an arrangement of two semiconductor switches
with one holding or clamping capacitor. Topology offers a reduced switch count solution with simple
control strategy compared to the existing seven-level inverters. Different standard multicarrier sinusoidal
pulse-width modulation techniques (SPWMs) are adapted for the generation of switching gate signals
for the PUC power switches, and these SPWMs are compared with novel optimization-based selective
harmonic elimination (SHE) that employs genetic algorithm (GA) for solving nonlinear SHE equation with
a constraint that eliminated all third-order harmonics efficiently. The investigation that involves analysis and
comparison is done for obtaining reduced total harmonic distortion (THD) by using different level-shifted
multicarrier SPWM schemes along with proposed GA-based SHE. Obtained findings with design of dc
voltage and load current controllers are elaborated and presented in this paper. For better understanding,
the converter topology is tested under different dynamic conditions. Mathematical background developed
on the theoretical basis is verified by numerical simulation software and also validated on the developed
laboratory-scale prototype experimental setup.

INDEX TERMS Multi-level converter, power converter, dc–ac power conversion, pulse-width modulation,
selective harmonic elimination, genetic algorithm.

I. INTRODUCTION limited harmonic distortion, low-switching losses, high out-

Multilevel inverter’s (MLI’s) circuit discretize several DC
sources (photovoltaic DC buses) sequentially and the fun-
damental frequency to construct nearly sinusoidal stepped
AC output voltages. MLI’s offers several advantages with
respect to the traditional two-level configurations, by
The associate editor coordinating the review of this manuscript and
approving it for publication was Sze Sing Lee.
put power capability and power quality with fault toler-
ant structure [1]–[5]. However, the main disadvantages of
multilevel inverters are increased number of DC sources,
power switches, neutral point and load balancing issues,
when compared with counterpart two-level voltage source
inverter (VSI) [6], [7]. Further, control schemes are com-
plex and have a reduced overall efficiency. Therefore,
the cost of MLI’s increases and it becomes non-reliable.

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see http://creativecommons.org/licenses/by/4.0/
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 A. Iqbal et al.: Experimental Investigation and Comparative Evaluation of Standard Level Shifted Multi-Carrier Modulation Schemes
Traditional MLI’s circuits: the neutral point clamped
converters (NPC), Flying capacitors converters (FCC) and
classic cascaded H-bridges configuration addressed these
drawbacks [1]–[15]. The MLI’s are increasingly employed
in solar PV applications due to lower THD in the output
voltage waveform, better power quality with reduced switch-
ing losses and higher efficiency [16]–[20]. Major drawbacks
of neutral point clamped or flying capacitor MLI’s are the
fluctuations in the neutral point voltages [5]. These neutral
point voltage fluctuations occurs because of unequal charging
and discharging of the DC link capacitors in case of NPC and
flying capacitors in case of FLC [7].
In literature several methods are proposed to overcome this
problem, one of them being by modifying the pulse-width
modulation schemes [21]–[25]. However, the complexity of
algorithm and as well the control strategies still poses a huge
challenge. Packed U Cell (PUC) MLI topology is introduced
in [26]–[30] and operates with only one DC source and one
auxiliary capacitor whose voltage is required to be maintained
at a certain percentage of the DC link. The extra auxiliary
capacitor used in the topology is also termed as ‘holding
capacitor’. A seven-level output voltage is generated with
only six semiconductor switches and one extra capacitor
in the DC link [31]–[35]. The balanced output is obtained
when the auxiliary capacitor voltage is maintained at one
third of the DC link voltage. Precisely this control action
is done by using standard PI controller. Major advantages
offered by the PUC topology are reduced switch count with
no need of neutral point voltage control in contrast to NPC
and FLC [36]–[38]. When compared to CHB, the number of
power switches are significantly lower with no requirement of
isolated dc sources. Two power switches and one capacitor
are used to configure the (U) shape cell. Hence, one cell in
the shape of U that is frame by two power switches and one
capacitor is basic unit of this inverter topology. By repeating
this cell, the number of output voltage level can be increased
exponentially. As such by adding two extra U cells, 31-output
voltage level are generated [39], [40]. The rectifier version of
PUC are presented in [27], [41] and major advantage of this
topology, when used in solar PV application is that only one
DC bus is needed, thus simplifying the control of maximum
power point tracking and eliminates the need for sourcing
load balance [42]–[44].
By using simple multicarrier PWM scheme, the switching
signals are generated for PUC inverter [26]. Multicarrier
PWM techniques are natural sampling of a single modulat-
ing or reference waveform (typically being sinusoidal) with
several carrier signals (typically being triangular waveforms).
Using multicarrier PWM schemes, both level- and phase-
shifted modulation can be utilized. In level shifted PWM
techniques, namely three different schemes: the Phase dispo-
sition (PD), Phase Opposition Disposition (POD) and Alter-
nate Phase Opposition Disposition (APOD) are in general
used [45]. These PWM scheme varies in their harmonic
profile and several literature is available on the subject, when
applied to standard MLI [46]–[48]. However, no study is
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reported on the performance of these level shifted PWM when
applied to PUC inverter. The study and analysis is necessary
for PUC inverter in view of its suitability to local grid con-
nected PV application [49]. Therefore, this paper presents a
comprehensive analysis of use of these three-standard level-
shifted PWM scheme for a seven-level single-phase PUC
inverter and enhance the harmonic profile of output wave-
forms. Moreover, in this paper, authors have proposed a novel
GA based SHE, for reduction of harmonics, also the proposed
GA based SHE technique is compared with different types of
level shifted multicarrier PWM techniques.
SHE techniques are employed by using different meth-
ods in literature, such as Numerical based technique and
pattern search techniques. Due to involvement of nonlinear
SHE equation, the conventional techniques exhibit multiple
solution due to trapping in local minima. Moreover, found-
ing an initial point for such techniques is a difficult task.
Therefore, such techniques can be limited to the elimination
of few harmonics. To overcome these drawbacks authors in
this work have used GA for solving nonlinear SHE equa-
tion. Authors have complied this technique together with a
constraint that eliminates all 3rd order harmonics without
increasing the switching frequency. Which marks in reduced
switching losses and effective operation of overall system.
To the best knowledge of the authors, till date, no such
paper exists in the literature which has covered the compara-
tive evaluation between the standard multi carrier level shifted
signals with the constraint SHE technique. The comparison
includes a detailed mathematical analysis along with detailed
simulation and experimental results on packed U cell inverter.
This article is organized as follows: Section 2 explains
Packed U Cell MLI topology and its operation. Section 3
presents control of the PUC inverter. In section 4, design of
DC-link voltage, auxiliary capacitor voltage and load current
controllers are presented. Section 5 gives the spectral analysis
for harmonic components deposition. In section 6 Numerical
simulation modeling is presented. Section 7 discusses GA
based SHE technique. Experimental validation by hardware
prototype analysis are presented in section 8. Conclusion of
this investigation is discussed in the section 9.
II. ASYMMETRICAL HOLDING CAPACITOR OR PACKED
U CELL MULTILEVEL INVERTER
The circuit topology of a seven level Asymmetrical Holding
Capacitor or Packed U Cell (PUC) multilevel inverter intro-
duced in [26], [27] is shown in Fig. 1. The analyzed inverter
topology is modular in nature, in which adding a U cell
increases the number of levels of output voltage waveform.
Adding one U cell that consist of two power switches and
one capacitor, leads to 15 level inverter configuration [41] and
similarly adding two U cell makes it a 31-level inverter [39],
[40]. Appropriate DC voltage levels need to be maintained
across the holding capacitors. In the PUC MLI configuration,
which contain one U cell, there are six power semiconductor
switches, one DC link and one clamping/auxiliary capacitor.
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TABLE 1. Seven level single phase inverter topologies.
FIGURE 1. Single-phase Packed U–cell inverter configuration.
To obtain seven-level output, the auxiliary capacitor voltage
is maintained at one third of the DC link voltage value.
The number of output voltage levels (L) is expressed in
terms of the used clamping capacitors as given by eqn. (1).
L = 2Nc +2 − 1
where, NC is the number of clamping capacitors used and L
is the number of levels generated. Number of output voltage
level is expressed in terms of used number of power switches
NSW as given in eqn. (2).
L = 20.5Nsw − 1
The major advantage of the analyzed inverter topology
can be highlighted from eqns. (1) and (2). It employs much
fewer numbers of auxiliary capacitors and power switches
for creating additional number of levels when compared to
conventional topologies such as NPC, FLC and CHB. Hence,
this reduced switch count inverter topology offers highly
efficient and reliable solution.
A comparison in used number of components in
PUC inverter and other multilevel inverters are described
in Table 1. The analyzed topology of PUC do not use the
clamping diodes unlike NPC and fewer number of clamp-
ing capacitors when compared with FLC. The used power
switches are minimum when compared with all the exist-
ing seven-level inverter topologies. There are eight possible
switching states in a single-phase PUC inverter which are
illustrated in Fig. 2 and tabulated in Table 2. It is observed
that there are three positive levels and three negative levels,
while two states yield zero voltage, namely state 4 and state
5. Zero voltage is produced when load is short circuited
either though main switches or complimentary switches.
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TABLE 2. Output voltage levels in different switching states.
Inverter generates seven-level output voltages [Vdc , Vdc /3,
2/3Vdc , 0, −2/3Vdc , −1/3Vdc , −Vdc ].
The analyzed Packed U Cell MLI offer numerous advan-
tages especially if used in solar photovoltaic conversion appli-
cations. Only one DC/DC converter with Maximum Power
Point Tracking (MPPT) is needed in the whole system. There
is no need of bulky transformer to obtain the required lev-
els, which significantly reduces the cost and the sizing of
(1) PV system making it more suitable for small residential
or off-grid applications. Furthermore, PUC inverter requires
lowest number of power switching components compared
with other multilevel inverters, which reduces number of gate
drive circuits and increases system efficiency and reliability.
Efficiency is enhanced further by employing low frequency
(2) modulation such as Selective Harmonic Elimination (SHE),
while maintaining Total Harmonic Distortion (THD) at min-
imum. Hence, it provides the ability to use a low cost
controller to generate switching pattern and increase the
efficiency by reducing the switching loss of the used power
switches.
III. CONTROL OF PACKED U CELL
MULTILEVEL INVERTER
Fig. 3 shows that the control signal is generated using seven-
level hysteresis controller. The transition condition varies
subsequently and depends on the behavior of the current error.
For example, if the actual state is −V1/3, the reduction of the
current error below the value ‘h’ (the hysteresis band) causes
a transition to state 0. Inversely, if the current error increases
above the ‘h’ (the hysteresis band) value, then, a transition to
the state −2V1/3 occurs.
s2 + 2 ε1 ωn s + ωn2
H (s) = (3)
s2 + 2 ε2 ωn s + ωn2
When actual load current is lower than its reference, then,
the application of a positive voltage across the load allows
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FIGURE 2. Switching states for single-phase AFLC/PUC.
FIGURE 3. Control Block diagram for generation of Gate pulses.
their repprochement. Thus, the positive voltages (sector I
in Fig. 3) are applied when the current error 1i, which is
the difference between actual load current and its reference,
is negative. Contrariwise, the negative voltages (sector II) are
applied when the current error is positive.
Gate signal are generated using level-shifted multicarrier
PWM scheme and the methods analyzed are as follows:
3 Alternative phase opposition disposition (APOD
3 Phase opposition disposition (POD),
3 Phase disposition (PD).
Six triangular carrier of equal magnitude and frequency are
used such that they fully occupy the continuous band in the
range of −Vdc to +Vdc . In APOD scheme each adjacent
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carrier signals are 180◦ phase shifted (Fig. 4c). In the POD
scheme, the positive carriers are in phase opposition to nega-
tive carriers (Fig. 4b). In PD method, all carriers are in phase
and having only level shifts (Fig. 4a).
IV. DESIGN OF DC-LINK VOLTAGE, AUXILIARY
CAPACITOR VOLTAGE AND LOAD CURRENT
CONTROLLERS
A. VOLTAGE CONTROLLERS
In PV applications, using capacitors of electrolytic type will
be less desirable because of short lifetime, mainly when
installed in outdoor temperatures [46]. Film capacitors have
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KI + jωKp
G (jω) = (8)
−ω2 C
The phase of the system is expressed as given in eqn. (9),
−1 ωKp
 
Phase (G (jω)) = −180 + tan (9)
KI
The phase margin of the system is 75◦ . Thus, eqn. (9) can be
expressed as given in eqns. (10-11).
−1 ωKp
 
−180 + 75 = −180 + tan (10)
KI

ωKp
 
75 = tan−1 ; hence, ωKp = 3.73KI
KI

(11)
Using the criterion for the gain margin of the system, the
eqns. (12-14) can be obtained as:
KI + jωKp
G (jω) = (12)
−ω2 C
v
u ωKp 2 + (KI )2
u

|(G (jω))| = t

2 =1 (13)
ω2 C
FIGURE 4. Carrier waveform for (a) PD, (b) POD, and (c) APOD.
2
ωKp + KI2 = ω4 C 2 (14)
By substituting the value of C = 2.2mf in eqn. (14), one gets
very long lifetime; hence these can replace electrolytic capac-
eqns. (15-16):
itors; however their sky level prices limits size but that can be  
used in solar PV inverters. This makes practical limitation for 3.732 + 1 KI2 = (10)4 ∗ 2.22 ∗ 10−6 (15)
DC link capacitor, establishing significant doubly frequency
ripple on DC link and clamping capacitor voltages. This KI = 0.05696; Kp = 0.02124 (16)
double frequency ripple further couples with control loop and
creates distortions in the output current. Therefore, a notch After fine-tuning, both the dc link & clamping capacitor
filter (stop band filter) is needed to be placed on the feedback controllers are set to as follows: KI = 0.06, Kp = 0.02.
signal of DC voltage to attenuate ripple component. Notch
filter is given by the eqn. (3). B. CURRENT CONTROLLERS
where, ωn has double value to that of fundamental fre- On applying the KVL in Fig. (1), the load or grid side eqns.
quency. For maintaining the auxiliary capacitor or holding (17-18) are obtained.
capacitor voltage to 1/3 of DC link voltage a simple PI diL
controller is used to control the DC link voltage and is given For RL load: Van = R ∗ iL + L (17)
dt
in eqn. (4).
diL
dvc For grid load: Van = Rf ∗ iL + Lf + Vac (18)
iL = c (4) dt
dt
Assuming a phase margin of 750 and critically damped sys- x(t) = ωc t + θc (19)
tem with damping factor ε = 1. The transfer function of the
y(t) = ωo t + θo (20)
system are given in eqns. (5-8):
Here R, L are load resistor, reactor and Rf , Lf are the filter
   
KI 1
G (s) = Kp + ∗ (5) inductor internal resistance and inductance. For generation
s sC
of seven level output voltage, one should control the DC-link
sK p + KI & Holding capacitor voltages to Vdc and Vdc /3, respectively.
G (s) = (6)
s2 C This was done by voltage controllers and is given in Fig. 3.
When actual injected current into grid or load is lower than
KI + jωKp reference (current error) then positive voltage across the
G (jω) = (7)
(jω)2 C load has to be applied thus in Fig. 3, sector-I are applied.

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When actual injected current into grid or load is greater than

reference (current error) then negative voltage across the load
has to be applied thus in Fig. 3, sector-II are applied.

V. SPECTRAL ANALYSIS
For analyzing the spectra of all the above three carriers
shown in Fig. 4, two time variables existence is assumed.
Two time variable has been assumed due to the presence of
high frequency modulating wave {x (t)} and low frequency
modulating wave {y (t)} as given in eqns. (19)-(20). As
F(x, y) is separately periodic with respect to the carrier and
reference waveforms, hence it can be expressed as a double
Fourier series arranged about the carrier and fundamental [38]
as given in eqn. (21), as shown at the top of the next page.
On replacing x by ωc t + θc and y by ωo t + θo , eqn. (21) can
be expressed in time-varying form as given in eqn. (22).

A. PHASE DISPOSITION (PD)

The function F(x, y) has no symmetry properties and hence
sine and cosine both terms will be present in the expansion
of the series. For an N level PWM strategy, where N is
odd, the converter arranges N-1 carrier waveforms of equal
amplitude, frequency and the phase.
N’ = (N-1)/2
M = Am /N’Ac
The multilevel voltage can be expressed as in eqn. (23), as
shown at the top of the next page:
Where, Jk denotes a Bessel function of the first kind.
From the above equations, it has three terms:
i) A term giving the amplitude of the fundamental.
ii) A term (for m = 0), it gives the amplitude of the
harmonic multiples of the modulating frequency.
iii) A term (for n = 0), it gives the amplitude of the har-
monics at the carrier frequency and multiples.
where:
Zπ Zπ
1
Fmn = Amn + jBmn = f (x, y)ej(mx+ny) dxdy
2π 2
−π −π
∞
A00 X
f (t) = + [A0n cos(n[ω0 t +θ0 ])+B0n sin(n[ω0 t +θ0 ])]
2
n=1
∞
X
+ [Am0 cos(m[ωc t +θc ]) + Bm0 sin(m[ωc t +θc ])]
m=1
X∞ ∞
X
+ [Amn cos(m[ωc t + θc ]) + n[ω0 t + θ0 ])
m=1 n=−∞
(n6=0)
+ Bmn sin(m[ωc t + θc ]) + n[ω0 t + θ0 ])] (22) FIGURE 5. Dynamic response in Simulation, (a) DC link voltage is
reduced, (b) DC link voltage is increased.
where m is the carrier index variable and n is the baseband
index variable. For PD, the harmonic does not exist at even sidebands centered around each multiple. As in PD, no har-
multiples of the carrier frequency. This term with m fixed monics exist at even multiples of the carrier frequency; hence,
and n variable provides the amplitude of the harmonics in the the THD are lower.

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∞ ∞
1 X X
F(x, y) = A00 + [A0n cos ny + B0n sin ny] + [Am0 cos mx + Bm0 sin mx]
2
n=1 m=1
∞ X
X ∞
+ [Amn cos(mx + ny) + Bmn sin(mx + ny)] (21)
m=1 n=−∞
(n6 =0)

where:

Vdc  
M 2xN 0 +1 − sin 2xN 0 +1 + 4 cos xN 0 +1 .Sin (ωm t + ϕ)



v(t) =
π
+∞
sin (n − 1) xN 0 +1 sin (n + 1) xN 0 +1
( "    # )
Vdc X n 2

+ [1 − (−1) ]. M − + cos nxN 0 +1 sin(nωm t + nϕ)
π n−1 n+1 n
n=3,odd
+∞ +∞
Vdc X 1 X 
Cm,n cos (mωc t + nωm t + nϕ) + Sm,n sin (mωc t + nωm t + nϕ)

+ (23)
π 2N
0
m n=−∞
m=1

where:
X 0 1
Cm,n = 1 + (−1)n 1 − (−1)m Jh (mMN π)
 
n+h
hodd
0
N
X
· cos [m (k − 1) π] {cos [(n + h) xk+1 ] − cos [(n + h) xk ]}
k=1
Sm,n = 1 − (−1)n 1 + (−1)m ∗
  
  0  
   XN  
0
Jn mMN π cos [m (k − 1) π] (xk+1 − xk ) −

 


 


   

k=1
0
N
1 X
   
0
 X 
Jh mMN π cos [m (k − 1) π] . {sin [(n + h) xk+1 ] − sin [(n + h) xk ]} 

 
 
n+h

 

h6=−n,odd k=1

B. ALTERNATIVE PHASE OPPOSITION
DISPOSITION (APOD)
The function F(x, y) has odd symmetry properties and hence
only sine terms will be present in the expansion of the series.
From the eqn. (24), as shown at the top of the page 9. It has
three terms, as defined in the case of PD. In APOD and
POD spectrum analysis, the third term (for n = 0) will not
present any harmonics. When this third term has m fixed
and n variable then only odd-order components exists in each
sideband for APOD and POD.
C. PHASE OPPOSITION DISPOSITION (POD)
The function F(x, y) has odd symmetry properties and hence
only sine terms will be present in the expansion of the series.
As the function is same as APOD, hence the spectrum anal-
ysis and presence of harmonics will be same as presented for
APOD. The frequency ratio defined as, R = Frequency of the
carrier wave (ωc )/Frequency of the reference signal (ωm ).
There are no considerable differences between the dis-
cussed three carrier (PD, APOD and POD) dispositions at
high R due to the shifting of the all harmonics to high
frequencies, which are easily filtered out. When R is not
sufficiently high, they have substantial differences in harmon-
ics. For the case of three phase 7-level PUC using single
phase modulation schemes, harmonics are co-phasal in nature
and hence not present in the current spectrum of the load.
The PD methods is the most promising as it has very little
values of other harmonics. The PD carrier signals will provide
an enhanced harmonic profile for the 7-level PUC inverter,
due to the absence of harmonics at even multiples of the
carrier frequency. The analytical results are verified through
simulation results showing THD in Fig. 6. The results are
validated experimentally and THD results thus captured are
shown in Fig. 12.
VI. SIMULATION RESULTS
Simulation model is developed numerically for three dif-
ferent types of triangular carrier signals used for pulse-
width modulation. The parameters chosen are illustrated
in Table 3 wherein 1 kHz frequency is used for standards
switching scheme and 100 Hz for GA scheme. The results
obtained in Simulink environment are shown in Fig. 5.

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FIGURE 6. Simulation Results: Harmonic spectrum of current; (a) PD,

(b) APOD and (c) POD.

FIGURE 8. Flowchart of GA.

VII. CONSTRAINT GA BASED SHE TECHNIQUES

Seven level waveform shown in fig. 7 is represented for one
time period as a summation of step function in (24).
To analyze waveforms harmonic content, Fourier series
expansion is applied to the waveform. The waveform is con-
sisting of odd and quarter wave symmetry and by virtue of
FIGURE 7. Proposed 7 level phase voltage waveform. these symmetries it is evident that output waveform will be
TABLE 3. The operating conditions for simulation. free from cos component and even harmonic terms in Fourier
series expansion of the output wave. Fourier series expansion
for calculation of sine component is done in equation (25-28)
Z
2
bn = V (t) ∗ sin(nωo t).dt ∀n = 1, 3, 5 . . . (25)
To
To
2E
bn = [4 cos(nωo α1 )+4 cos(nωo α2 ) + 4 cos(nωo α3 )]
nωo To
Dynamic response of the control system is simulated by (27)
step change in the DC link voltage, and corresponding volt- 4E
age and current response is recorded. The holding capacitor bn = [cos(nα1 ) + cos(nα2 ) + cos(nα3 )] (28)
nπ
voltage follows the change in the DC link and the voltage
maintains the seven-level output. The THD for different car- Since, ωo To = 2π, the harmonic amplitude of waveform is
rier schemes are shown in Fig. 6 (a) – (c). calculated in (28). And harmonic amplitude for all third order

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u(t −α1 )−u(t −(π −α1 ))+u(t −α2 )−u(t −(π −α2 )+u(t −α3 )−u(t −(π −α3 ))−u(t −(π +α1 ))
V (t) = E ∗ (24)
+u(t −(2π −α1 ))−u(t −(π +α2 ))+u(t −(2π −α2 ))−u(t −(π +α3 ))+u(t −(2π −α3 ))
Z 
2E u(t −α1 )−u(t −(π −α1 ))+u(t −α2 )−u(t −(π −α2 ))+u(t −α3 )−u(t −(π −α3 ))−u(t −(π +α1 ))
bn = ∗sin(nωo t).dt
To +u(t −(2π −α1 ))−u(t −(π +α2 ))+u(t −(2π −α2 ))−u(t −(π +α3 ))+u(t −(2π −α3 ))
To
(26)
   
4E 1
bn = cos cos−1 (cos(−3nα2 ) + cos(−3nα3 )) + cos(nα2 ) + cos(nα3 ) (32)
nπ 3
s
∞ h h   ii
4E 1 −1 (cos(−3nα ) + cos(−3nα )) + cos(nα ) + cos(nα )
P
nπ cos 3 cos 2 3 2 3
n=3,5,...
THD = h   i (33)
cos 13 cos−1 (cos(−3α2 ) + cos(−3α3 )) + cos(α2 ) + cos(α3 )
4E
π
   
4E 1 4E
bf = cos cos (cos(−3α2 ) + cos(−3α3 )) + cos(α2 ) + cos(α3 ) =
−1
∗ 3ma (34)
π 3 π

harmonic is given in (29) In low switching frequency schemes number to switch-

ing angles are limited to number of steps in phase voltage
4E
b3n = [cos(3nα1 ) + cos(3nα2 ) + cos(3nα3 )] waveform, hence switching frequency is reduced to hundreds
3nπ of hertz. The frequency is considerably low as compared
∀n = 1, 2 . . . (29)
to switching scheme discussed in previous section VI. This
Equating third harmonic amplitude and solving it yields to scheme is very much suitable for high power applications.
equation (30-31)
A. GENETIC ALGORITHM
4E Genetic Algorithm works in the principle of natural genet-
b3n = [cos(3nα1 ) + cos(3nα2 ) + cos(3nα3 )] = 0 (30)
3nπ ics and evolution to optimize nonlinear complex problems.
1 As it is a nature-based algorithm it does not require deriva-
α1 = cos−1 (cos(−3nα2 ) + cos(−3nα3 )) (31)
3n tive information of objective function, which is difficult
Substituting the value of α1 from equation (31), equation (32), to obtained in many engineering optimization problems.
as shown at the top of this page, is obtained. Equations are GA works on input output mapping of objective function.
intentionally modified by eliminating α1 as to get rid of all And by crossover and mutation the individual solutions (chro-
third order harmonic component, without increase switching mosomes) are evolved in GA.
frequency of inverter. The flowchart used for GA in this paper is listed in fig. 8.
• The first goal of modified SHE is achieved by control- The parameters of GA used is listed in table 4.
ling fundamental component to desired value ma .
• Second aim is to eliminate all 3rd order harmonics by TABLE 4. Parameters of GA.

substituting α1 in THD equation, from equation 31.

• Third aim of mitigating harmonics is achieved by
solving for optimum switching angles resulting in
minimum THD.
The transcendental SHE equations that are developed in
above section may have multiple solution as well as unique
and no solution. These equations may be solved by numer- Fig.9 shows the evaluation of fitness over generation, the
ical iterative methods. The conventional numeric methods convergence can be seen to be met after 80 iterations, mean
may lead to local minima, subjected to initial starting point. fitness is the average fitness of all individual and best fitness
To overcome problems of conventional numerical iterative is the fitness value of best chromosome. Fig. 10 shows the
methods, in this work authors have modified SHE equation Harmonic spectrum of current the obtained THD is least from
as an optimization problem listed in equation (35), which is other PWM techniques (Fig. 6).
being solved by Genetic algorithm in this work.
VIII. EXPERIMENTAL RESULTS
F(α2 , α3 ) = min {THD} 

 Experimental test investigation was carried out to validate
Subjected to
 the theoretical findings and numerical simulation results.
(35)
bf = ma (bf in per unit)  Customized hardware comprising of SEMIKRON modules
0 ≤ α1 ≤ α2 ≤ α3 ≤ 90
o o

SKM75GB12T4 was developed. Control codes were written


VOLUME 7, 2019 100613

 A. Iqbal et al.: Experimental Investigation and Comparative Evaluation of Standard Level Shifted Multi-Carrier Modulation Schemes

FIGURE 9. Fitness evolution over the generation.

FIGURE 10. Simulation Results: Harmonic spectrum of current obtained

by GA based SHE.

TABLE 5. Experimental parameters.

in system generator and are processed using FPGA board

Vortex 5. Fluke 42B power analyzer was used to record the
THD in the voltage and current waveform. The experimental
parameters are presented in Table 5.
Power quality measurement analysis was done for the three
different types of multicarrier PWM schemes. Comparison
between the modulation schemes was done on the experimen-
tal prototype setup shown in Fig. 11 (a), where the hardware is
encapsulated with the power switching module, FPGA board
and data acquisition system. The experimental results for
different types of level shifted multicarrier PWM and GA
based SHE output waveforms were captured and analyzed. FIGURE 11. (a) Experimental Setup (b) DC link voltage, holding capacitor
voltage, output voltage and load current. (c) Dynamic response when DC
Results were obtained for both the conditions i.e. steady link voltage is reduced, (d) DC link voltage is increased.
state and transient conditions. A sample result is shown for
PD multicarrier based PWM in Fig. 11 (b). The phase shift
between voltage and current is observed due to inductive for the case of GA based SHE modulation scheme, voltage
nature of the load. The output voltage clearly shows seven spectrum is free from all 3rd order harmonics by applica-
level symmetrical waveform. In line with the theoretical and tion of constraint develop in section VII, without increasing
simulation analysis, it is observed that the GA based SHE switching frequency. The switching frequency required for
method offers the best solution in experimental validation GA based SHE is 350 Hz. The constraint can be used as a
also. In Fig. 12, the THD is minimum in both voltage/current standard one, to eliminate all 3rd order harmonics in SHE

100614 VOLUME 7, 2019

A. Iqbal et al.: Experimental Investigation and Comparative Evaluation of Standard Level Shifted Multi-Carrier Modulation Schemes
FIGURE 12. (a) – (f) Experimental harmonic spectrum of voltage and
current for different types of multicarrier PWM.
PWM also. In Fig. 11 (b) the DC link voltage is traced as
100V and the auxiliary capacitor voltage is held at 1/3rd of the
DC link voltage at 33 V. Although the results obtained from
all techniques applied looks alike, they differ in harmonic
content.
The dynamics of DC link voltage control loop and load cur-
rent loop are tested and the resulting waveforms are presented
in Fig. 11 (c) and Fig. 11 (d). The DC link voltage is ramped
down from 80V to 30V (>60% change) and the transients is
recorded which is shown in Fig. 11 (c). The DC link voltage
is seen to quickly drop to the new value and correspondingly
the holding capacitor voltage follows the change. The output
voltage level drops and the current magnitude drops accord-
ingly. Further, the test conducted by increasing the DC link
voltage value and resultant is shown in Fig. 11 (d). The DC
link voltage ramped up from 14 V to 34 V (>200% increase).
The holding capacitor voltage seems to follow the change and
settle to the new value, the voltage/current follows the change
quickly. It is concluded that both the DC voltage control
loop and load current loop has the large control bandwidth
with fast dynamics.
VOLUME 7, 2019
FIGURE 13. (a) Steady state performance of PUC with Phase Disposition
(PDPWM) (b) Harmonic Spectrum of load voltage and load current with
PD PWM.
Fig. 13 shows experimental results for Phase Disposed
PWM for PUC topology. Steady state waveform for load
voltage [60Vrms ] and load current [2Arms ] are shown
in Fig. 13(a). Fig. 13(b) shows harmonic spectrum of the
load voltage and load current up to 39th harmonic of the
fundamental frequency (50Hz). THD spectrum suggests exis-
tence of lower order harmonics in both voltage and current as
observed in Fig. 13(b).
Power quality measurement was done for the three differ-
ent types of multicarrier PWM and proposed GA based SHE.
Comparison for total harmonic distortion in voltage/current
waveforms is presented in Fig. 12. It can be observed GA
based SHE gives the best overall result in terms of THD,
along with reduction in switching frequency which results
in low switching losses. So, the proposed technique is best
suited for enhanced efficiency of PUC 7 level inverter.
IX. CONCLUSION
Packed U-cell multilevel inverter topology also called
asymmetrical flying capacitor inverter was presented and
examined in this paper. The investigated inverter provides a
reliable solution as it has a reduced switch count (uses fewer
number of power switches) compared to classical MLI’s.
The investigated converter has the capability to generate
seven-level output by utilizing only one extra capacitor only
with the condition that the capacitor voltage must be clamped
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 A. Iqbal et al.: Experimental Investigation and Comparative Evaluation of Standard Level Shifted Multi-Carrier Modulation Schemes
at 1/3rd of the DC link voltage. Hence, a detailed controller
design was performed and has been reported in the paper.
In addition, different types of level shifted multicarrier PWM
was compared with Proposed Ga based SHE. The conclusion/
finding that the GA based SHE approach offer the optimum
solution in terms of lowest THD moreover it eliminated all 3rd
order harmonics without increase in switching frequency. The
dynamic and steady state responses has been performed using
the PD based modulation approach and results thus obtained
for simulation and experimental were similar (in synchroniza-
tion) thus validating the experimental investigation approach
adopted in this paper.
ACKNOWLEDGMENT
The statements made herein are solely the responsibility of
the authors.
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ATIF IQBAL (M’09–SM’11) received the B.Sc.
(Hons.) and M.Sc. degrees in engineering (elec-
trical) from Aligarh Muslim University (AMU),
Aligarh, India, in 1991 and 1996, respectively, and
the Ph.D. degree from Liverpool John Moores Uni-
versity, Liverpool, U.K., in 2006. He is currently
an Associate Professor of electrical engineering
with Qatar University and a former Full Profes-
sor of electrical engineering with AMU. Since
1991, he has been a Lecturer with the Depart-
ment of Electrical Engineering, AMU, where he was a Full Professor until
August 2016. He has published widely in international journals and con-
ferences his research findings related to power electronics and renewable
energy sources. He has authored/coauthored more than 360 research papers,
one book, and two chapters in two other books. He has supervised several
large Research and Development projects. His research interests include
modeling and simulation of power electronic converters, control of multi-
phase motor drives, and renewable energy sources. He is also a Fellow of IE,
India, and IET, U.K. He was a recipient of the Maulana Tufail Ahmad Gold
Medal for standing first at B.Sc.Engg. Exams, in 1991, from AMU. He was
a recipient of the Outstanding Faculty Merit Award AY 2014–2015 and the
Research Excellence Award at Qatar University, Doha, Qatar. He received
Best Research Paper Awards at the IEEE ICIT-2013 and IET-SEISCON-
2013. He is also an Associate Editor of the IEEE TRANSACTION ON INDUSTRY
APPLICATIONS and IEEE ACCESS and a Guest Associate Editor of the IEEE
TRANSACTIONS ON POWER ELECTRONICS.
VOLUME 7, 2019
MOHAMMAD MERAJ received the bachelor’s
degree in electrical engineering from Osmania
University, Hyderabad, India, in 2012, and the
master’s degree in machine drives and power elec-
tronics from IIT Kharagpur, India, in 2014. He is
currently pursuing the Ph.D. degree in electri-
cal engineering with Qatar University, Qatar. His
research interests include power electronics, dc/ac
converter, dc–dc converter, and renewable energy.
MOHD TARIQ (S’10–M’18) obtained the bache-
lor’s degree in electrical engineering from Aligarh
Muslim University, Aligarh, the master’s degree
in machine drives and power electronics from IIT
Kharagpur, and the Ph.D. degree from Nanyang
Technological University, Singapore.
He was a Scientist with an autonomous institute
(NIOT, Chennai) under the Ministry of Earth Sci-
ences, Government of India, and was an Assistant
Professor with the National Institute of Technol-
ogy (NIT), Bhopal, India. He is currently an Assistant Professor with Aligarh
Muslim University. His research interests include power converters, energy
storage devices, and its optimal control for the electrified transportation and
renewable energy application. He was a recipient of the Best Paper Award
from the IEEE Industrial Applications Society (IAS) and the Industrial
Electronic Society, Malaysia Section—Annual Symposium (ISCAIE-2016)
held in Penang, Malaysia.
KAIF AHMED LODI received the B.Tech. degree
from AMU, Aligarh, where he is currently pur-
suing the M.Tech. degree. His research interests
include the areas of nature-based optimization and
power electronics converters and its control.
ALI I. MASWOOD (SM’96) received the B.Eng.
and M.Eng. degrees (Hons.) from the Moscow
Power Engineering Institute, and the Ph.D. degree
from Concordia University, Montreal, Canada.
Having taught in Canada for a number of years,
he joined Nanyang Technological University, Sin-
gapore, in 1991, where he is currently an Associate
Professor. His work in ‘‘FROSIN’’ switch-mode
power supply gave rise to several patents. He is
also the chapter-author of Power Electronics
Handbook (San Diego, USA: Academic Press, 2002). His research interests
include power electronics, particularly in converter generated harmonics,
novel inverter topology, advanced PWM switching, and power quality.
He has authored several international journals and conference publica-
tions on these topics. He is also actively involved in the Local IAS/PELS
Chapter and the Steering Committee of the IEEE Power Electronics and
Drives (PEDS) Conference.
SYED RAHMAN received the B.E. degree (Hons.)
in electrical and electronics engineering from
Osmania University, India, in 2012, and the
M.Tech. degree in machine drives and power elec-
tronics from IIT Kharagpur, India, in 2014. He was
an R&D Design Engineer with GE Healthcare,
India, from October 2014 to January 2016. Since
February 2016, he has been a Research Asso-
ciate with Qatar University. His research interests
include impedance-based converters, solar power
converters, machine drives, modeling, and control.
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