1086 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO.
4, AUGUST 2005
Extended Voltage Swell Ride-Through Capability for
PWM Voltage-Source Rectifiers
Rolando P. Burgos, Member, IEEE, and Eduardo P. Wiechmann, Senior Member, IEEE
Abstract—Voltage swells are one of the most harmful distur-
bances present in industrial power systems, being capable of
severely damaging, breaking, or tripping converters. In the case
of pulsewidth-modulation voltage-source rectifiers (PWM-VSRs),
swells first saturate their control system and then force them
into six-pulse operation if no precautions are taken. This paper
presents an extended ride-through strategy enabling these con-
verters to deal and cope with swells of up to 1.8 p.u. (IEEE Std.
1159 swell definition). The proposed strategy first fully exploits
the dc-link voltage capacity by dynamically entering the over-
modulation region, and secondly by drawing inductive current
in case the former action does not suffice. Dynamic overmodula-
tion makes possible the straight ride-through of 15% and 42%
three-phase and single-phase swells, whereas the modulation
index supervisor/control loop drawing inductive current enables
the ride-through for greater magnitude disturbances, all the
while avoiding saturation of the converter control system. This is
realized using decision-making space vector modulation, and a
control system built over a nonlinear control law directly obtained
from the converter complex state variable model. In this way,
linear and decoupled – axes dynamics are attained, ensuring
a constant dynamic response throughout the whole operating
range. Finally, experimental results from a TMS320C32 dig-
ital-signal-processor-based 5-kVA laboratory prototype subjected
to typical industry single- and three-phase swells ranging from 5%
to 50% are presented. These confirm the predicted performance
and feasibility of the proposed voltage swell ride-through strategy
for PWM-VSRs.
Index Terms—Complex state variables, feedback lineariza-
tion, nonlinear control, overmodulation, pulsewidth-modulation
voltage-source rectifier (PWM-VSR), space-vector modulation
(SVM), voltage swell.
I. INTRODUCTION
T HE pulsewidth-modulation voltage-source rectifier
(PWM-VSR) possesses highly appealing operational
characteristics [1]–[3], such as sinusoidal input currents, con-
trollable input power factor, high-quality regulated dc-link
voltage, current regeneration capacity, and even a harmonic
current compensation capability [4], [5]. Its cost (which is
nearly double that of a diode rectifier) is perhaps the only
reason that has hindered its widespread use. In spite of this,
Manuscript received August 28, 2004; revised December 30, 2004. Ab-
stract published on the Internet April 28, 2005. This work was supported by
FONDECYT (Chilean Fund for Science and Technology Development) under
Project 101-0885.
R. P. Burgos is with the Center for Power Electronics Systems, Virginia
Polytechnic Institute and State University, Blacksburg, VA 24060 USA (e-mail:
rp.burgos@ieee.org).
E. P. Wiechmann is with the Electrical Engineering Department, University
of Concepción, Concepción, Chile.
Digital Object Identifier 10.1109/TIE.2005.851643
0278-0046/$20.00 © 2005 IEEE
PWM-VSRs have become the definite choice for high-perfor-
mance adjustable speed drives, applications that demand tightly
regulated dc-link voltages and present operating cycles with
continual transitions between motoring and regeneration [6].
These transitions amount to significant regenerative energy too
expensive to be burnt or simply spared. In all, the craving for
more efficient ways of handling electric energy and consequent
ever stringent energy policies and regulations will certainly
increase the allure of this converter. Its growing usage and
expanding range of applications is hence easily foreseen.
The attractive features of PWM-VSRs have no doubt brought
the attention of numerous authors, who have further improved
its overall performance by developing different modulation and
control strategies. These have mainly achieved decoupled active
and reactive power flow [7]–[9], linear – -axes dynamics [10],
[11], and optimized dynamic responses [12], [13]. A common
goal in these references has been to improve the dc-link voltage
regulation, which has revealed yet another trait of PWM-VSRs,
their voltage sag ride-through capability. This is certainly of
great importance considering that voltage sags have been re-
ported to be the most common disturbance occurring in indus-
trial power systems [14], [15], having been directly associated
to production and revenue losses. A specific sag-oriented de-
sign and control scheme for PWM-VSRs was presented in [16],
showing the advantages attained by motor drives fed from these
converters.
Voltage swells are but another type of voltage disturbance,
defined as an increase in the rms supply voltage between
1.1–1.8 p.u., and lasting from half a cycle to 1 min. They are
usually produced by switching off large loads, by energizing
capacitor banks, or by faults produced within power systems
themselves. Swells averaging 15% are frequently encountered
on U.S. utility feeders [17]. They might not be as common as
voltage sags, however are much more harmful and disruptive
to static power converters [17], [18]. In fact, they may severely
damage or trip them, causing shutdowns of entire processes.
This overall situation has become even more critical given the
recent industrial trend to increase operating voltages of power
converters(a practice that has pushed semiconductor devices up
to their limit [19], [20]. A closer look to this phenomenon is,
hence, required.
A buck-type or current-source rectifier may easily handle
voltage swells by decreasing its modulation index, i.e., the con-
verter voltage gain, thus thwarting its input voltage increase.
In this way it may regulate the dc-link voltage as long as its
rated voltage is not surpassed. A boost-type VSR on the other
hand counteracts swells by increasing its modulation index,
which compensates for the supply voltage rise and permits it to
regulate the power flow into the dc link, hence controlling its
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS 1087

voltage. Naturally, this compensating action eventually drives This paper presents the complete modeling and analysis of
the modulator into saturation, rendering useless the converter the PWM-VSR using complex state variables, a description
control system. Moreover, saturation also implies that the an- of the decision-making SVM, and a detailed description of its
tiparalleled diodes of the PWM-VSR become forward biased, nonlinear control system with emphasis into the modulation
forcing it into six-pulse mode. The converter then operates index control loop. Finally, experimental results obtained from
with heavily distorted currents, and completely loses control a TMS320C32 digital-signal-processor (DSP)-based 5-kVA
over its dc-link voltage, endangering both the safety and cor- laboratory prototype are presented and used for evaluation
rect operation of the motor drive. Consequently, a shutdown purposes. These confirm the feasibility and excellent results
is mandatorily commanded in order to avoid this harmful, attained by the proposed voltage swell ride-through strategy.
detrimental scenario.
The preceding discussion shows the sheer vulnerability of II. PWM-VSR TOPOLOGY AND MODELING
PWM-VSRs to voltage swells, from where some immediate
A. Converter Topology and Frame Modeling
solutions may be envisioned. A simple and effective method
would be to increase the dc-link voltage rating of the drive, thus The converter topology is shown in Fig. 1 as part of a high-
increasing the range of voltage swells that it could withstand. performance induction motor drive. The drive is comprised of a
This approach however presents severe drawbacks, namely power supply, an inductive input filter, the PWM-VSR itself, a
increased commutation losses, higher on the motor capacitive dc-link filter, a PWM voltage-source inverter (VSI),
terminals [21], and a consequently increased rating and cost and a motor load. The PWM-VSR input–output relationships
of the dc-link capacitor and semiconductor devices. An alternate are obtained per the transfer function concept [24], and are de-
approach has therefore been sought, which consists in keeping fined by
the dc-link voltage to its minimum while dealing with the
disturbance by means of the converter control system. A novel (1)
solution under this approach was proposed in [18], which (2)
basically drew inductive current throughout the disturbance
where is the input phase-voltage vector ,
with the purpose of creating a quadrature voltage drop on the
input filter, which when added to the direct voltage drop on is the modulating vector , is the dc-link
it had the desired effect of maintaining the input terminals voltage, is the dc-link current, and is the input line cur-
voltage of the converter. Naturally, this approach implies a rent vector . Relations (1) and (2) are then employed to
current rating increase for the converter semiconductors in order obtain the state-space model of the PWM-VSR, which is given
to handle both the active and compensation reactive current. below
Also, this work improved the voltage gain of the converter
(3)
and hence its operating range by employing harmonic-injection
sinusoidal PWM .
(4)
This paper presents an extended voltage swell ride-through
capability for PWM-VSRs. The proposed strategy is based where is the power supply phase-voltage vector
on [18] and, therefore, also relies on drawing inductive cur- , is the PWM-VSI dc-link load current,
rent for compensation. This work, however, first fully exploits and and are the respective parasitic resistances of the
the dc-link voltage capacity, allowing the converter to dy-
inductors and capacitor , not shown in Fig. 1 for the
namically enter the overmodulation region if required. In this
sake of clarity.
way single- and three-phase swells of up to 42% and 15%
may be, respectively, ridden through solely compensated by B. Complex State Variable Modeling in the Synchronous
the converter modulation index. Only for higher magnitude Frame
disturbances will the converter draw inductive current, action
regulated by a modulation index supervisor/control loop that The following expression is used to transform frame vari-
ensures a minimum reactive power injection. This loop not ables into space-vector quantities:
only avoids saturation of the control system, but enables the
ride-through of swells up to 1.8 p.u. provided semiconduc- (5)
tors are appropriately current rated. Moreover, decision-making
space-vector modulation (SVM) is employed to determine the where , and , , and are three-phase variables.
space vector conduction times, a modulation strategy with min- The resultant space vector is expressed as follows in the com-
imum processing-capacity requirements that covers both linear plex plane:
and overmodulation regions up to bang-bang
mode [22]. Further, a nonlinear control law directly (6)
derived from the complex state variable model of the converter Hereinafter, bold fonts will be used to represent complex
is employed to linearize and decouple the converter dynamics variables. Notice that (6) expresses a transformation into the
[23]. The converter thus presents a totally decoupled active
stationary – frame. A rotating transformation into the syn-
and reactive power flow, and a constant dynamic response re-
chronous – -axes frame is then easily defined as follows:
gardless of the drive operating point. The latter, as discussed,
is a highly desirable feature for high-performance drives. (7)
1088 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Fig. 1. PWM voltage-source induction motor drive comprising a PWM-VSR and PWM-VSI.

where is a unity space vector rotating at synchronous

speed . The converter input–output relationships (1) and
(2) may then be rewritten in complex space-vector notation as
follows:
(8)
(9)
where stands for the complex conjugate of variable . This
transformation is then applied to (3) and (4), yielding the fol-
lowing system of complex state variables:
(10)
(11)
where constants and are, respectively, defined by
(12)
C. PWM-VSR Complex Signal Flow Graph
Equations (9) and (10) may be represented using signal flow
graphs, a graphic design tool usually employed by engineers to
represent dynamic systems given its utter simplicity and ease of
understanding. The use of complex signal flow graphs has al-
ready been used for studying and analyzing electric machines
[23], where it has produced excellent results. This technique
has not only been shown capable of rendering complex systems
of equations intelligible by visual inspection, but has also pro-
vided the means to directly derivate nonlinear control laws from
them [25]. Fig. 2 shows the complex signal flow graph of the
PWM-VSR. It is basically comprised of three blocks, namely,
inductors, capacitor, and converter, each representing the dy-
namics and transfer characteristics of the complex state vari-
ables and the converter itself.
The input to the whole system is the power supply voltage
vector , which excites the inductor block. This block is also
Fig. 2. PWM-VSR complex signal flow graph.
excited through a negative feedback by current , which depicts
the existent coupling between the and axes (only observable
from rotating frames), and indirectly by the dc-link voltage
through product . The current dynamics are represented by
a first-order delay with time constant . The output of this block
indirectly excites the capacitor block through its interaction
with the converter control signal , which produces the dc-link
current . The capacitor dynamics are also represented by a
first-order delay with time constant . The second excitation to
this block is the PWM-VSI load current , and its output the
dc-link voltage . This signal flows back, exciting the inductor
block and, thus, closing the dynamic interaction between the
converter complex state variables. Notice that the scalar nature
of this block is depicted by using single flow path lines instead.
III. VOLTAGE SWELL ANALYSIS
A. Converter Input Voltage Behavior
The PWM-VSR behavior under disturbed supply conditions
may be analyzed using small-signal modeling. Assuming that
the converter is feeding a constant power load, the following
power balance relation may be written:
(13)
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS 1089

Fig. 3. PWM-VSR ac-side phasor diagrams depicting (a) normal, (b) swelling,
and (c) compensated swell operating conditions.

Hereinafter, capital letter variables represent operating point

values, and lowercase variables deviations around them.
Expanding (13) and solving for yields the following
expression: Fig. 4. Per-unit PWM-VSR behavior under voltage disturbances. Traces
depicted are: modulation index M , input voltage V , and input current I .

(14)
This also allows defining the converter modulation index as
follows, considering a 5% higher dc-link voltage:
which shows that the -axis current component diminishes
when the supply voltage increases, thus maintaining the con-
verter power flow. (19)
The previous swell-induced current reduction also diminishes
These two expressions may be then depicted graphically
the voltage drop on the converter input reactance, implying a
showing the evolution of and as a function of the distur-
possible modulation index decrease given the consequent dis-
bance . This is shown in Fig. 4, confirming that the converter
placement and modification of the converter input voltage .
input current effectively diminishes, and that both and
This effect is shown in Fig. 3(a) and (b), depicting augmented
increase when the supply voltage swells. Notice that the actual
phasor diagrams of unity-power-factor operation under normal
range of swells that can be withstood is fairly small, forcing a
and swelling conditions. Nonetheless, it can be shown, again by
converter shutdown prior to saturation of its modulator. That
small-signal analysis, that will still increase, endangering the
is at for linear modulation, and at if the
converter operation as approaches saturation. This is shown
converter is capable of overmodulation.
below.
The following expression may be obtained from Fig. 3: B. Reactive Power Effect on the Converter Operation
(15) Fig. 3(c) shows that by drawing inductive current, a quadra-
where represents the inductor reactance. Rearranging (15), ture voltage drop on the input filter is produced, effectively
and solving for the input voltage deviation using (14) finally withholding the converter input voltage. This may be shown by
yields studying the following relationship obtained from the afore-
mentioned figure:
(16) (20)

which proves that actually increases when the supply voltage
does, showing the harmful effect that swells have over PWM-
VSRs.
The increase on is described by the following relationship:
and also by taking into consideration that
(21)
If a small-signal perturbation around the operating point is ap-
plied to these equations, the following expression is obtained:

(17)
(22)
where represents the disturbance magnitude in p.u. Equation Then, solving for yields
(17) may be rewritten in p.u. terms considering 10% regulation
on the input reactance as shown below

p.u. (18) (23)

1090
Fig. 5. Decision-making SVM rules for the PWM-VSR [22]. The linear region algorithm determines the sector (S ) and normalized conduction times T and
T , and the overmodulation region algorithm determines the zero state time T and reassigns T and T if required. The -axis component m must be scaled as
shown to enable the if–then rules sector determination.
This equation shows an inverse relation between and ,
therefore, an increase in this current component will reduce the
converter modulation index, which is actually what enables the
proposed control strategy of this paper.
The reactive power effect on the converter operation may also
be observed in the converter complex state variable model. Par-
ticularly, (10) shows that any increase in may be readily coun-
teracted with the cross-coupling product by drawing in-
ductive current, that is negative -axis current. Also, (9) and (11)
show that the dc-link current increases when drawing induc-
tive current, given that both and are negative. Hence,
must be consequently reduced in order to maintain the converter
power flow, which again is the sought-after effect enabling the
proposed control strategy.
IV. DECISION-MAKING SVM WITH OVERMODULATION
A high-performance converter requires a high-performance
control system, where the modulator definitely plays a key
role. SVM has proved to be the most appropriate technique
in terms of voltage utilization, harmonic distortion, commuta-
tion frequency, and ease of implementation in digital control
systems [26]. Moreover, considerable effort has been done
to cover the whole overmodulation range with this technique
[27]–[29]. However, conventional SVM algorithms usually
require solving a system of equations involving sine functions
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005
in the linear range, and solving highly processing-intensive
nonlinear trigonometric equations when operating in the over-
modulation region. This ends up marring the control system
and overall converter performance by limiting its sampling
frequency.
In order to reduce the processing requirements of SVM, a
decision-making technique was presented in [22]. Under this
strategy space-vector conduction times were solely determined
by following a set of if–then rules and by doing simple arith-
metic. The utter simplicity of this technique is such that it was
extended to current-source and matrix converters, where it has
significantly simplified previous modulation strategies [30]. The
normalized time rules for modulating in the linear region are
shown in Fig. 5, which also depicts the voltage reference trans-
formation that enables the direct sector determination by simple
comparison of the and components of . A space-vector
hexagon depicting the boundaries between linear, overmodula-
tion, and bang-bang regions is shown in Fig. 6.
The space-vector sequence employed in this work is shown
below
(24)
where and are the respective conduction times of the lag-
ging and leading space vectors, and is the zero state time.
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS
Fig. 6. Space-vector hexagon depicting: limit of sinusoidal region (M =
:907), linear region, overmodulation region, and bang-bang region.
If the voltage reference lies within the linear region, the fol-
lowing inequality complies:
(25)
and the zero vector is placed for
(26)
If (25) is not complied with, that is
(27)
the voltage reference lies outside the linear region, or equiva-
lently, lies outside the space-vector hexagon. If this is the
case, conduction times are determined using the rules shown
under the overmodulation region algorithm in Fig. 5. Then, if
both times are shorter than 1, the reference lies within the over-
modulation region (Fig. 6), in which case only the two adjacent
space vectors are applied and is nulled. In case either or
are larger than 1, then only that vector is applied for the whole
sampling period, meaning that the voltage reference lies in the
bang-bang region (Fig. 6). These measures naturally introduce
a phase error between the reference voltage and the actual con-
verter voltage . This error is required to achieve the desired
voltage magnitude, and is identical to that produced by conven-
tional techniques. A more detailed description of this modula-
tion technique is given in [22].
V. PROPOSED CONTROL STRATEGY
A. General Description
The proposed control strategy is built over an inner input cur-
rent loop, featuring fully linearized and decoupled – -axes dy-
namics. A key aspect of this control loop is that its control law
is directly obtained from the converter complex state variable
model, significantly simplifying its overall design procedure.
The converter dc-link voltage is regulated by means of the -axis
current component, hence controlling the active power flow for
the PWM-VSI/motor load system. The -axis current compo-
nent on the other hand is used to regulate the converter reac-
tive power flow, trait that enables the PWM-VSR to act as a var
compensator if desired. Paralleled to this loop is the modula-
tion index supervisor loop in charge of the voltage swell
1091
Fig. 7. Block diagram of proposed control scheme. (a) Input current i
control loop in d–q axes frame. (b) DC-link voltage v , reactive power q , and
modulation index M control loops, shown together with the M -supervisor
block and controller selector (q or M controller).
ride-through operation. This control loop is activated within a
control band of , set on the top portion of the overmodula-
tion region . It avoids saturation by reducing the
-axis current component reference, making it inductive if re-
quired. The reactive power loop is meanwhile set on standby,
returning to operation as soon as the disturbance disappears or
leaves the control band. Fig. 7 shows block diagrams of the
input current loop, and also of the dc-link voltage and reactive
power loops, including the supervisor block. A detailed de-
scription of them is given below.
B. Input Current Loop
This paper employs feedback linearization to linearize and
decouple the – -axes dynamics of the converter input current
[31]. The advantage of using this technique in combination with
complex state variable modeling is that control laws may be di-
rectly obtained from the converter complex signal flow graph
(Fig. 2), or from the model itself (10) and (11). This approach
therefore provides highly intuitive means to derive advanced
control laws, being not only of immense simplicity but also of
great intelligibility. Moreover, this approach produces exactly
the same control laws and, hence, the same results obtained with
much more complicated nonlinear control strategies, such as,
for example, with input–output linearization [10], [11], [31].
By inspecting the complex signal flow graph in Fig. 2 it may
be easily determined that there exists a direct link between input
current and the converter control variable through the in-
ductor block. Hence, the current dynamics with respect to
are of first order, which makes the desired linear dynamics for
the input current of the following form:
(28)
1092 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

where is the new input and control variable. Then, by variable , hence, the desired linear dynamics are of first
replacing (28) into (10) and solving for finally yields the order and have the following form:
following control law:
(35)
(29)
where is the new control variable. Therefore, by replacing
(35) into (34) and solving for yields the following non-
where is defined in terms of the current error as follows:
linear control law:

(30) (36)

and the current error is given by , and where is defined by

. Equations (28) and (30) define then two equiva-
lent transfer functions (37)

(31) and , and is the dc-link voltage refer-

ence. Equations (35) and (37) then describe the following linear
where subindex stands for either or axis. The dynamic transfer function:
response of (31) is explicitly determined by constants and ,
and the desired settling time . The values of these constants, (38)
shown below, are set according to the ITAE criterion optimized
for a ramp input [32] where the values of and are also determined using the
ITAE criterion, this time optimized for a step input instead [32].
(32) The values for settling time are shown below

This linear controller structure assures zero steady-state error (39)

even under parameter uncertainties, and improves the loop re-
sponse by providing exponentially convergent tracking-control The dc-link current drawn by the inverter need not be
capability. measured directly, as it can be easily obtained from evaluating
the following expression in the DSP system:
C. DC-Link Voltage Loop
The dc-link voltage dynamics are linearized employing feed- (40)
back linearization. This has the advantage of assuring the con-
verter stability regardless of its operating point, which is a
most desirable feature for PWM-VS’s presenting continual D. Reactive Power Loop
transitions between motoring and regeneration. This particular The converter reactive power is defined by
operating mode has been reported to easily drive systems into
unstable operation if no precautions are taken [33], therefore
(41)
evidencing the significance of this approach. The dynamics of
this state variable are governed by the following input–output
or expanding it simply as
power balance expression
(42)
(33)
where again, just as in (34), is replaced by and nulled
through proper synchronization. A simple proportional plus in-
Notice that current is replaced by its reference , as this loop
tegral (PI) controller is, hence, used to control the converter re-
is designed to be ten times slower than the current control loop,
active power by means of the -axis current component . The
hence, it is assumed to have reached its reference value. This
control law governing this loop is given below
equation is then rearranged into its state-space form as shown
below
(43)
(34)
The reactive power error is defined by , and
is the reactive power reference. Again, (42) and (43) determine
In (34), the -axis term of the supply voltage has been nulled a closed-loop transfer function, specifically defined by
through appropriate synchronization of the space-vector trans-
formation. Then, according to (34) and [31], an explicit relation-
(44)
ship exists between the dc-link voltage derivative and its control
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS 1093

Fig. 8. Experimental waveforms from DSP-based 5-kVA laboratory prototype. (a), (b) AC- and dc-side converter variables at 80% nominal loading when operating
at unity power factor. (c), (d) AC- and dc-side converter variables at 80% nominal loading when operating at leading power factor. Traces depicted are: input phase
voltage v (100 V/div, 2 ms/div); line current i (20 A/div, 2 ms/div); converter line voltage v (200 V/div, 2 ms/div); dc-side current i (10 A/div, 2 ms/div);
dc-link voltage v (200 V/div, 2 ms/div); load current i (10 A/div, 2 ms/div); and d- and q -axes current components i and i (20 A/div, 2 ms/div).

where represents the nominal value of , and constants If the voltage disturbance still demands a higher converter
and set the desired dynamic response. The values of these input voltage, it will push toward saturation. In this case,
constants are shown below, and are determined using Bode plots the modulation index control loop will be activated and the re-
in order to ensure a 20-dB attenuation at the cutoff frequency active power controller parameters saved for proper resuming
of the current loop after the disturbance disappears. This controller swap over the
-axis current occurs whenever lies on the following control
(45) band:

E. Modulation Index and Extended Ride-Through Controller
The converter modulation index is defined according to (19)
as follows:
(46)
For sinusoidal, linear operation is restrained to 0.907, de-
picted in Fig. 6(b) as the area within the inscribed circle. The
area amid this circle and the space-vector hexagon is linear but
not sinusoidal. In this paper, the PWM-VSR is designed to op-
erate at , within the linear region as all conventional
converters do. However, it is allowed to dynamically enter the
overmodulation region under the presence of swells, thus ex-
tending by 10% the range of voltage swells that can be sustained
unaltered. Although overmodulation introduces harmonic dis-
tortion, its transient, sporadic nature does not mar the converter
performance at all.
(47)
Given the linearized dynamics of the converter current , a
simple PI controller is used to regulate the modulation index.
The linear control law governing this loop is
(48)
where , is the loop reference set at 0.98,
and determine the desired dynamic response, and
is the stored reactive power loop reference for . Just as for
the reactive power loop, the values of and are determined
to ensure a 20-dB attenuation at the cutoff frequency of the
current loop
(49)
1094 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Fig. 9. Transient response waveforms from DSP-based 5-kVA laboratory prototype. (a) 25% three-phase swell ride-through operation while operating at unity
power factor. (b) AC waveforms for case (a) during ride-through operation (dynamic overmodulation and reactive current loop are active). (c) 25% three-phase swell

v M
ride-through operation while operating at leading power factor. (d) AC waveforms for case (c) during ride-through operation (dynamic overmodulation and reactive

d q i i i v
current loop are active). Traces depicted are: input phase voltage (a)–(c) 200 V/div, 50 ms/div. (b)–(d) 100 V/div, 2 ms/div), modulation index (0.5 p.u./div,
50 ms/div), - and -axes currents and (20 A/div, 50 ms/div), input current (20 A/div, 2 ms/div), and converter input line voltage (200 V/div, 2 ms/div).

v
Fig. 10. Transient response waveforms from DSP-based 5-kVA laboratory prototype. (a), (b) 15% three-phase swell ride-through operation while operating at

M d q i i i
unity power factor solely compensated by dynamic overmodulation. Traces depicted are: input phase voltage (a) 200 V/div, 50 ms/div, (b) 100 V/div, 2 ms/div),

v
modulation index (0.5 p.u./div, 50 ms/div), - and -axes currents and (20 A/div, 50 ms/div), input current (20 A/div, 2 ms/div), and converter input line
voltage (200 V/div, 2 ms/div).

Notice that, although (23) shows a negative relation between
and , this controller need not have a negative gain given
that the inductive current is herein defined as negative, while
the capacitive current is defined as positive.
The drawing of reactive current for swell compensation nat-
urally increases the converter current rating, even though the
-axis current diminishes to maintain the converter power flow.
The rms input current under the proposed control scheme is
shown below for a disturbance of magnitude
(50)
where is the p.u. converter reactive power compensation
capability, and the p.u. filter reactance. Particularly, a 0.3-p.u.
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS 1095

var-compensating capability is employed in this paper. Then, to

enable 30% three-phase swell ride-through a 0.05-p.u. current
overrate is required, whereas for full swell compensation (80%
swell) a 4.1-p.u. overrate would be required. Nonetheless,
15% swells have been reported as being the most common
by industrial surveys [17], so a 0.05-p.u. current overrate is
recommended to compensate for up to 30% three-phase swells,
also accommodating compensation for 81% single-phase swells.

VI. PERFORMANCE EVALUATION

A. Implementation
A 5-kVA PWM-VSR laboratory prototype was built in Fig. 11. PWM-VSR ac-side space-vector diagrams depicting (a) normal,
order to assess the feasibility of the proposed strategy. The (b) compensated three-phase swell, and (c) compensated single-phase swell
operating conditions. Space vectors rotate at angular speed !t, and the
converter was fed from a variable three-phase 110-V/50–Hz amplitude oscillation in (c) occurs at 2 !t.
power supply, and built using a third-generation insulated gate
bipolar transistor (IGBT) bridge for its power stage. The filter
parameters employed were mH, and mF.
The inductor value was designed to limit the input current
harmonics, while the capacitor employed was simply the size
available in the laboratory. Its value however ensures a 5%
dc-link voltage ripple. For the sake of simplicity, a 5-kW
variable resistive load was used instead of a PWM-VSI. Both
the decision-making space-vector modulator and nonlinear
control system were fully implemented using a DSP-based
digital control system. The system is built over a TMS320C32
processor running at 60 MHz, and has low-latency A/D and
D/A converters, as well as digital outputs (an 8-bit DSP
memory address) used for sending out the gating signals for
the PWM-VSR. The sampling frequency employed was 3 kHz,
internally clocked with one of the two processor timers. The
space-vector modulator operated at a normalized sampling
frequency of 60, and used the remaining timer as a space-vector
sequence counter. The control system parameters employed
were the following: input current settling time ms,
controller parameters , and ;
dc-link voltage settling time ms, con-
troller parameters , and ; controller Fig. 12. Supply voltage space vector v amplitude for single- and three-phase
swells, showing both modulation index M and i compensating regions.
parameters , and ; and controller
parameters , and .

B. Normal Operation
Waveforms depicting unity-power-factor operation of the
PWM-VSR are shown in Fig. 8(a) and (b), each depicting ac-
and dc-side waveforms at 80% loading conditions. Fig. 8(c)
and (d) shows the same waveforms but for var-compensating
operation, where the converter operates with leading power
factor. These waveforms clearly show the correct converter
operation under these conditions. The waveforms depicted are:
input phase voltage , line current , converter line voltage
, dc-side current , dc-link voltage , load current
and - and -axes current components and , respectively.
C. Voltage Swell Ride-Through
Ride-through operation for 25% voltage swells is depicted in
Fig. 9, showing how the PWM-VSR effectively rides through
swells while operating at unity [Fig. 9(a) and (b)] and leading
power factor [Fig. 9(c) and (d)]. These waveforms show how
ride-through is achieved first by overmodulating and secondly
by drawing inductive current. In this way, the modulation index
reference is effectively followed. Particularly, Fig. 9(c) shows
a smoother evolution compared to Fig. 9(a) given that the
converter is compensating reactive power and, hence, was al-
ready operating at a higher modulation index. Fig. 9(b) and (d)
on the other hand show the momentary distortion and inductive
power factor observed in the converter input currents during the
,
ride-through operation, respectively caused by the usage of dy-
namic overmodulation and the modulation index control loop
drawing reactive current. The waveforms depicted in these fig-
ures are: supply phase-voltage , modulation index , - and
-axes currents and , input current , and converter input
line voltage .
1096 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Fig. 13. Transient response waveforms from DSP-based system while operating at unity power factor. (a). (b) 30% single-phase swell ride-through operation

v M
solely compensated by dynamic overmodulation. (c), (d) 48% single-phase swell ride-through operation compensated by overmodulating and drawing inductive

d q i i i v
current. Traces depicted are: input phase voltage (a)–(c) 200 V/div, 50 ms/div; (b)–(d) 100 V/div, 2 ms/div), modulation index (0.5 p.u./div, 50 ms/div),
- and -axes currents and (20 A/div, 50 ms/div), input current (20 A/div, 2 ms/div), and converter input line voltage (200 V/div, 2 ms/div).

D. Extended Voltage Swell Ride-Through Capability
The proposed strategy presents an extended ride-through
characteristic where the PWM-VSR is able to ride through 10%
more swells while maintaining unity-power-factor operation.
This is accomplished by the use of dynamic overmodulation,
which suffices to compensate for voltage swells of up to 15%.
Fig. 10(a) and (b) depicts such a ride-through, where no in-
ductive current is drawn at all. Particularly, a 15% swell is
depicted, showing how it is effectively counteracted by the
proposed control strategy, allowing the converter to maintain
its unity-power-factor operation. Again, the only effect is the
momentary distortion observed in the converter input current.
Nonetheless, this transient and sporadic distortion does not
affect the converter performance or its average distortion. The
waveforms depicted are: supply phase voltage , modulation
index , - and -axes currents and , input current , and
converter input line voltage .
VII. DISCUSSION
A. Single-Phase Swells
The proposed strategy has been developed in terms of phasor
and space-vector analysis, assuming a balanced three-phase
supply. It can be shown however to be just as effective with
single-phase swells. Fig. 11(a) shows a space-vector diagram
equivalent to the phasor diagrams in Fig. 3, with the differ-
ence that space vectors posses the information of all three
phases in them. These space vectors rotate in time at speed
, maintaining a constant relative phase between them, just
as phasors do. Fig. 11(b) depicts a space-vector diagram
under a three-phase swell, effectively counteracted by the
proposed control scheme, and Fig. 11(c) depicts a single-phase
swell space-vector diagram. The only observed difference in
Fig. 11(c) compared to Fig. 11(b) are the space-vectors ampli-
tude oscillations at speed 2 , a consequence of the unbalanced
supply conditions. Consequently, these figures show that the
same principles may be readily employed to compensate and
ride through single-phase swells.
The nature of single-phase swells is such that the proposed
technique may actually sustain much higher single- than three-
phase swells. This can be shown by examining the amplitude of
the voltage supply space vector under single- and three-phase
swells. For the former, its amplitude is defined by
p.u. (51)
and for the latter by
p.u. (52)
where represents the p.u. magnitude of the swell. These
equations, plotted in Fig. 12, demonstrate how the swell effect
is much higher on three-phase than single-phase swells. In fact,
the proposed scheme may sustain up to 42% single-phase swells
unaltered, nearly thrice as severe swells than the three-phase
BURGOS AND WIECHMANN: EXTENDED VOLTAGE SWELL RIDE-THROUGH CAPABILITY FOR PWM VOLTAGE-SOURCE RECTIFIERS
case. This limit is set by the boundary between the modulation
index and compensation regions, also depicted in Fig. 12.
B. Ride-Through Operation Under Single-Phase Swells
Ride-through operation for single-phase swells is shown in
Fig. 13. These waveforms show results completely obtained
with the TMS320C32 DSP-based system, where the power
stage has been modeled and simulated in the processor where
it interacts with the actual converter control system. Resulting
waveforms were viewed, sending them out through D/A con-
verters. Fig. 13(a) and (b) shows the response to a 30% swell
while operating at unity power factor. Ride-through is attained
solely by overmodulating, proving that the proposed strategy
may handle unaltered much more severe single-phase swells.
Fig. 13(c) and (d) shows the response to a 48% swell, com-
pensated this time by transient overmodulation and drawing
inductive current. All these figures show the second-order har-
monic oscillation present in the system variables, both power
stage and control system, a consequence of the unbalanced
supply conditions. Naturally, the effect on the 48% swell is
more significant. The waveforms depicted are: supply phase
voltage , modulation index , - and -axes currents
and , input current , and converter input line voltage . adjustable speed drives,” IEEE Ind. Appl. Mag., vol. 2, no. 1, pp. 16–19,
VIII. CONCLUSION
This paper has presented an extended voltage swell
ride-through strategy for PWM-VSRs. The proposed approach
has successfully dealt with this harmful disturbance, enabling
these converters to effectively ride through swells of up to 80%.
Moreover, 15% and 42% three-phase and single-phase swells
could be ridden straight through solely compensated by using
dynamic overmodulation—implemented by decision-making
SVM. Larger swells were compensated by a modulation index
supervisor control loop drawing inductive current, which by
preventing saturation of the control system also avoided dreaded
converter shutdowns. Furthermore, a nonlinear control strategy
directly obtained from the complex state variable model of
the converter was employed to linearize and decouple the syn-
chronous – -axes dynamics. Consequently, the PWM-VSR
presented a constant dynamic response totally independent
from the operating conditions. Finally, experimental results
from a 5-kVA TMS320C32 DSP-based laboratory prototype
subjected to typically encountered industry swells ranging from
5% to 50% were presented and used for evaluation purposes.
These validated the predicted theoretical results and showed the
feasibility of the proposed voltage swell ride-through strategy.
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Rolando P. Burgos (S’96–M’03) received the Elec-
tronics Engineering, M.S., and Ph.D. degrees with
honors from the University of Concepción, Concep-
ción, Chile in 1997, 1999, and 2002 respectively.
In 2002, he joined, as a Postdoctoral Fellow, the
Center for Power Electronics Systems, Virginia
Polytechnic Institute and State University, Blacks-
burg, where, since 2003, he has been a Research
Scientist. He has been involved in several projects
for marine and aircraft applications. His areas of
interest are the modeling and control of three-phase
static power converters.
Eduardo P. Wiechmann (S’81–M’86–SM’94)
received the Electronics Engineering degree from
Santa Maria University, Valparaiso, Chile, in 1975,
and the Ph.D. degree from Concordia University,
Montreal, QC, Canada, in 1985.
Since 1976, has been with the University of Con-
cepción, Concepción, Chile, where he is currently
a Professor in the Electrical Engineering Depart-
ment. His research interests are power converters,
high-current rectifiers, ac drives, UPS systems, har-
monics, and power-factor control in industrial power
distribution systems. His industrial experience includes more than 6000 hours
working on engineering projects and consulting. He has published numerous
technical papers and has coauthored technical books.
Dr. Wiechmann is currently Chairman of the IEEE Chilean Joint Chapter
of the IEEE Industry Applications, IEEE Power Electronics, and IEEE Indus-
trial Electronics Societies. He is the recipient of the year 2000 Concepción City
Award for Outstanding Achievements in Applied Research.