1 nV/√Hz Low Noise

210°C Instrumentation Amplifier

Data Sheet AD8229
FEATURES FUNCTIONAL BLOCK DIAGRAM
Designed and guaranteed for 210°C operation AD8229
–IN 1 8 +VS
Low noise
RG 2 7 VOUT
1 nV/√Hz input noise
RG 3 6 REF
45 nV/√Hz output noise
High CMRR +IN 4 5 –VS

09412-001
126 dB CMRR (minimum), G = 100 TOP VIEW
(Not to Scale)
80 dB CMRR (minimum) to 5 kHz, G = 1
Excellent ac specifications Figure 1.
100
15 MHz bandwidth (G = 1)
1.2 MHz bandwidth (G = 100) 80

22 V/μs slew rate 60

THD: −130 dBc (1 kHz, G = 1) 40
Versatile
20

VOSI (µV)
±4 V to ±17 V dual supply
0
Gain set with single resistor (G = 1 to 1000)
Specified temperature range –20

−40°C to +210°C, SBDIP package –40

−40°C to +175°C, SOIC package –60

APPLICATIONS –80

Down-hole instrumentation –100

09412-016
–55 –35 –15 5 25 45 65 85 105 125 145 165 185 205 225
Harsh environment data acquisition TEMPERATURE (°C)
Exhaust gas measurements Figure 2. Typical Input Offset vs. Temperature (G = 100)
Vibration analysis

GENERAL DESCRIPTION
The AD8229 is an ultralow noise instrumentation amplifier
designed for measuring small signals in the presence of large
common-mode voltages and high temperatures.
The AD8229 has been designed for high temperature operation.
The process is dielectrically isolated to avoid leakage currents at
high temperatures. The design architecture was chosen to
compensate for the low VBE voltages at high temperatures.
The AD8229 excels at measuring tiny signals. It delivers industry
leading 1 nV/√Hz input noise performance. The high CMRR of
the AD8229 prevents unwanted signals from corrupting the
acquisition. The CMRR increases as the gain increases, offering
high rejection when it is most needed.
The AD8229 is one of the fastest instrumentation amplifiers
available. Its current feedback architecture provides high
bandwidth at high gain, for example, 1.2 MHz at G = 100. The
design includes circuitry to improve settling time after large
input voltage transients. The AD8229 was designed for excellent
distortion performance, allowing use in demanding applications
such as vibration analysis.
Gain is set from 1 to 1000 with a single resistor. A reference pin
allows the user to offset the output voltage. This feature can be
useful when interfacing with analog-to-digital converters.
For the most demanding applications, the AD8229 is available
in an 8-lead side-brazed ceramic dual in-line package (SBDIP).
For space-constrained applications, the AD8229 is available in
an 8-lead plastic standard small outline package (SOIC).

Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com
Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
AD8229 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 6
Predicted Lifetime vs. Operating Temperature ........................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 17
Architecture ................................................................................ 17
Gain Selection ............................................................................. 17
Reference Terminal .................................................................... 17
Input Voltage Range ................................................................... 18
Layout .......................................................................................... 18
Input Bias Current Return Path ............................................... 19
Input Protection ......................................................................... 19
Radio Frequency Interference (RFI) ........................................ 19
Calculating the Noise of the Input Stage ................................. 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21

REVISION HISTORY
2/12—Rev. A to Rev. B
Added 8-Lead SOIC ........................................................... Universal
Changes to Features Section and General Description Section...... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2, Thermal Resistance Section, and Table 3 ... 6
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21

9/11—Rev. 0 to Rev. A
Changes to Features Section and General Description Section...... 1
Changes to Table 2 ............................................................................ 6
Added Predicted Lifetime vs. Operating Temperature Section and
Figure 3; Renumbered Sequentially .............................................. 6
Changes to Figure 18 and Figure 19............................................. 10
Changes to Figure 24 to Figure 28 ................................................ 11
Changes to Figure 29 and Figure 30............................................. 12
Changes to Figure 48 ...................................................................... 15
Changes to Figure 56 ...................................................................... 17
Changes to Power Supplies Section.............................................. 18

1/11—Revision 0: Initial Version

Rev. B | Page 2 of 24
Data Sheet AD8229

SPECIFICATIONS
+VS = 15 V, −VS = −15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 10 kΩ, unless otherwise noted.

Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
COMMON-MODE REJECTION RATIO (CMRR)
CMRR DC to 60 Hz with 1 kΩ Source Imbalance VCM = ±10 V
G=1 86 dB
Temperature Drift TA = −40°C to +210°C 300 nV/V/°C
G = 10 106 dB
Temperature Drift TA = −40°C to +210°C 30 nV/V/°C
G = 100 126 dB
Temperature Drift TA = −40°C to +210°C 3 nV/V/°C
G = 1000 TA = −40°C to +210°C 134 dB
CMRR at 5 kHz VCM = ±10 V
G=1 80 dB
G = 10 90 dB
G = 100 90 dB
G = 1000 90 dB
VOLTAGE NOISE VIN+, VIN− = 0 V
Spectral Density 1: 1 kHz
Input Voltage Noise, eni 1 1.1 nV/√Hz
Output Voltage Noise, eno 45 50 nV/√Hz
Peak to Peak: 0.1 Hz to 10 Hz
G=1 2 µV p-p
G = 1000 100 nV p-p
CURRENT NOISE
Spectral Density: 1 kHz 1.5 pA/√Hz
Peak to Peak: 0.1 Hz to 10 Hz 100 pA p-p
VOLTAGE OFFSET VOS = VOSI + VOSO/G
Input Offset, VOSI 100 µV
Average TC TA = −40°C to +210°C 0.1 1 µV/°C
Output Offset, VOSO 1000 µV
Average TC TA = −40°C to +210°C 3 10 µV/°C
Offset RTI vs. Supply (PSR) VS = ±5 V to ±15 V
G=1 TA = −40°C to +210°C 86 dB
G = 10 TA = −40°C to +210°C 106 dB
G = 100 TA = −40°C to +210°C 126 dB
G = 1000 TA = −40°C to +210°C 130 dB
INPUT CURRENT
Input Bias Current 70 nA
High Temperature TA = 210°C 200 nA
Input Offset Current 35 nA
High Temperature TA = 210°C 50 nA

Rev. B | Page 3 of 24
AD8229 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC RESPONSE
Small Signal Bandwidth –3 dB
G=1 15 MHz
G = 10 4 MHz
G = 100 1.2 MHz
G = 1000 0.15 MHz
Settling Time 0.01% 10 V step
G=1 0.75 µs
G = 10 0.65 µs
G = 100 0.85 µs
G = 1000 5 µs
Settling Time 0.001% 10 V step
G=1 0.9 µs
G = 10 0.9 µs
G = 100 1.2 µs
G = 1000 7 µs
Slew Rate
G = 1 to 100 22 V/µs
THD (FIRST FIVE HARMONICS) f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p
G=1 –130 dBc
G = 10 –116 dBc
G = 100 –113 dBc
G = 1000 –111 dBc
THD + Noise f = 1 kHz, RL = 2 kΩ, VOUT = 10 V p-p, G = 100 0.0005 %
GAIN 2 G = 1 + (6 kΩ/RG)
Gain Range 1 1000 V/V
Gain Error VOUT = ±10 V
G=1 0.01 0.03 %
G = 10 0.05 0.3 %
G = 100 0.05 0.3 %
G = 1000 0.1 0.3 %
Gain Nonlinearity VOUT = −10 V to +10 V
G = 1 to 1000 RL = 10 kΩ 2 ppm
Gain vs. Temperature
G=1 TA = −40°C to +210°C 2 5 ppm/°C
G > 10 TA = −40°C to +210°C −100 ppm/°C
INPUT
Impedance (Pin to Ground) 3 1.5||3 GΩ||pF
Input Operating Voltage Range 4 VS = ±5 V to ±18 V for dual supplies −VS + 2.8 +VS − 2.5 V
Over Temperature TA = −40°C to +210°C −VS + 2.8 +VS − 2.5 V
OUTPUT
Output Swing, RL = 2 kΩ −VS + 1.9 +VS − 1.5 V
High Temperature, SBDIP package TA = 210°C −VS + 1.1 +VS − 1.1 V
High Temperature, SOIC package TA = 175°C −VS + 1.2 +VS − 1.1 V
Output Swing, RL = 10 kΩ −VS + 1.8 +VS − 1.2 V
High Temperature, SBDIP package TA = 210°C −VS + 1.1 +VS − 1.1 V
High Temperature, SOIC package TA = 175°C −VS + 1.2 +VS − 1.1 V
Short-Circuit Current 35 mA

Rev. B | Page 4 of 24
Data Sheet AD8229
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE INPUT
RIN 10 kΩ
IIN VIN+, VIN− = 0 V 70 µA
Voltage Range −VS +VS V
Reference Gain to Output 1 V/V
Reference Gain Error 0.01 %
POWER SUPPLY
Operating Range ±4 ±17 V
Quiescent Current 6.7 7 mA
High Temperature, SBDIP package TA = 210°C 12 mA
High Temperature, SOIC package TA = 175°C 11 mA
TEMPERATURE RANGE
For Specified Performance 5
SBDIP package −40 +210 °C
SOIC package −40 +175 °C
1
Total Voltage Noise = √(eni2 + (eno/G)2)+ eRG2). See the Theory of Operation section for more information.
2
These specifications do not include the tolerance of the external gain setting resistor, RG. For G>1, RG errors should be added to the specifications given in this table.
3
Differential and common-mode input impedance can be calculated from the pin impedance: ZDIFF = 2(ZPIN); ZCM = ZPIN/2.
4
Input voltage range of the AD8229 input stage only. The input range can depend on the common-mode voltage, differential voltage, gain, and reference voltage. See
the Input Voltage Range section for more details.
5
For the guaranteed operation time at the maximum specified temperature, refer to the Predicted Lifetime vs. Operating Temperature section.

Rev. B | Page 5 of 24
AD8229 Data Sheet

ABSOLUTE MAXIMUM RATINGS

PREDICTED LIFETIME VS. OPERATING
Table 2.
TEMPERATURE
Parameter Rating
Supply Voltage ±17 V Comprehensive reliability testing is performed on the AD8229.
Output Short-Circuit Current Duration Indefinite Product lifetimes at extended operating temperature are obtained
Maximum Voltage at –IN, +IN1 ±VS using high temperature operating life (HTOL). Lifetimes are
Differential Input Voltage1 predicted from the Arrhenius equation, taking into account
Gain ≤ 4 ±VS
potential design and manufacturing failure mechanism assump-
4 > Gain > 50 ±50 V/gain
tions. HTOL is performed to JEDEC JESD22-A108. A minimum
Gain ≥ 50 ±1 V
of three wafer fab and assembly lots are processed through
Maximum Voltage at REF ±VS
HTOL at the maximum operating temperature. Comprehensive
reliability testing is performed on all Analog Devices, Inc., high
Storage Temperature Range −65°C to +150°C
temperature (HT) products.
Specified Temperature Range
100k
SBDIP −40°C to +210°C
SOIC −40°C to +175°C
Maximum Junction Temperature 10k

PREDICTED LIFETIME (Hours)

SBDIP 245°C
SOIC 200°C 1k
ESD
Human Body Model 4 kV
100
Charge Device Model 1.5 kV
Machine Model 200 V
10
1
For voltages beyond these limits, use input protection resistors. See the
Theory of Operation section for more information.

Stresses above those listed under Absolute Maximum Ratings 1

09412-200
120 130 140 150 160 170 180 190 200 210
may cause permanent damage to the device. This is a stress OPERATING TEMPERATURE (°C)
rating only; functional operation of the device at these or any Figure 3. Predicted Lifetime vs. Operating Temperature
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute Refer to the AD8229 Predicted Lifetime vs. Operating Temperature
maximum rating conditions for extended periods may affect document for the most up-to-date reliability data.
device reliability.
THERMAL RESISTANCE
θJA is specified for a device in free air using a 4-layer JEDEC
printed circuit board (PCB).

Table 3.
Package Type θJA Unit
8-Lead SBDIP 100 °C/W
8-Lead SOIC 121 °C/W

ESD CAUTION

Rev. B | Page 6 of 24
Data Sheet AD8229

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD8229
–IN 1 8 +VS

RG 2 7 VOUT

RG 3 6 REF

+IN 4 5 –VS

09412-003
TOP VIEW
(Not to Scale)

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 −IN Negative Input Terminal.
2, 3 RG Gain Setting Terminals. Place resistor across the RG pins to set the gain. G = 1 + (6 kΩ/RG).
4 +IN Positive Input Terminal.
5 −VS Negative Power Supply Terminal.
6 REF Reference Voltage Terminal. Drive this terminal with a low impedance voltage source to level-shift the output.
7 VOUT Output Terminal.
8 +VS Positive Power Supply Terminal.

Rev. B | Page 7 of 24
AD8229 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, VS = ±15, VREF = 0, RL = 2 kΩ, unless otherwise noted.
60
N: 200 N: 201
60 MEAN: 12.2 MEAN: 4.0
σ: 8.2 σ: 0.7
50
50

40
40
HITS

HITS
30
30

20 20

10 10

0
09412-004
0

09412-007
–60 –40 –20 0 20 40 60 0 2 4 6 8
VOSI ±15V (µV) IBIAS OFFSET (nA)

Figure 5. Typical Distribution of Input Offset Voltage Figure 8. Typical Distribution of Input Offset Current

N: 200 N: 200
MEAN: 0.9 MEAN: 10.9
35 σ: 161.2 120 σ: 3.7

30 100

25
80
HITS

HITS

20
60
15
40
10

5 20

0 0
09412-005

09412-008
–600 –400 –200 0 200 400 600 800 –60 –40 –20 0 20 40 60
VOSO ±15V (µV) CMRR G1 (µV/V)

Figure 6. Typical Distribution of Output Offset Voltage Figure 9. Typical Distribution of Common Mode Rejection, G = 1

INVERTING N: 200 N: 198

40 NONINVERTING MEAN: –6.1 MEAN: –9.1
35
σ: 6.7 σ: 9.9
35 N: 200
MEAN: –10.1 30
σ: 6.9
30
25
25
HITS
HITS

20
20
15
15

10
10

5 5

0 0
09412-015
09412-006

–50 –40 –30 –20 –10 0 10 20 30 –60 –40 –20 0 20

IBIAS (nA) NINV G ERROR G1 10K ±15V (µV/V)

Figure 7. Typical Distribution of Input Bias Current Figure 10. Typical Distribution of Gain Error, G = 1

Rev. B | Page 8 of 24
Data Sheet AD8229
3 3
G = 1, VS = ±5V 25°C
210°C
2 2
COMMON-MODE VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

1 1

0 0

–1 –1

–2 –2
25°C
G = 100, VS = ±5V 210°C
–3 –3

09412-009

09412-012
–5 –4 –3 –2 –1 0 1 2 3 4 5 –5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 11. Input Common-Mode Voltage vs. Output Voltage, Figure 14. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±5 V; G = 1 Dual Supply, VS = ±5 V; G = 100

10 10
G = 1, VS = ±12V 25°C
8 210°C 8

6 6
COMMON-MODE VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

4 4

2 2

0 0

–2 –2

–4 –4

–6 –6
25°C
–8 –8
210°C
G = 100, VS = ±12V
–10 –10
09412-010

09412-013
–12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 12. Input Common-Mode Voltage vs. Output Voltage, Figure 15. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±12 V; G = 1 Dual Supply, VS = ±12 V; G = 100

14 14
12 G = 1, VS = ±15V 25°C 12
210°C
10 10
COMMON-MODE VOLTAGE (V)

COMMON-MODE VOLTAGE (V)

8 8
6 6
4 4
2 2
0 0
–2 –2
–4 –4
–6 –6
–8 –8
–10 –10
25°C
–12 –12 G = 100, VS = ±15V 210°C
–14 –14
09412-014
09412-011

–15 –10 –5 0 5 10 15 –15 –10 –5 0 5 10 15

OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

Figure 13. Input Common-Mode Voltage vs. Output Voltage, Figure 16. Input Common-Mode Voltage vs. Output Voltage,
Dual Supply, VS = ±15 V; G = 1 Dual Supply, VS = ±15 V; G = 100

Rev. B | Page 9 of 24
AD8229 Data Sheet
0 70
GAIN = 1000 VS = ±15V
–5 60

–10 50
INPUT BIAS CURRENT (nA)

GAIN = 100
–15 40
–12.28V
–20 30

GAIN (dB)
GAIN = 10
–25 20

–30 12.60V
10
GAIN = 1
–35 0

–40 –10

–45 –20

–50 –30

09412-068

09412-017
–14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 100 1k 10k 100k 1M 10M 100M
COMMON-MODE VOLTAGE (V) FREQUENCY (Hz)
Figure 17. Input Bias Current vs. Common-Mode Voltage Figure 20. Gain vs. Frequency

160 160
GAIN = 1000 GAIN = 1000
GAIN = 100 GAIN = 100
140 GAIN = 10 140 GAIN = 10
GAIN = 1 GAIN = 1

120 120
POSITIVE PSRR (dB)

100 100 BANDWIDTH

CMRR (dB)

LIMITED
80 80

60 60

40 40

20 20

0 0
09412-069

09412-018
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 18. Positive PSRR vs. Frequency Figure 21. CMRR vs. Frequency

160 160
GAIN = 1000
GAIN = 100
140 GAIN = 10 140
GAIN = 1
NEGATIVE PSRR (dB)

120 120

100 100
CMRR (dB)

GAIN = 1000 BANDWIDTH

80 80 GAIN = 100 LIMITED
GAIN = 10
GAIN = 1
60 60

40 40

20 20

0 0
09412-070

09412-019

1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M

FREQUENCY (Hz) FREQUENCY (Hz)
Figure 19. Negative PSRR vs. Frequency Figure 22. CMRR vs. Frequency, 1 kΩ Source Imbalance

Rev. B | Page 10 of 24
Data Sheet AD8229
12 20
CHANGE IN INPUT OFFSET VOLTAGE (µV)

10 15

8 10

CMRR (µV/V)
6 5

4 0

2 –5

0 –10

09412-071
0 100 200 300 400 500 600 700 –55 –25 5 35 65 95 125 155 185 215

09412-023
WARM-UP TIME (s)
TEMPERATURE (°C)

Figure 23. Change in Input Offset Voltage (VOSI) vs. Warm-Up Time Figure 26. CMRR vs. Temperature, G = 1, Normalized at 25°C

200 10.0 12

150 7.5
10
INPUT OFFSET
INPUT OFFSET CURRENT (nA)

CURRENT
INPUT BIAS CURRENT (nA)

100 5.0

SUPPLY CURRENT (mA)

8
50 2.5
INPUT BIAS
0 CURRENT 0 6

–50 –2.5
4

–100 –5.0
2
–150 –7.5

–200 –10.0 0
09412-072

–55 –25 5 35 65 95 125 155 185 215

09412-074
–55 –25 5 35 65 95 125 155 185 215
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 24. Input Bias Current and Input Offset Current vs. Temperature Figure 27. Supply Current vs. Temperature, G = 1

150 50

100 40 ISHORT+
SHORT CIRCUIT CURRENT (mA)

30
50
20
GAIN ERROR (µV/V)

0
10

–50 0

–100 –10

–20
–150
–30
–200
–40 ISHORT–

–250 –50
09412-075

–55 –25 5 35 65 95 125 155 185 215

09412-073

–55 –25 5 35 65 95 125 155 185 215

TEMPERATURE (°C) TEMPERATURE (°C)

Figure 25. Gain Error vs. Temperature, G = 1, Normalized at 25°C Figure 28. Short-Circuit Current vs. Temperature, G = 1

Rev. B | Page 11 of 24
AD8229 Data Sheet
30 +VS

–0.4
+SR

REFERRED TO SUPPLY VOLTAGES

25
–0.8

OUTPUT VOLTAGE SWING (V)

–SR
–1.2
SLEW RATE (V/μs)

20
–55°C –40°C +25°C +85°C
+125°C +150°C +210°C +225°C
15 +2.0

+1.6
10
+1.2

+0.8
5
+0.4

0 –VS

09412-076
–55 –25 5 35 65 95 125 155 185 215

09412-029
4 6 8 10 12 14 16 18
TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 29. Slew Rate vs. Temperature, VS = ±15 V, G = 1 Figure 32. Output Voltage Swing vs. Supply Voltage, RL = 10 kΩ

25 +VS
+SR
–0.4

REFERRED TO SUPPLY VOLTAGES

–SR
20 –0.8

OUTPUT VOLTAGE SWING (V) –1.2

SLEW RATE (V/μs)

–55°C –40°C +25°C +85°C

15 +125°C +150°C +210°C +225°C
+2.0

10 +1.6

+1.2

5 +0.8

+0.4

0 –VS
09412-077

09412-030
–55 –25 5 35 65 95 125 155 185 215 4 6 8 10 12 14 16 18
TEMPERATURE (°C) SUPPLY VOLTAGE (±VS)

Figure 30. Slew Rate vs. Temperature, VS = ±5 V, G = 1 Figure 33. Output Voltage Swing vs. Supply Voltage, RL = 2 kΩ

+VS 15
VS = ±15V
–0.5 –55°C –40°C +25°C +85°C
+125°C +150°C +210°C +225°C
10 –55°C
REFERRED TO SUPPLY VOLTAGES

–1.0
–40°C
OUTPUT VOLTAGE SWING (V)

–1.5 +25°C
+85°C
+125°C
INPUT VOLTAGE (V)

–2.0 5
+150°C
+210°C
–2.5 +225°C
0

+2.5
+2.0 –5

+1.5
+1.0 –10

+1.5
–VS –15
09412-031
09412-028

4 6 8 10 12 14 16 18 100 1k 10k 100k

SUPPLY VOLTAGE (±VS) LOAD (Ω)

Figure 31. Input Voltage Limit vs. Supply Voltage Figure 34. Output Voltage Swing vs. Load Resistance

Rev. B | Page 12 of 24
Data Sheet AD8229
+VS 1000
VS = ±15V
–0.4
REFERRED TO SUPPLY VOLTAGES

–0.8
OUTPUT VOLTAGE SWING (V)

100
–1.2 GAIN = 1

NOISE (nV/√Hz)
–1.6
–55°C –40°C +25°C +85°C
+125°C +150°C +210°C +225°C
10
+1.8 GAIN = 10

+1.6 GAIN = 100

+1.2 1
+0.8 GAIN = 1000
+0.4

–VS 0.1

09412-037
09412-032
10μ 100μ 1m 5m 1 10 100 1k 10k 100k
OUTPUT CURRENT (A) FREQUENCY (Hz)

Figure 35. Output Voltage Swing vs. Output Current Figure 38. Voltage Noise Spectral Density vs. Frequency

10
GAIN = 1
8
GAIN = 1000, 100nV/DIV
6
NONLINEARITY (ppm/DIV)

2
GAIN = 1, 2μV/DIV
0

–2

–4

–6

09412-086
–8 1s/DIV
–10
09412-083

–10 –8 –6 –4 –2 0 2 4 6 8 10
OUTPUT VOLTAGE (V)

Figure 36. Gain Nonlinearity, G = 1, RL = 10 kΩ Figure 39. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1, G = 1000

10 16
GAIN = 1000
15
8
14
6 13
NONLINEARITY (ppm/DIV)

12
4
11
NOISE (pA/√Hz)

2 10
9
0
8
–2 7
6
–4
5
–6 4
3
–8
2
–10 1
09412-084

09412-087

–10 –8 –6 –4 –2 0 2 4 6 8 10 1 10 100 1k 10k 100k

OUTPUT VOLTAGE (V) FREQUENCY (Hz)

Figure 37. Gain Nonlinearity, G = 1000, RL = 10 kΩ Figure 40. Current Noise Spectral Density vs. Frequency

Rev. B | Page 13 of 24
AD8229 Data Sheet

5V/DIV

640ns TO 0.01%
896ns TO 0.001%

0.002%/DIV

09412-088
50pA/DIV 1s/DIV 2µs/DIV

09412-091
TIME (µs)

Figure 41. 1 Hz to 10 Hz Current Noise Figure 44. Large Signal Pulse Response and Settling Time (G = 10), 10 V Step,
VS = ±15 V

30
G=1 G=1

VS = ±15V
25 25°C 175°C
210°C 225°C
OUTPUT VOLTAGE (V p-p)

20

50mV/DIV
15

10

VS = ±5V
5

09412-048
0 1μs/DIV
09412-089

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 42. Large Signal Frequency Response Figure 45. Small Signal Response, G = 1, RL = 10 kΩ, CL = 100 pF

G = 10

5V/DIV
20mV/DIV

750ns TO 0.01%
872ns TO 0.001%

0.002%/DIV 25°C 175°C

210°C 225°C
09412-049

2µs/DIV
09412-090

1μs/DIV
TIME (µs)

Figure 43. Large Signal Pulse Response and Settling Time (G = 1), 10 V Step, Figure 46. Small Signal Response, G = 10, RL = 10 kΩ, CL = 100 pF
VS = ±15 V

Rev. B | Page 14 of 24
Data Sheet AD8229
25°C 1400
G = 100
175°C
210°C
225°C 1200

1000

SETTLING TIME (ns)

SETTLED TO 0.001%
800

SETTLED TO 0.01%
600

400

200

09412-094
20mV/DIV 2µs/DIV
0

09412-092
2 4 6 8 10 12 14 16 18 20
STEP SIZE (V)
Figure 47. Small Signal Response, G = 100, RL = 10 kΩ, CL = 100 pF Figure 50. Settling Time vs. Step Size, G = 1

25°C 1
G = 1000 NO LOAD G = 1, SECOND HARMONIC
175°C
210°C 2kΩ LOAD VOUT = 10V p-p

AMPLITUDE (Percentage of Fundamental)

225°C 600Ω LOAD

0.1

0.01

0.001

0.0001
09412-095

20mV/DIV 10µs/DIV

0.00001

09412-096
10 100 1k 10k 100k
FREQUENCY (Hz)
Figure 48. Small Signal Response, G = 1000, RL = 10 kΩ, CL = 100 pF Figure 51. Second Harmonic Distortion vs. Frequency, G = 1

1
G=1 NO LOAD G = 1, THIRD HARMONIC
2kΩ LOAD VOUT = 10V p-p
AMPLITUDE (Percentage of Fundamental)

600Ω LOAD

0.1

0.01

0.001

NO LOAD 0.0001
09412-093

CL = 100pF
50mV/DIV CL = 147pF 1µs/DIV
0.00001
09412-097

10 100 1k 10k 100k

FREQUENCY (Hz)
Figure 49. Small Signal Response with Various Capacitive Loads, G = 1, Figure 52. Third Harmonic Distortion vs. Frequency, G = 1
RL = Infinity

Rev. B | Page 15 of 24
AD8229 Data Sheet
1 1
NO LOAD G = 1000, SECOND HARMONIC VOUT = 10V p-p
2kΩ LOAD VOUT = 10V p-p RL ≥ 2kΩ
AMPLITUDE (Percentage of Fundamental)

600Ω LOAD

0.1
0.1

0.01

THD (%)
0.01
GAIN = 100
0.001

GAIN = 1000
0.001
0.0001 GAIN = 10
GAIN = 1

0.0001 0.00001

09412-098

09412-100
10 100 1k 10k 100k 10 100 1k 10k 100k
FREQUENCY(Hz) FREQUENCY (Hz)

Figure 53. Second Harmonic Distortion vs. Frequency, G = 1000 Figure 55. THD vs. Frequency

1
NO LOAD G = 1000, THIRD HARMONIC
2kΩ LOAD VOUT = 10V p-p
AMPLITUDE (Percentage of Fundamental)

600Ω LOAD

0.1

0.01

0.001

0.0001
09412-099

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 54. Third Harmonic Distortion vs. Frequency, G = 1000

Rev. B | Page 16 of 24
Data Sheet AD8229

THEORY OF OPERATION
I VB I

IB IB
COMPENSATION COMPENSATION
A1 A2 R3
5kΩ
C1 C2 R4 +VS
NODE 1 5kΩ

NODE 2 A3 OUTPUT

+VS +VS R5 +VS

R1 R2 5kΩ R6 –VS
3kΩ 3kΩ
5kΩ
+VS +VS REF
–IN Q1 Q2 +IN
RG
–VS –VS –VS
RG– RG+

09412-058
–VS –VS

Figure 56. Simplified Schematic

ARCHITECTURE Table 5. Gains Achieved Using 1% Resistors

The AD8229 is based on the classic 3-op-amp topology. This 1% Standard Table Value of RG (Ω) Calculated Gain
topology has two stages: a preamplifier to provide differential 6.04 k 1.993
amplification followed by a difference amplifier that removes the 1.5 k 5.000
common-mode voltage and provides additional amplification. 665 10.02
Figure 56 shows a simplified schematic of the AD8229. 316 19.99
The first stage works as follows. To keep its two inputs matched, 121 50.59
Amplifier A1 must keep the collector of Q1 at a constant voltage. It 60.4 100.34
does this by forcing RG− to be a precise diode drop from –IN. 30.1 200.34
Similarly, A2 forces RG+ to be a constant diode drop from +IN. 12.1 496.9
Therefore, a replica of the differential input voltage is placed 6.04 994.4
across the gain setting resistor, RG. The current that flows 3.01 1994.355
through this resistance must also flow through the R1 and R2
resistors, creating a gained differential signal between the A2 The AD8229 defaults to G = 1 when no gain resistor is used.
and A1 outputs. The tolerance and gain drift of the RG resistor should be added
to the AD8229’s specifications to determine the total gain accuracy
The second stage is a G = 1 difference amplifier, composed of
of the system. When the gain resistor is not used, gain error and
Amplifier A3 and the R3 through R6 resistors. This stage removes
gain drift are minimal.
the common-mode signal from the amplified differential signal.
RG Power Dissipation
The transfer function of the AD8229 is
The AD8229 duplicates the differential voltage across its inputs
VOUT = G × (VIN+ − VIN−) + VREF
onto the RG resistor. The RG resistor size should be chosen to
where: handle the expected power dissipation.
6 kΩ REFERENCE TERMINAL
G =1+
RG The output voltage of the AD8229 is developed with respect to
GAIN SELECTION the potential on the reference terminal. This is useful when the
output signal must be offset to a precise midsupply level. For
Placing a resistor across the RG terminals sets the gain of the
example, a voltage source can be tied to the REF pin to level-
AD8229, which can be calculated by referring to Table 5 or by
shift the output so that the AD8229 can drive a single-supply
using the following gain equation:
ADC. The REF pin is protected with ESD diodes and should
6 kΩ not exceed either +VS or −VS by more than 0.3 V.
RG =
G −1

Rev. B | Page 17 of 24
AD8229 Data Sheet
For best performance, source impedance to the REF terminal Common-Mode Rejection Ratio over Frequency
should be kept well below 1 Ω. As shown in Figure 56, the Poor layout can cause some of the common-mode signals to be
reference terminal, REF, is at one end of a 5 kΩ resistor. converted to differential signals before reaching the in-amp.
Additional impedance at the REF terminal adds to this 5 kΩ Such conversions occur when one input path has a frequency
resistor and results in amplification of the signal connected to response that is different from the other. To keep CMRR over
the positive input. The amplification from the additional RREF frequency high, the input source impedance and capacitance of
can be calculated as follows: each path should be closely matched. Additional source resistance
2(5 kΩ + RREF)/(10 kΩ + RREF) in the input path (for example, for input protection) should be
Only the positive signal path is amplified; the negative path placed close to the in-amp inputs, which minimizes their
is unaffected. This uneven amplification degrades CMRR. interaction with parasitic capacitance from the PCB traces.
INCORRECT CORRECT Parasitic capacitance at the gain setting pins can also affect CMRR
over frequency. If the board design has a component at the gain
setting pins (for example, a switch or jumper), the component
AD8229 AD8229 should be chosen so that the parasitic capacitance is as small as
REF
V
REF possible.
V Power Supplies
+
A stable dc voltage should be used to power the instrumentation
OP1177 amplifier. Noise on the supply pins can adversely affect perfor-
09412-059

–
mance. See the PSRR performance curves in Figure 18 and
Figure 19 for more information.
Figure 57. Driving the Reference Pin
A 0.1 μF capacitor should be placed as close as possible to each
INPUT VOLTAGE RANGE supply pin. As shown in Figure 59, a 10 μF tantalum capacitor
Figure 11 through Figure 16 show the allowable common-mode can be used farther away from the part. In most cases, it can be
input voltage ranges for various output voltages and supply shared by other precision integrated circuits.
voltages. The 3-op-amp architecture of the AD8229 applies gain +VS

in the first stage before removing common-mode voltage with

the difference amplifier stage. Internal nodes between the first and 0.1µF 10µF
second stages (Node 1 and Node 2 in Figure 56) experience a
combination of a gained signal, a common-mode signal, and a +IN

diode drop. This combined signal can be limited by the voltage VOUT
RG AD8229
supplies even when the individual input and output signals are
LOAD
not limited. REF
–IN

LAYOUT
To ensure optimum performance of the AD8229 at the PCB 0.1µF 10µF
09412-061

level, care must be taken in the design of the board layout. The
–VS
pins of the AD8229 are arranged in a logical manner to aid in
Figure 59. Supply Decoupling, REF, and Output Referred to Local Ground
this task.
Reference Pin
–IN 1 8 +VS
The output voltage of the AD8229 is developed with respect to
RG 2 7 VOUT
the potential on the reference terminal. Care should be taken to
RG 3 6 REF
tie REF to the appropriate local ground.
+IN 4 5 –VS
AD8229
09412-060

TOP VIEW
(Not to Scale)

Figure 58. Pinout Diagram

Rev. B | Page 18 of 24
Data Sheet AD8229
INPUT BIAS CURRENT RETURN PATH place a small value resistor, such as a 33 Ω, between the diodes and
The input bias current of the AD8229 must have a return path to the AD8229.
ground. When using a floating source without a current return +VS
+VS
+VS
RPROTECT RPROTECT 33Ω
path, such as a thermocouple, a current return path should be I
+ +
created, as shown in Figure 60. VIN+ I VIN+
–VS
– –
AD8229 AD8229
INCORRECT CORRECT +VS
RPROTECT RPROTECT 33Ω
+VS +VS
+ +
VIN– –VS VIN– –VS
– – –VS

09412-066
SIMPLE METHOD LOW NOISE METHOD
AD8229 AD8229
Figure 61. Protection for Voltages Beyond the Rails
REF REF

Large Differential Input Voltage at High Gain

–VS –VS
If large differential voltages at high gain are expected, use an
external resistor in series with each input to limit current during
TRANSFORMER TRANSFORMER
overload conditions. The limiting resistor at each input can be
+VS +VS computed from

1  |V | −1V 
RPROTECT ≥  DIFF − RG 
2 I MAX 
AD8229 AD8229
REF REF Noise-sensitive applications may require a lower protection
resistance. Low leakage diode clamps, such as the BAV199, can be
10MΩ
used across the inputs to shunt current away from the AD8229
–VS –VS
inputs and therefore allow smaller protection resistor values.
THERMOCOUPLE THERMOCOUPLE
RPROTECT RPROTECT

+ I + I
+VS +VS
VDIFF VDIFF
AD8229 AD8229
C C – –

RPROTECT RPROTECT

09412-067
1 R
AD8229 fHIGH-PASS = 2πRC AD8229 SIMPLE METHOD LOW NOISE METHOD
C C
REF REF
Figure 62. Protection for Large Differential Voltages
R
IMAX
09412-062

–VS –VS
CAPACITIVELY COUPLED CAPACITIVELY COUPLED
Figure 60. Creating an Input Bias Current Return Path
INPUT PROTECTION
The inputs to the AD8229 should be kept within the ratings
stated in the Absolute Maximum Ratings section. If this cannot
be done, protection circuitry can be added in front of the AD8229
to limit the current into the inputs to a maximum current, IMAX.
Input Voltages Beyond the Rails
If voltages beyond the rails are expected, use an external resistor in
series with each input to limit current during overload conditions.
The limiting resistor at the input can be computed from
| VIN − VSUPPLY |
RPROTECT ≥
I MAX
Noise-sensitive applications may require a lower protection
resistance. Low leakage diode clamps, such as the BAV199, can be
used at the inputs to shunt current away from the AD8229 inputs
and therefore allow smaller protection resistor values. To ensure
current flows primarily through the external protection diodes,
Rev. B | Page 19 of 24
The maximum current into the AD8229 inputs, IMAX, depends
on both time and temperature. At room temperature, the part
can withstand a current of 10 mA for at least a day. This time is
cumulative over the life of the part. At 210°C, limit current to
2 mA for the same period. The part can withstand 5 mA at
210°C for an hour, cumulative over the life of the part.
RADIO FREQUENCY INTERFERENCE (RFI)
RF rectification is often a problem when amplifiers are used in
applications that have strong RF signals. The disturbance can
appear as a small dc offset voltage. High frequency signals can
be filtered with a low-pass RC network placed at the input of
the instrumentation amplifier, as shown in Figure 63. The filter
limits the input signal bandwidth, according to the following
relationship:
1
FilterFrequency DIFF =
2πR(2C D + C C )
1
FilterFrequency CM =
2πRC C
where CD ≥ 10 CC.
AD8229 Data Sheet
+VS
Source Resistance Noise
0.1µF 10µF Any sensor connected to the AD8229 has some output resistance.
CC
There may also be resistance placed in series with inputs for
1nF protection from either overvoltage or radio frequency interference.
R +IN
This combined resistance is labeled R1 and R2 in Figure 64. Any
4.02kΩ
CD VOUT resistor, no matter how well made, has a minimum level of noise.
10nF
RG AD8229
This noise is proportional to the square root of the resistor
R REF
–IN
value. At room temperature, the value is approximately equal
4.02kΩ
CC to 4 nV/√Hz × √(resistor value in kΩ).
1nF

0.1µF 10µF
For example, assuming that the combined sensor and protection
resistance on the positive input is 4 kΩ, and on the negative

09412-063
–VS input is 1 kΩ, the total noise from the input resistance is
Figure 63. RFI Suppression
( 4  4 ) 2  ( 4  1) 2 = 64  16 = 8.9 nV/ Hz
CD affects the difference signal, and CC affects the common-mode
signal. Values of R and CC should be chosen to minimize RFI. A Voltage Noise of the Instrumentation Amplifier
mismatch between R × CC at the positive input and R × CC at the
The voltage noise of the instrumentation amplifier is calculated
negative input degrades the CMRR of the AD8229. By using a
using three parameters: the part input noise, output noise, and
value of CD one magnitude larger than CC, the effect of the
the RG resistor noise. It is calculated as follows:
mismatch is reduced, and performance is improved.
Total Voltage Noise =
Resistors add noise; therefore, the resistor and capacitor values
chosen depend on the desired tradeoff between noise, input (Output Noise / G)2  ( Input Noise)2  (Noise of RG Resistor )2
impedance at high frequencies, and RFI immunity. The resistors
For example, for a gain of 100, the gain resistor is 60.4 Ω. Therefore,
used for the RFI filter can be the same as those used for input
the voltage noise of the in-amp is
protection.
CALCULATING THE NOISE OF THE INPUT STAGE (45 / 100) 2  12  (4  0.0604 ) 2 = 1.5 nV/√Hz
The total noise of the amplifier front end depends on much
more than the 1 nV/√Hz headline specification of this data Current Noise of the Instrumentation Amplifier
sheet. There are three main contributors: the source resistance, Current noise is calculated by multiplying the source resistance
the voltage noise of the instrumentation amplifier, and the by the current noise.
current noise of the instrumentation amplifier. For example, if the R1 source resistance in Figure 64 is 4 kΩ,
In the following calculations, noise is referred to the input and the R2 source resistance is 1 k Ω, the total effect from the
(RTI). In other words, everything is calculated as if it appeared current noise is calculated as follows:
at the amplifier input. To calculate the noise referred to the
((4  1.5)2  (1  1.5)2 ) = 6.2 nV/√Hz
amplifier output (RTO), simply multiple the RTI noise by the
gain of the instrumentation amplifier.
SENSOR
Total Noise Density Calculation
To determine the total noise of the in-amp, referred to input,
combine the source resistance noise, voltage noise, and current
noise contribution by the sum of squares method.
R1 RG AD8229
For example, if the R1 source resistance in Figure 64 is 4 kΩ, the
R2 source resistance is 1 k Ω, and the gain of the in-amps is 100,
09412-064

R2 the total noise, referred to input, is

Figure 64. AD8229 with Source Resistance from Sensor and
Protection Resistors 8.9 2  1.52  6.2 2 ) = 11.0 nV/√Hz

Rev. B | Page 20 of 24
Data Sheet AD8229

OUTLINE DIMENSIONS
0.528
0.520
0.512

8 5
0.298
0.290 0.320
0.282 0.310
0.300
1 4

INDEX 0.305 0.125

MARK
0.300 0.110
0.295 0.095

0.011
0.010
0.105 0.009
0.095 0.130 NOM
0.085

0.045
0.035 0.011
SEATING
PLANE 0.054 0.025 0.010
NOM 0.310 0.009
0.175 NOM 0.020 0.300
0.105
0.018 0.290
0.100
0.016

07-08-2010-B
0.095 0.032
NOM

Figure 65. 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]

(D-8-1)
Dimensions shown in inches

5.00 (0.1968)
4.80 (0.1890)

8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4

1.27 (0.0500) 0.50 (0.0196)

BSC 45°
1.75 (0.0688) 0.25 (0.0099)
0.25 (0.0098) 1.35 (0.0532)
8°
0.10 (0.0040) 0°
COPLANARITY 0.51 (0.0201)
0.10 1.27 (0.0500)
0.31 (0.0122) 0.25 (0.0098)
SEATING 0.40 (0.0157)
PLANE 0.17 (0.0067)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
012407-A

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 66. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD8229HDZ −40°C to +210°C 8-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-8-1
AD8229HRZ −40°C to +175°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8229HRZ-R7 −40°C to +175°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
1
Z = RoHS Compliant Part.

Rev. B | Page 21 of 24
AD8229 Data Sheet

NOTES

Rev. B | Page 22 of 24
Data Sheet AD8229

NOTES

Rev. B | Page 23 of 24
AD8229 Data Sheet

NOTES

©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D09412-0-2/12(B)

Rev. B | Page 24 of 24