MOSFET: Variations and

Design for Manufacturing

Dr. Rajan Pandey
Associate Professor, SENSE
 TRADE-OFF BETWEEN Ion AND Ioff AND DESIGN
FOR MANUFACTURING

• Sub-threshold Ioff would not be a problem if Vt is set at a very high value.

• That is not acceptable because a high Vt would reduce Ion and therefore
reduce circuit speed.

• Using a larger Vdd can raise Ion, but that is not acceptable either because it
would raise the power consumption, which is already too large for comfort.

• Decreasing L can raise Ion but would also reduce Vt and raise Ioff.
 Variations and Design for Manufacturing

NMOS PMOS

Intel, T. Ghani et al., IEDM 2003

• Higher Ion goes hand-in-hand with larger Ioff (think L, Vt, Tox, Vdd).
• Figure shows spread in Ion (and Ioff) produced by intentional
difference in Lg and unintentional manufacturing variations in Lg
and other parameters.
 Variation Tolerant Circuit Design
In a large circuit such as a microprocessor, only some circuit blocks need to operate at
high speed at a given time and other circuit blocks operate at lower speed or are idle.

• Multiple Vt
• Lower Vt is used only in the blocks that need speed.
• Multiple Vdd
• Higher Vdd is used only in the blocks that need speed.
• Substrate (well) bias
• Only some circuit blocks need to operate at high speed.
• Can use reverse well bias to raise the Vt for the rest.
• This techniques can also reduce the chip-to-chip and
block-to-block variations with intelligent control circuitry.
• Would like larger body effect than conventional MOSFET.
 Variation Tolerant Circuit Design
• A major cause of the device variations is the imperfect control of Lg in the lithography process.
Some of the variation is more or less random variation in nature. The other part is more or less
predictable, called systematic variation.

• One example of the systematic variations is the distortion in photolithography due to the
interference of neighboring patterns of light and darkness.

• Elaborate mathematical optical proximity correction (OPC) reshapes each pattern in the photo-
mask to compensate for the effect of the neighboring patterns.

• An example of random variation is the gate edge roughness or waviness caused by the graininess
of the photoresist and the poly-crystalline Si.

• Yet another example of random variation is the random dopant fluctuation phenomenon. The
statistical variation of the number of dopant atoms and their location in small size MOSFET creates
significant variations in the threshold voltage.

• Metal Grain Granularity (MGG) in the work function metal and resulting variation in Vt.
 Ultra-Thin-Body SOI and Multi-gate MOSFETs
• There are alternative MOSFET structures that are less susceptible to Vt roll-off and allow gate length
scaling beyond the limit of conventional MOSFET.
• We want to maximize the gate-to-channel capacitance and minimize the drain-to-channel capacitance.
To do the former, we reduce Tox as much as possible. To accomplish the latter, we reduce Wdep and Xj
as much as possible.
• Reducing Tox gives the gate excellent control of Si surface potential.
• But, the drain could still have more control than the gate along sub-surface leakage
current paths. (Right figure.)
Vgs Vgs
Description of the
competition between the
gate and the drain over the Vds Vds
Tox Cg
control of the channel D
S D S Cd
barrier height Cg
Cd

P-Sub leakage path

There are two transistor structures that can eliminate the leakage paths that are far away from the
gate. One is called the ultra-thin-body MOSFET or UTB MOSFET. The other is multi-gate MOSFET.
 Ultra-Thin-Body MOSFET and SOI
Electron Micrograph of UTB MOSFET
• UTB MOSFET built on ultra thin
silicon film on an insulator (SiO2).
Gate
• Since the silicon film is very thin
(< 10nm), no leakage path is
Gate
very far from the gate. N+ N+
Gate
SiO2 Source Drain
Drain SiO2 Si TSi = 3 nm
Cross-Section of SOI Circuits

• In order to benefit from the UTB concept, Si film

thickness must be aggressively reduced to ~ Lg/4.
• Due to the high cost of SOI wafers, only some
microprocessors, which command high prices and
Si compete on speed, have embraced this technology.
Buried Oxide
Si substrate
 Ultra-Thin-Body MOSFET
• The sub-threshold leakage is reduced as the silicon film is made thinner.
Tox=1.5nm, Nsub=1e15cm-3, • The body effect that is
Vdd=1V, Vgs= 0 detrimental to circuit
speed is eliminated
because the body is
fully depleted and
floating and has no
fixed voltage.
• One challenge posed
by UTB MOSFETs is the
large source/drain
resistance due to their
thinness.
• The solution is to
thicken the source and
drain with epitaxial
Use of an ultrathin-body structure - a thin Si film on an insulator (SiO2) eliminates
deposition – The so
the submerged leakage paths. Since the Si film is very thin (< 10 nm), no leakage
called raised source
path is very far from the gate.
and drain.
Producing Silicon-on-Insulator (SOI) Substrates

• Initial Silicon wafer A and B.

• Oxidize wafer A to grow SiO2.
• Implant hydrogen into wafer A.
• Place wafer A, upside down, over
wafer B.
• A low temperature annealing
causes the two wafers to fuse
together.
• Apply another annealing step to
form H2 bubbles and split wafer A.
• Polish the surface and the SOI
wafer is ready for use.
• Wafer A can be reused.
 Multi-gate MOSFET and FinFET
• The second way of eliminating deep leakage paths is to provide gate control from more than one side of
the channel.
• The Si film is very thin so that no leakage path is far from one of the gates.

Gate 1 Vg
Because there may be more
than one gate, the structure may Source Si Drain TSi double-gate MOSFET
be called multi-gate MOSFET.
Tox Gate 2

• Shrinking TSi automatically reduces Wdep and Xj and Vt roll-off can be suppressed to allow Lg to shrink to
as small as a few nm.
• Because the top and bottom gates are at the same voltage and the Si film is fully depleted.
• There is no need for heavy doping in the channel to reduce Wdep. This leads to low vertical field and less
impurity scattering; as a result the mobility is higher.
• There are two channels (top & bottom) to conduct the transistor current. For these reasons, a multi-gate
MOSFET can have shorter Lg, lower Ioff, and larger Ion than a single-gate MOSFET.
• How to fabricate the multi-gate MOSFET structure?
 FinFET
• One multi-gate structure, called FinFET, is particularly
attractive for its simplicity of fabrication.
• The channel consists of the two vertical surfaces and the top
surface of the fin.
• Question: What is the channel width, W?
Answer: The sum of twice the fin height and the width of the fin.

• The process starts with an SOI wafer or a bulk Si wafer.

• A thin fin of Si is created by lithography and etching.
• Gate oxide is grown over the exposed surfaces of the fin.
• Poly-Si gate material is deposited over the fin and the
gate is patterned by lithography and etching.
• Finally, source/drain implantation is performed. SOI FinFET Bulk FinFET
 Variations of FinFET
G

Lg G G
S S
S
D
D
D
Tsi
u ri ed Oxide
B
Tall FinFET Short Nanowire
FinFET FinFET

• Tall FinFET has the advantage of providing a large W and therefore

large Ion while occupying a small footprint.
• Short FinFET has the advantage of less challenging lithography and
etching. also known as a triple-gate MOSFET.
• Nanowire FinFET gives the gate even more control over the silicon
wire by surrounding it.
I-V of a Nanowire “Multi-Gate” MOSFET
 Output Conductance
Output conductance limits the
What Parameters Determine the gds ? transistor voltage gain. Its cause
dI ds at dI ds at dVt and theory are intimately related
g ds   
dVds dVt dVds to those of Vt roll-off.
dI ds at  dI ds at dVt
  g msat and  e L / l d
dVt dVgs dVds
 L / ld
Idsat is a function of Vgs-Vt ( Vt  Vt long  Vds  e )

g ds  g msat  e L / l d
g msat
Max voltage gain (R   )   eL / ld
g ds
• A larger L or smaller ld , i.e. smaller Tox, Wdep, Xj, can
increase the maximum voltage gain.
• gds needs to be minimized for high voltage gain.
• The cause is “Vt dependence on Vds”in short channel transistors.
 Output Conductance

• The output conductance is caused by the drain/channel capacitive coupling, the

same mechanism that is responsible for Vt roll-off.

• This is why gds is larger in a MOSFET with shorter L.

• To reduce gds or to increase the intrinsic voltage gain, we can use a large L and/or
reduce ld.

• Circuit designers routinely use much larger L than the minimum value allowed
for a given technology node when the circuits require large voltage gains.

• Reducing ld is the job of device designer. Every design change that improves the
suppression of Vt roll-off also suppresses gds and improves the voltage gain.
 Channel Length Modulation
• For large L and Vds close to Vdsat, another mechanism may
dominate gds. That is channel length modulation.

• A voltage, Vds-Vdsat, is dissipated over a short distance next to

drain, causing the “channel length” to decrease with increasing
Vds. Ids, which is inversely proportional to L, thus increases
without true saturation.
Vd>Vdsat
ld  I ds at
g ds 
LVds  Vdsat 
ΔL

ld  3 ToxWdep X j Vc=Vdsat
 2D Devices (MOSFETs) Device Design: 3D Devices (FinFETs)
L Top view L
Device 3
Device 1 Device 2
L L L
S D
W2 G
G
W1
S pitch
D W 2W W
L
Device 2
Device 1
2 Fins
4 Fins 4 Fins
Fin
PC
Rx

n+ n+

Cross view
Fin Facts
W1 = 8nm, 5nm
down from Fin top Epi
8 nm
W2 = 14nm, 2nm
up from Fin bottom
41.5 nm
h = 41.5 nm
Lgate = 30 nm 14LP 14 nm
Effective channel Fin
Length = 14nm

5nm and beyond:

Nano-sheets

Nano-sheets
 Device and Process Simulation
• Device Simulation
– Commercially available computer simulation tools can solve all
the equations simultaneously with few or no approximations.
– Device simulation provides quick feedback about device design
before long and expensive fabrication.
• Process Simulation
– Inputs to process simulation: lithography mask pattern,
implantation dose and energy, temperatures and times for
oxidization and annealing steps, etc.
– The process simulator generates a 2-D or 3-D structures with all
the deposited or grown and etched thin films and doped regions.
– This output may be fed into a device simulator as input together
with applied voltages.
 Example of Process Simulation
• FinFET Process

The small figures only show 1/4 of the

complete FinFET--the quarter farthest from
the viewer.
Manual, Taurus Process, Synoposys Inc.
Example of Device Simulation---
Density of Inversion Charge in the Cross-Section of a FinFET Body

C.-H. Lin et al., 2005 SRC TECHCON

Tall FinFET Short FinFET

• The inversion layer has a significant thickness (Tch).

• There are more sub-threshold inversion electrons at the corners.
 MOSFET Compact Modeling for Circuit Simulation

• For circuit simulation, MOSFETs are modeled with analytical equations.

• Device model is the link between technology/manufacturing and
design/product. The other link is design rules.
• Circuits are designed (A) through circuit simulations or (B) using cell
libraries that have been carefully designed beforehand using circuit
simulations.
• BSIM is the first industry standard MOSFET model.
 MOSFET Compact Modeling for Circuit Simulation
• Circuit designers can simulate the operation of circuits containing up to hundreds of thousands or
even more MOSFETs accurately, efficiently, and robustly. Accuracy must be delivered for DC as well
as RF operations, analog as well digital circuits, memory as well as processor ICs.
• In circuit simulations, MOSFETs are modeled with analytical equations. These models are called
compact models to highlight their computational efficiency in contrast with the device simulators.
• It could be said that the compact model (and the layout design rules) is the link between two
halves of the semiconductor industry—technology/manufacturing on the one side and
design/product on the other.
• A compact model must capture all the subtle behaviors of the MOSFET over wide ranges of
voltage, L, W, and temperature and present them to the circuit designers in the form of equations.
• Some circuit-design methodologies, such as analog circuit design, use circuit simulations directly.
Other design methodologies use cell libraries.
• A cell library is a collection of hundreds of small building blocks of circuits that have been carefully
designed and characterized beforehand using circuit simulations.
• Finally, a good compact model should provide fast simulation times by using simple model
equations. In addition to the IV of N-channel and P-channel transistors, the model also includes
capacitance models, gate dielectric leakage current model, and source and drain junction diode
model. Noise and high-frequency models are usually provided, too.
Examples of BSIM Model Results
Example of BSIM Model Results

A compact model needs

to accurately model the
transistor behaviors for
any L and W that circuit
designers may specify.
MOSFET SPICE Models and their Parameters

(SPICE – Simulation Program with Integrated

Circuit Emphasis)

Study material with thanks from: Prof. V. N. Ramakrishnan

 Outline
• Level-1 model
• Level-2 model
• Level-3 model
• Level-4 model ( excluded in the syllabus)
BSIM (Berkeley Short-channel Igfet Model)
• References
 Level-1 model
• A first order model suitable for long channel devices
• Level 1 model is often referred to as the Shichman-Hodges
model
• Simplest of four MOSFET models
• DC Model
• Capacitance Model
– Strong inversion region
– Linear region
– Saturation region
– Weak inversion region
SPICELevel-1: Device Parameters
SPICE Level-1 Model Parameters
SPICE Level-1 Model Parameters
 Level-1: DC Model
• Threshold voltage Vth for the spice model-1 is given by

• No short channel or narrow width effects are considered

• The saturation voltage Vdsat is given by

• The drain current can be calculated using

 Level-1 : Capacitance Model
• The model parameters are
– Source/drain junction capacitances
– Overlap capacitances
– Intrinsic MOSFET capacitance (Gate oxide capacitance)
• Three intrinsic capacitances ( CGS, CGD, CGB)
– Junction capacitances are the sum of both the bottom wall (area)
capacitance and side-wall (periphery) capacitance
 Level-1 : Capacitance Model
• The source diode capacitance (CBS) is given by

• As and Ps are area and periphery of source-to-bulk pn-junction

respectively
• Cj0 and Cjsw0 are the junction capacitance per unit area and per
unit periphery, respectively, at zero back bias
• Similar equation holds for the drain-to-bulk junction capacitance
CBD
 Level-1: Capacitance Model
• Strong inversion region : Vgs > Vth
• Linear region: Vth > (Vgs + Vds)

• Saturation region: Vth < Vgs < (Vth + Vds)

 Level-1: Capacitance Model
• Weak inversion region: Vgs < Vth
 Level-1: Capacitance Model
• The overlap capacitances CGSO , CGDO and CGBO are then added
to CGS, CGD and CGB, respectively, in different regions of device
operation and are calculated from the following equations
 Level-2 Model
• Includes various second order effects present in small
geometry devices
• Model Parameters
 Level-2 : DC Model
• The Vth equation is

where Fl is short channel factor and Fw is narrow width factor

 Level-2 : DC Model
• Linear region current is given by
 Level-2 : DC Model
• Saturation voltage can be calculated in 2 ways
– If the maximum carrier drift velocity Vmax is assumed zero, then Vdsat
is calculated using a pinch-off model
 Level-2 : DC Model
• Second method is using the velocity saturation model
 Level-2 : Capacitance model
• MOSFET source and drain junction capacitance models are the
same as for Level-1
• MOSFET intrinsic capacitances - there are two models available
-first model, which is also the default model,
is the Meyer model as described for Level 1; the only
difference being that Vth is replaced by Von
- The second model is the charge controlled model of Ward
and Dutton
 Level-3 Model
• A semi-empirical model that includes most of the second order
effects described in the Level-2 model
• DC Model

• Saturation voltage
 Level-3 Model
• Linear region current
 Level-3 Model
• Saturation region current