Introduction to CMOS RF Integrated Circuits Design

II. RFIC System Overview

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-1
Outline

 Introduction
 RF Transceiver Architectures
 RF System Considerations
 Sensitivity and Selectivity
 Noise Figure
 Dynamic Range
 1-dB CP and IP3

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-2
RFIC is Analog Circuit

 KCL
 KVL
 Ohm’s Law
 Current Source
 Voltage Source
 R
 L
 C
 Wire
 Transistors

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-3
Inductors

1

LC

Unit-length
L > L1 > L2 > L3 > L 4 > L5 > Lo
f < f1 <f2 < f3 < f4 < f5 < fo

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-4
Capacitors

w
A wh
h C  
d d

Unit length
d

C > C1 > C2 > C3 > Co

f < f1 < f2 < f3 < fo

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-5
Challenges in RF IC Design

 RF IC Designs = Device Models + Simulators +

Experience

 RF IC Designer =
Analogue circuit designer (Simulation) +
Component maker (layouts) +System designer

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-6
RFIC Development Flow

Target System Spec

High-cost design:
Device Model
•Manpower
RF System Design
•EDA tool
•Measurement systems
System partitioning & sub-block sepcs •Test chips (3~5 rounds)

Circuit Design
RF Library

Layout Design
and DRC / LVS, parasitic extraction
18~24 Months

Design Rule
(Wafer Process)

PCB Design On-wafer

for Evaluation (Assembly Process) measurement

Evaluation
NG
OK

Mass Production Transfer

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-7
General Design Considerations

le Un
ab ive
or t rsa
P l

Low Costs

er
M

pow
ul
ti-
fu

-
Low
nc
tio
ns
Miniaturization

From the customers’ point of view

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-8
Broad-knowledge Required

Device Physics Material Packaging

EMC/EMI Analog Circuit

Microwave Comm. Theory

Theory
Analog/RF IC
RF IC Design CAD Tools
Transceiver Designer
Architectures Distributed
Parameters
IC Design
Wireless Standard Semiconductor
Processes

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-9
Teamwork Required

Global Customer
Standard

Wireless System
Spec / Evaluation Digital Design
RF System/Circuit
Design
Packaging

RF Circuit Layout/Parasitic extraction

Device Model Design Rule /

CAD / Library

Foundry

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-10
Trade-Offs

Wide-band

Low-Noise Low-Power
Consumption

High-linearity Wide-dynamic High-frequency

range

Low-Voltage High-Gain

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-11
Outline

 Introduction
 RF Transceiver Architectures
 RF System Considerations
 Sensitivity and Selectivity
 Noise Figure
 Dynamic Range
 1-dB CP and IP3

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-12
Multi-Mode Wireless

Future receivers need “Co-exist” with transmitters of different standards.

(i.e. simultaneous operation SoC/SiP)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-13
(Super-) Heterodyne Receiver

Out-of-band rejection

BPF1
LO1
Image problem
(1st down-conversion)
BPF2

BPF3
1st channel selection
(2nd down-conversion)

2nd channel selection

BPF4
Introduction to CMOS RF Integrated Circuits Design
*Razavi
Fall 2012, Prof. JianJun Zhou II-14
Out-of-band Interference Rejection (Band Selection)

Out-of-band In-band Out-of-band

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-15
Image Problem in Heterodyne System

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-16
Image Rejection by Filter

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-17
Channel Selection Filter

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-18
Image Rejection and Channel Selection

High Q Filter

High Q Filter

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-19
In-band Interference (1)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-20
In-band Interference (2)

Near-Far Problem Comes from Wandering into Adjacent Cells

Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-21
In-band Interference (3)

How does Non-linear Amplifier (IMD3) affect the signal?

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-22
Receiver : Heterodyne

 Advantages
 (High Selectivity) Relaxation of linearity requirements due to the use of IF SAW BPF
 (High Sensitivity) Less DC-offset impairment, Easier I/Q match at lower frequencies
 Disadvantages
 Bulky off-chip RF/IF SAW BPFs
 A good frequency plan is essential
 Image problem
 “Half-IF” spurious response at lower IF frequencies
 Need at least two LO sources
 Integration level is low due to filter

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-23
Receiver : Direct-Conversion (Zero-IF)

 Advantages
 No Image or “half-IF” issues
 High level integration and lower cost (No IF filters)
 Disadvantages
 DC offset problems are extremely challenging (IM2/IP2)
 LO leakage re-radiation (LO pulling)
 1/f noise (CMOS) can substantially corrupt the D/C signal
 Even-order distortion of great concert
 More difficult I/Q match at RF frequencies
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-24
DC offset

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-25
Receiver : Low-IF

 Advantages
 Integration of channel filters is possible
 Less susceptible to 1/f noise and DC offsets (AC coupling)
 Low-frequency IM2 product can be easily blocked.
 Disadvantages
 Image is still a problem, which entails precise I/Q match
 Complex signal processing is essential to obtain necessary
selectivity
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-26
Receiver: Image Rejection Low-IF

 To achieve 30dB Image rejection

 IQ amplitude imbalance is less than 0.5dB
 IQ phase imbalance is less than 3.5 degree

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-27
Receiver: Image Rejection Low-IF (Digital)

 Advantages
 Digital signal process avoids the problem of I/Q mismatch\
 Less susceptible to process variations
 Disadvantages
 ADC performance is a great concern

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-28
Zero-IF Receiver Channel Selection

IP3

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-29
Transmitter : Heterodyne

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-30
Transmitter: Direct Conversion

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-31
No interference

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-32
With Interference (LO Pulling)

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-33
Indirect VCO Frequency (Sub-harmonic LO)

- Or using sub-harmonic modulator or mixer

Introduction to CMOS RF Integrated Circuits Design

*APMC2006
Fall 2012, Prof. JianJun Zhou II-34
Duplexer Freq. Response

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-35
PA Leakage to Rx

935-960 MHz

Rx

Tx

TDD TRx

890-915 MHz, FDD TRx

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-36
Desensitization Through Compression

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-37
TRx Architecture Selection

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-38
Outline

 Introduction
 RF Transceiver Architectures
 RF System Considerations
 Sensitivity and Selectivity
 Noise Figure
 Dynamic Range
 1-dB CP and IP3

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-39
System Considerations

Spurious
Sensitivity
Rejection
Selectivity Dynamic Range

IM Rejection Frequency EMI

stability Linearity

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-40
Sensitivity

 RF Receiver sensitivity: quantifies the ability

to respond to a weak signal.
 Defined as the minimum detectable signal
power level, satisfying the requirement of the
specified signal-to-noise ratio (SNR) for an
analog receiver and bit-error-rate (BER) for a
digital receiver.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-41
dBm

dBm  10 log (mW)=10log(W)  30dB

Boltzmann constant k = 1.3806503 × 10-23 JK-1

Room temp=300K

kT  1.38  10 23  300W/Hz=  173.83dBm / Hz

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-42
Equations

Noise Floor  Pnf (dBm)  kTB (dBm)  Freceiver (dB)

Sensitvity  Pin,min (dBm)  kTB(dBm)  Freceiver (dB)  SNRmin (dB)

 174dBm / Hz  10logB  Freceiver  SNRmin

Desired Signal

Receiver Added Noise

Receiver Thermal Noise

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-43
Selectivity

The ability to reject unwanted signals on adjacent

channels (channel selectivity) and/or the outside of the
wanted band (band selectivity). 70 to 90 dB rejections are
normally required

Wanted
Desired RF Channel
band

f
Desired RF Band

Band selectivity Channel selectivity

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-44
Spurs and Intermodulation

Spurious Response Rejection

The ability to reject undesired channels to reduce the
interference. Rejection of 70dB to 100 dB is usually
required for wireless communications;

Intermodulation (IM) Rejection

The receiver has the tendency to generate its own on-channel
interference from one or more RF signals due to the
nonlinearity of the receiver. These interference signals are
called IM products. Greater than 70 dB rejection is
desirable
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-45
Others

Frequency Stability
Stable frequency operation is important in order to capture the
desired frequency channel. PLL/synthesizers are
commonly employed to obtain an accurately controlled LO
frequency.

EMI: Electromagnetic Interference

From one part to another part within an RF front-end receiver or

from interconnects as well as the silicon substrates

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-46
Noise Figure
 Signal-to-noise ratio (SNR): ratio of the signal power to
the total noise power

wanted signal power

SNR 
unwanted noise power
 Noise figure is a figure of merit quantitatively specifying
how noisy a system/component is. The noise factor F is
defined for the two-port network:
SNR |in put Si / N i
F 
SNR |out put So / N o

NF=10log(F) (dB)
Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-47
Noise Figure—cont.

Si F So
G
Nn
Ni No

Two-port system with power gain G, added noise

power Nn and the noise factor F

So  GSi N o  GN i  N n (W)
Si / N i No Nn
F   1 N o  FGN i
GSi / N o GN i GN i

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-48
Cascaded Noise Figure

F1 F2 F3 Fm
Si G1 G2 G3 Gm
So
Nn1 Nn2 Nn3 Nnm
Ni
No

m systems in cascade NF contribution

Friis equation:
F2  1 F3  1 Fm  1
Ftotal  F1    
G1 G1G2 G1G2G3  Gm 1

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-49
Dynamic Range

Pin  Pout  G (dB)

 For an RF system, operation is normally in a region
where the output power is linearly proportional to the
input power, while the coefficient is the desired power
gain. This region is called as the dynamic range (DR).
 DR is the rang between the maximum power level that
the system is still in linear region to the minimum
detectable signal (MDS) power level
 The range could be specified in terms of input power or output
power.
 Higher DR is desirable

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-50
Nonlinear Effects

It is desired that no matter how high the input signal power is,
the output power will be the linearly amplified input signal.
Nonlinearities often exist in practical systems and lead to interesting
phenomena, those phenomena limit the linear operating range of a
system. For simplicity, the output – input relationship can be
approximately modelled as (Taylor Series expansion):

y(t)  ao  a1x(t)  a2x (t)  a3x (t) 2 3

y(t) is the output and x(t) is the input signal. ao is the DC component,
a1 the gain, a2 and a3 (less than zero) the coefficients of the second
and third-order nonlinear terms.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-51
1-dB Compression Point

Pin,1-dB = Pout,1-dB –G +1 dB DR = Pin,1dB – MDS (dB)

Linear relationship
1 dB
(dB)
out
P

DR

- dB
-1
Noise MDS P in (dB) P in,1dB
Floor

Gain-compression of a realistic RF system

Introduction to CMOS RF Integrated Circuits Design
Fall 2012, Prof. JianJun Zhou II-52
1-dB Compression Point: Equations
y(t)  ao  a1( Ao cosot  A1 cos1t  A2 cos2t)
 a2 ( Ao cosot  A1 cos1t  A2 cos2t)2
 a3( Ao cosot  A1 cos1t  A2 cos2t)3

Fundamental components:
3A02 3 2 2
{a1  a3[  ( A1  A2 )]}A0 cos0t 
4 2
3A12 3 2 2
{a1  a3[  ( A0  A2 )]}A1 cos1t 
4 2
3A22 3 2 2
{a1  a3[  ( A1  A0 )]}A2 cos2t
4 2

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-53
1-dB CP

If 0 is the desired signal then the gain will be , a decreasing gain

because of a3<0. If the unwanted signal strengths A1 and A2
are so strong, the gain of the wanted signal drops to 1 or
lower when:
2 a1  1 1 2
A A 
1
2 2
2  A0
3 | a3 | 2
Now the wanted signal is “blocked” by the unwanted strong
signal, because the wanted signal cannot be amplified by the
RF section. Many RF sections in wireless applications must be
able to withstand blocking signals 60 to 70 dB stronger than
the wanted signal

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-54
1dB CP vs a3

The 1-dB compression point can be obtained from three-tone for the
wanted channel as (assuming 3 input tones are at the same power):
15 3
20 log(a1 A1 dB )  20 log(a1 A1 dB  | a3 | A1 dB )  1 (dB)
4
Or
a1 a1
| a3 | 0.029 2 or A1 dB  0.029
A1 dB | a3 |

Thus, from the measured linear gain a1 and the input level at the 1-
dB compression point, one can calculate the nonlinear coefficient
|a3|

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-55
Intermodulation

Intermodulation or intermodulation distortion

(IMD), or intermod for short, is the result of two or
more signals of different frequencies being mixed
together, forming additional signals at
frequencies that are not, in general, at harmonic
frequencies (integer multiples) of either.

Intermodulation should not be confused with

general harmonic distortion. Intermodulation
specifically creates non-harmonic tones ("off-
key" notes, in the audio case) due to unwanted
mixing of closely spaced frequencies.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-56
IMD in a 3-Tone Case

IM
Desired
Channel

RF  
Section

0- 0 0+ 0- 0 0+

Adjacent
Channels

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-57
Intermodulation Equations for 3-Tone Case

| a3 | 3 A02 3 2
y (t )  {1  [  ( A1  A22  A1 A2 )]}a1 A0 cos  0t 
a1 4 2
A2
3( A02  A12 )
| a3 | A1 3 2
{1  [  ( A0  A22 )]}a1 A1 cos( 0   )t 
a1 4 2
A1
3( A02  A22 )
| a3 | A2 3
 {1  [  ( A02  A12 )]}a1 A2 cos( 0   )t 
a1 4 2
3 A0 1 2 1 2
 a3 {[ A1  A1 A2 ] cos( 0  2  )t  [ A2  A1 A2 ] cos( 0  2  )t} 
2 2 2
3
 a3 A1 A2 { A1 cos( 0  3 )t  A2 cos( 0  3 )t}  others
4

There are IM effects between any two channels

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-58
Intermodulation Examples

100

90
One channel
Output Signal Magnitude 80

70
Two-tone

60

50

40

30
Three-tone

20

10

0
0 5 10 15 20 25
Input Signal Magnitude A in

The output signal vs. the input signal amplitude for the three-tone
and the two-tone tests, respectively

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-59
Intercept Point (IP)

The intercept point is obtained graphically by plotting the

output power versus the input power both on logarithmic
scales (e.g., dB). Two curves are drawn; one for the linearly
amplified signal at an input tone frequency, one for a nonlinear
product. On a logarithmic scale, the function xn translates into
a straight line with slope of n. Therefore, the linearly amplified
signal will exhibit a slope of 1. A third-order nonlinear product
will increase by 3 dB in power when the input power is raised
by 1 dB.

The intercept point is a purely mathematical concept, and

does not correspond to a practically occurring physical power
level. In many cases, it lies beyond the damage threshold of
the device.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-60
IP3 Plots

100
IM of three-tone

IP3
IP3
20log(Output)

50 20log(a A)
1

0
IM of two-tone

-50 20log(A)
0 5 10 15 20 25 30 35 40 45

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-61
Nonlinear Effects of Cascaded RF Systems

P11dB P12dB
X(t) y2(t)
G1 G2
••••

P11dB and IP31

1 1 G1 G1G2
   
PIP3 PIP3,1 PIP3,2 PIP3,3
1 1 G GG GG G
  1  1 2  1 2 3 
P1dB P1dB,1 P1dB,2 P1dB,3 P1dB,4
N 1 N 1
1 1
PIP 3 |dBm  PIP 3, N |dBm   Gi |dBm  10 log[1  PIP 3, N  N i
]
G
i 1 i 1 PIP 3,i
j
j 1

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-62
Trade-off between NF & IP3

Higher gains lower NF lower IP3

1 1 G GG GG G
  1  1 2  1 2 3 
P1dB P1dB ,1 P1dB , 2 P1dB ,3 P1dB , 4
1 1 G GG
  1  1 2 
PIP 3 PIP 3,1 PIP 3, 2 PIP 3,3
N 1 N 1
1 1
PIP 3 |dBm  PIP 3, N |dBm   Gi |dBm  10 log[1  PIP 3, N  N i
]
G
i 1 i 1 PIP 3,i
j
j 1

F2  1 F3  1 Fm  1
Ftotal  F1    
G1 G1G2 G1G2G3  Gm 1

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-63
Spurious-Free Dynamic Range

IM of three-tone

IP3 IP3
20log(Output)

20log(a1A)
1:1 SFDR
slope

Noise-floor

3:1 slope
IM of two-tone

P F
Pin,max  IIP3
-60
3
-10
20log(A)

characterizes a receiver with more than one signal applied to the input

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-64
Spurious-Free Dynamic Range

Pout  PIM,out 2 PIIP 3  PIM,in

PIIP 3  Pin  Pin 
2 3
The maximum input level for which the IM products become
Equal to the noise floor:
PIIP 3  F
Pin,max  , F  174dBm  NF  10 log B
3
2 PIIP3  F 2( PIIP3  F )
SFDR   ( F  SNRmin )   SNRmin
3 3
E.g. if a receiver with NF=9dB, PIIP3=-15dBm, and B=200kHz
SNRmin=12dB, then, SFDR53dB.
The SFDR represents the maximum relative level of interferers
that a receiver can tolerate while producing an acceptable signal
quality from a small input level.

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-65
Total System IIP3

Transfer all input intercept points to system input, subtracting gains

and adding losses decibel for decibel
Convert intercept points to powers (dBm to mW). We have IP1,
IP2, …. IPN for N elements
Assuming all input intercepts points are independent and
uncorrelated, add powers in “parallel”:
Convert IIP3 from power (mW) to dBm.

1 1 1 1 1
IIP 3  (    ) (mW)
IP1 IP2 IP3 IPN

Introduction to CMOS RF Integrated Circuits Design

Fall 2012, Prof. JianJun Zhou II-66