Modeling and Suppression of Circulating Currents for
Multi-ParalleledThree-Level T-Type Inverters
Zicheng Zhang, Alian Chen, Xiangyang Xing, Ke Li, Chunshui Du, Chenghui Zhang
School of Control Science and Engineering
Shandong University
Jinan, P.R. China
Abstract—Paralleled inverters have the merits of high power
rating, improved reliability and convenient maintenance, but
zero-sequence circulating current (ZSCC) will occur and lead to
current distortion and system loss. The ZSCC control is more
complicated when adopting three-level topology and increasing
paralleled number. This paper addresses the suppression of
ZSCC in multi-paralleled three-level T-type inverters (3LT2Is). A
new equivalent model is developed by reorganizing the ZSCCs
into another form. The ZSCC controller based on the new model
is easier to implement. Therefore, the number of paralleled
inverters can be increased without complicating the control
scheme and the inverters could be switched on or off optionally.
Besides, feed-forward (FF) strategy is adopted to eliminate the
ZSCC spikes caused by symmetrical three-level space vector
modulation (SVM). The effectiveness of the proposed control
scheme is verified by both simulated and experimental results.
Keywords—paralleled inverters, zero-sequence circulating
current (ZSCC), T-type three-level inverters (3LT2Is), feed forward
˄FF˅, space vector modulation (SVM)
I. INTRODUCTION
Three-level inverters have been widely utilized in recent
years due to their merits of superior output voltage quality and
high power rating [1]-[6]. In particular, the topology of three-
level T-type inverter (3LT2I) has been proposed for low-
voltage application and it has the highest efficiency among the
two-level, T-type and neutral-point clamped (NPC) inverters
for the medium switching frequency (4-30kHz) [7].
The topology of paralleled inverters is commonly used in
high power applications driven by its high power rating,
improved efficiency and reliability. However, zero-sequence
circulating current (ZSCC) will be generated with different
hardware parameters or control effect. The ZSCC will lead to
the distortion of output current and the reduction of the system
efficiency. Consequently, the suppression of ZSCC has
become a focus recently [8]-[19].
The ZSCC problem will be lessened with sinusoidal pulse
width modulation (SPWM) but the modulation index is low
which limits the usage of the DC link voltage [8]. PI regulator
is commonly used in ZSCC suppression [9]-[10]. However,
the performance of PI regulator will degrade with unequal
reference currents or filter inductors [11]. Several improved
strategies such as deadbeat controller and PI regulator with
This work is supported by the National Natural Science Foundation of
China under Grant 51377101, and Grant 61527809, and Grant 61573223.
978-1-5090-2998-3/17/$31.00 ©2017 IEEE
feed-forward (FF) are proposed in [11]-[13]. Nevertheless, the
ZSCC controllers are not unified among paralleled inverters
and have to be executed in sequence. Therefore, these
methods will become complicated and spend more time as the
number of paralleled inverter increases. Moreover, ZSCC
spikes will be generated in three-level paralleled inverters with
the symmetrical space vector modulation (SVM) due to the
change of seven-segment sequence [14]-[15]. The deadbeat
controller is adopted in [14] to eliminate the ZSCC spikes but
only two-paralleled system is considered. Two open-loop
methods are proposed for multi-paralleled system which are
relatively easy to implement [15]-[16]. But these methods
have weak stability and low robustness without close-loop
control.
To solve the conflict between easy implementation and
accurate ZSCC suppression, this paper proposes a new kind of
equivalent model for multi-paralleled system that makes the
controller easier to design. For M-paralleled system (M ı 3),
the first inverter does not need to control ZSCC since there are
redundant control variable [11]. The rest (M-1) inverters have
the same ZSCC controller and could be switched on or off
optionally which makes the system more flexible. The ZSCC
spikes are eliminated by the FF control scheme. The
description is based on three-paralleled system for simplicity.
Three-level T-type inverters are adopted as the paralleled unit
in this paper.
II. NEW EQUIVALENT MODEL OF THREE-PARALLELED
INVERTER SYSTEM
The topologies of 3LT2Is and three-paralleled system are
shown in Fig. 1 and Fig. 2, respectively. The neutral point (NP)
of the DC-link is taken as the reference point.
P
VP ua
O ub
uc
VN
N
Fig. 1. Topology of T-type inverter.
708
 Assume that the NP potential is balanced to simplify the VL3 : NPN VM2 : OPN
II
VL2 : PPN
derivation, that means VP=VN. As shown in Fig. 2, the
mathematic models of each inverter are derived as:
III
ªiax º ªiax º ªuax − ea + uOn º VM3 : VS3 : OPO VS2 : PPO VM1 :
d
Lx ««ibx »» = − Rx ««ibx »» + «« ubx − eb + uOn »»
NPO NON OON PON
(1)
dt I
¬« icx ¼» ¬« icx ¼» ¬« ucx − ec + uOn ¼»
3
5 1
VL4 : V0 : P PP
VS4 : OPP OOO VS1 : POO VL1 :
where x=1,2,3, refers to xth inverter; Lx and Rx are the NPP NOO NNN
6
ONN
2
PNN

inductance and equivalent series resistance of the filter 4

inductors; uax, ubx, ucx are the output voltages of the inverters. IV
VM4 : VS5 : OOP VL6 : POP VM6 :
NOP NNO ONO PNO
ua1 ia1 L1 R1 iz1 ea
P
VI
O ub1 ib1 eb
Vdc n
uc1 ic1 ec
N 1st Inverter VL5 : NNP VM5 : ONP VL6 : PNP
V

ua2 ia2 L2 R2 iz2

Fig. 3. Space vector diagram of three-level inverter
ub2 ib2
uc2 ic2
The model of ZSCC is derived by summing up the three
2nd Inverter equations in (1):

ua3 ia3 L3 R3 iz3 dizx

Lx = − Rx izx + u zx − ez + 3uOn
ub3 ib3 dt
(4)
uc3 ic3 3
3rd Inverter = − Rxizx + Vdc mzx − ez + 3uOn
2
Fig. 2. Three-paralleled inverter system. where izx is the circulating current, izx= iax + ibx + icx; uzx is the
The space vector diagram of three-level inverter is shown zero sequence voltage, uzx= uax + ubx + ucx; ez is the sum of the
in Fig. 3. There are six large vectors, six medium vectors, three phase grid voltages, ez= ea + eb + ec.
twelve small vectors and three zero vectors divided based on To simplify the analysis, uOn in (4) is eliminated by
their magnitude. Symmetrical SVM is commonly used as the subtracting the ZSCC equation of the first inverter:
modulation method for three-level inverters [20]-[21]. This
modulation scheme can be easily implemented by carrier diz 2 di 3
L2 − L1 z1 = −( R2iz 2 − R1iz1 ) + Vdc (mz 2 − mz1 )
based PWM (CBPWM) with zero-sequence injection [22]. dt dt 2
(5)
Based on CBPWM, the output voltages are represented as: di di 3
L3 z 3 − L1 z1 = −( R3iz 3 − R1iz1 ) + Vdc (mz 3 − mz1 )
Vdc V ∗
dt dt 2
uax = max = dc (max + mzx )
2 2 The equations in (5) could be further simplified by the
V V ∗ following definition:
ubx = dc mbx = dc (mbx + mzx ) (2)
2 2 L1 L1
V V ∗
iz′ 2 = iz 2 − iz1 iz′ 3 = iz 3 − i z1
ucx = dc mcx = dc (mcx + mzx ) L2 L3
2 2 (6)
R2 R1 R R
* * *
where m ax, m bx, m cx are the sinusoidal reference modulation k2 = L1 ( − ) k3 = L1 ( 3 − 1 )
L2 L1 L3 L1
waveforms generated by the current controller; max, mbx, mcx
are the modified modulation waveforms for symmetrical SVM; According to the definition, equation (5) is rewritten as:
mzx is the zero sequence component.
diz′ 2 3
The expression of mzx is given as: L2 + R2iz′ 2 = Vdc (mz 2 − mz1 ) − k2iz1
dt 2
(7)
1 diz′ 3 3
∗
mzx = [1 − max(max ∗
+ kax , mbx ∗
+ kbx , mcx + kcx ) L3 + R3iz′ 3 = Vdc (mz 3 − mz1 ) − k3iz1
2 dt 2
∗ ∗ ∗
− min(max + kax , mbx + kbx , mcx + kcx )] (3) Equation (7) describes a new equivalent model form of
three-paralleled three-level inverter system. iƍz2, iƍz3 are the
­° 0 mlx∗ ≥0
klx = ® l = a , b, c reorganized states of the original ZSCC iz1, iz2, iz3. And it is
°̄ 1 mlx∗ <0 obvious that the coefficients k1, k2 are relatively small based

709
on their definition. The equivalent model will be used to It can be seen from Fig. 4 that the ZSCC control schemes
design the ZSCC controller in the next part. of inverter 2 and inverter 3 are decoupled with each other. In
theory, the inverter 2 and inverter 3 can be switched on or off
III. IMPROVED CONTROL SCHEME OF PARALLELED SYSTEM without impacting the operation of the system. More inverters
can be added conveniently which makes the paralleled system
It can be seen from Fig. 2 that the sum of iz1, iz2, iz3 is zero,
more flexible.
therefore, the original ZSCC iz1, iz2, iz3 will be well suppressed
when the reorganized states iƍz2, iƍz3 are controlled to zero. That
means the control of the original ZSCCs and reorganized IV. SIMULATED AND EXPERIMENTAL RESULTS
states are equivalent. To verify the proposed approach, experiments are
performed in a prototype of two-paralleled 3LT2Is. The
The distribution of redundant vectors does not affect the
parameters for the experiments are shown in Table I and Em,
output voltage but can impact the ZSCC therefore it can be
Im1, Im2, Im3 refer to peak values.
used to realize the object of ZSCC suppression. As for
CBPWM, it can be achieved by adding the same component to TABLE I EXPERIMENT PARAMETERS
the modulation wave. Then equation (7) is rewritten as:
DC Voltage Vdc 400V
diz′ 2 3
L2 + R2iz′ 2 = Vdc (mz 2 − mz1 + y z 2 − y z1 ) − k2iz1 Grid Voltage Em 200V
dt 2
(8) Inductor L1 5mH
diz′ 3 3
L3 + R3iz′ 3 = Vdc (mz 3 − mz1 + y z 3 − y z1 ) − k3iz1 Inductor L2 3mH
dt 2
Inductor L3 4mH
where yz1, yz2, yz3 are the control variables of the three
Current Im1, Im2, Im3 17/15/13A
inverters for ZSCC suppression.
Sample Time Ts 200ȝs
The control variable yz1 could be set to zero since there is
redundancy for ZSCC control. Neglect the fluctuation in DC Fig. 5 shows the experimental waveforms with equal
bus voltage, the Laplace transform of (8) can be obtained as: reference currents. The output phase currents are distorted
without ZSCC suppression. The performance of ZSCC
3Vdc ( M z 2 − M z1 + Yz 2 ) − 2k2 I z1
I z′ 2 = suppression with PI controller only is limited shown in Fig.
2 × ( sL2 + R2 ) 5(b). With the proposed method being employed, ZSCC is
(9)
3Vdc ( M z 3 − M z1 + Yz 3 ) − 2k3 I z1 well suppressed and the ZSCC spikes are eliminated.
I z′ 3 =
2 × ( sL3 + R3 )

where Iz1, Iƍz2, Iƍz3, Mz1, Mz2, Mz3, Yz2 and Yz3 are the Laplace ia1(10A/div)
form of iz1, iƍz2, iƍz3, mz1, mz2, mz3,yz2 and yz3.
The control scheme based on the proposed equivalent
Currents

model is described in Fig. 4. As mentioned above, the variable

k2 and k3 are relatively small and the control loop has effective iz2(5A/div)
ia2(10A/div)
damping characteristic to the disturbance according to the
control theory. Therefore, the impact of iz1 could be neglected.
Moreover, the feed forward strategy is introduced to the
controller to eliminate the ZSCC spikes.
Time(5ms/div)
(a)

ia1(10A/div)
Currents

iz2(5A/div)
ia2(10A/div)

ZSCC spike
Time(5ms/div)
(b)
Fig. 4. Control scheme of ZSCC suppression.

710
 Fig. 6 shows the waveforms with different reference
currents and Im1 =17, Im2 = 13A. This is a worse case and a
ia1(10A/div)
large ZSCC is generated. As shown in Fig. 6(a), the phase
currents of 3LT2Is are distorted seriously. The ZSCC can only
Currents be partly suppressed with the PI controller scheme. It can be
seen that the ZSCC spikes cannot be eliminated either. The
current quality becomes superior after implementing the
iz2(5A/div)
ia2(10A/div) proposed control scheme.
The dynamic response of the paralleled system is shown in
Fig. 7 (a) under the condition of Im1 =17, Im2 = 13A. At first,
Time(5ms/div) no ZSCC control algorithm is applied and there is large ZSCC.
(c) The current waveforms are also distorted. At 30ms, PI
Fig. 5. Experimental results with Im1 = Im2 = 15A. (a) Without ZSCC control. controller is adopted. It can be seen than the ZSCC is
(b) With PI regulator only. (c)With PI regulator and FF. suppressed to some extent and the waveforms of the phase
currents become better. However, the ZSCC spikes caused by
symmetrical space vector modulation cannot be eliminated. At
80ms, PI controller together with FF strategy is applied. The
ia1(10A/div) ZSCC spikes are eliminated and the current quality becomes
superior.
To verify the effectiveness of the NP balance control
Currents

together with the ZSCC control, the upper and lower capacitor
iz2(5A/div)
voltage VP, VN as well as the line to line voltages is given in
ia2(10A/div) Fig. 7(b).

ia1(10A/div)
Time(5ms/div)
(a)
Currents

ia1(10A/div)
iz2(5A/div)
ia2(10A/div)
Currents

PI only PI+FF
ia2(10A/div) iz2(5A/div) Time(10ms/div)
(a)

VP
ZSCC spike
VN
Time(5ms/div)
Voltage(200V/div)

(b) vab1

ia1(10A/div)

vab2
Currents

ia2(10A/div) iz2(5A/div) Time(5ms/div)

(b)
Fig. 7. Experimental results with Im1 =17, Im2 = 13A. (a) Dynamic response.
(b) Steady NP balance and line to line voltages.

Time(5ms/div) Fig. 8 shows the simulated results of three-paralleled

(c) system with Im1=17A, Im2=15A, and Im3=13A. The ZSCCs of
Fig. 6. Experimental results with Im1 =17, Im2 = 13A. (a) Without ZSCC the three inverters are well suppressed and the output currents
control. (b) With PI regulator only. (c)With PI regulator and FF. are improved after the proposed control scheme is applied.

711
 Experiments are conducted on a two-paralleled system and the
ia1 effectiveness of the control scheme is validated. Simulated
ia2 results indicate that ZSCC could also be well suppressed in a
three-paralleled system.

iz1 iz2 iz3 (10A/div)

ia1 ia2 ia3 (20A/div)

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