Advanced Digital Electronics Laboratory Exp.

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Experiment 1
Introduction to Xilinx ISE 9.2i Development Software Basics
Design Examples AND,OR and XOR logic gates
Learning Objectives:
1. learning for new users of the ISE software and for users who wish to refresh their knowledge
of the software.
2. To demonstrates basic set-up and design methods available in the PC version of the ISE
software.
3. By the end of the experiment, you will have a greater understanding of how to implement
your own design flow using the ISE 9.2i software.
Equipment and Materials:
full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
Introduction:
VHDL is a hardware description language. It describes the behavior of an electronic circuit
or system, from which the physical circuit or system can then be implemented.
VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for
Very High Speed Integrated Circuits. VHDL is intended for circuit synthesis as well as circuit
simulation. A fundamental motivation to use VHDL is that VHDL is a standard,
technology/vendor independent language, and is therefore portable and reusable. The two
main immediate applications of VHDL are in the field of Programmable Logic Devices
(including CPLDs—Complex Programmable Logic Devices and FPGAs—Field Programmable
Gate Arrays) and in the field of ASICs (Application Specific Integrated Circuits). Once the VHDL
code has been written, it can be used either to implement the circuit in a programmable
device (from Altera, Xilinx, Atmel, etc.) or can be submitted to a foundry for fabrication of an
ASIC chip. Currently, many complex commercial chips (microcontrollers, for example) are
designed using such an approach.
A final note regarding VHDL is that, contrary to regular computer programs which are
sequential, its statements are inherently concurrent (parallel). For that reason, VHDL is usually
referred to as a code rather than a program. In VHDL, only statements placed inside a
PROCESS, FUNCTION, or PROCEDURE are executed sequentially.
Procedures:
1- Starting the ISE Software

To start ISE, double-click the desktop icon, or start ISE from the Start menu by
selecting:
Start → All Programs → Xilinx ISE 9.2i → Project Navigator
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2- Create a New Project
To create a new project:
a. Select File > New Project... The New Project Wizard appears.
b. Type tutorial in the Project Name field.
c. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically.
d. Verify that HDL is selected from the Top-Level Source Type list.
e. Click Next to move to the device properties page.
f. Fill in the properties in the table as shown below:
♦ Product Category: General Purpose
♦ Family: Spartan3E
♦ Device: XC3S500E
♦ Package: FG320
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: VHDL
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:

g. Click Next to proceed to the Create New Source window in the New Project Wizard.
At the end of the next section, your new project will be complete.

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3- Creating a VHDL Source
To Create a VHDL source file for the project as follows:
a) Click the New Source button in the New Project Wizard.
b) Select VHDL Module as the source type.
c) Type in the file name.
d) Verify that the Add to project checkbox is selected as shown below.

e) Click Next.
f) Declare the ports for the counter design by filling in the port information as shown
below:

g) Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the
new source file template.
h) Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and
the (and_1) displays in the Source tab, as shown below:

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i) Enter the VHDL code after begin word as shown below :

4- Checking the Syntax of the New Module

When the source files are complete, check the syntax of the design to find errors
a) Verify that Synthesis/Implementation is selected from the drop-down list in
the Sources window.
b) Select the (and_1) design source in the Sources window to display the related
processes in the Processes window.
c) Click the “+” next to the Synthesize-XST process to expand the process group.
d) Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the
Console tab. If you continue without valid syntax, you will not be able to simulate or
synthesize your design.

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e) In the Processes window, choose Synthesis - XST and click the “+” to expand it, then,
click on the View RTL schematic to see schematic for (and_ 1) design.

5- Design Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test
bench. To create the test bench waveform follows:
a) Create a new test bench source by selecting Project → New Source.
b) In the New Source Wizard, select Test Bench Wave Form as the source type, and type
and_tbw in the File Name field and then Click Next as shown in the figure below.

c) The Associated Source page shows that you are associating the test bench waveform
with the source file (and_1). Click Next and then click Finish.
d) You need to set the clock frequency, setup time and output delay times in the Initialize
timing dialog box before the test bench waveform editing window opens as shown
below.
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(Recommended to use the default values in Experiment 1)

e) Click Finish to complete the timing initialization.

f) Now the Test Bench Wave Form window for (and_tbw) source will be appears, and
you can change the values of input signals by Click on the blue cell as shown below.

g) Save the waveform.

h) In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project as shown below.

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i) In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and
double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs
the simulation to the end of the test bench.

j) To view your simulation results, select the Simulation tab and zoom in on the
transitions.

k) Finally, Sketch the Simulate Behavioral Model waveform result and the RTL schematic
for project.
6- Repeat steps in 1 to 5 new project OR gate logic circuit and perform design simulation for
it.
7- Repeat steps in 1 to 5 new project XOR gate logic circuit and perform design simulation
for it.
Report :
1- Discuss all results obtained during experiment procedures.
2- What is a VHDL?
3- Name the two essential design elements in a VHDL program.
4- Write a VHDL code that computes a four-input XOR function. The input is a3:0, and the
output is y.
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