Session:-2018-19 Semester:-VII

Subject:-DSP Processor & Architecture

Assignment 1

Unit I: FUNDAMENTALS OF PROGRAMMABLE DSPs

1) Give difference between general purpose processor & DSP processor.
2) Explain the concept of Pipelining with example & explain how it increases the throughput efficiency.
3) Explain MAC Unit with its block diagram.
4) Give differences between Von Nuemann & Harvard architecture.
5) A DSP has a circular buffer with start & end address as 0200h & 020Fh respectively. what would be the
new values of the address pointer of the buffer if, in the course of address computation it gets updated
to i) 0212h ii) 01FCh

Unit II: ARCHITECTURE OF TMS320C5X

1) Explain Direct, Indirect & Memory mapped addressing in TMS320C5X with example.
2) Draw the architecture of TMS320C5X & explain CPU unit & Parallel logic unit.
3) Draw & Explain Status Register format for ST0 & ST1 in TMS320C5X processors.
4) List the on Chip memory in C5X architecture. Explain how these memories improve the system
performance & integration.

Unit III : Programming TMS320C5X

1) Let the content of ARP,AR2 & INDX register be 2 ,1250h & 2h respectively & contents of data memory
location 1240-1260h be filled with data 2345h.let sxm=0,Find the values of ACC & AR2 after
sequential execution of following Instructions.
LACC *,0
LACC*+,1
LACC *-,2
2) Explain Direct addressing mode of C5X.Explain execution of instruction ADDC 2Ch with address
generation if content of DP=06h & content of data memory location 0320h to032Fh are 20h.take
content of ACC=25h.
3) Let the content of ACC be 1234h.After executing the instruction ADD #2345h,2, what is the content of
ACC? Also explain the instruction ADD *,1,AR2.
4) Draw the table showing content of instruction pipeline when following program is executed.
ZAP
BPGM 1250h

ADD*
SACL *+
MAC 4500h,25h
PGM 1250h: LACC *+
5) Explain block diagram of DSP starter kit C5XDSK.What are the addresses of program memory space &
data memory space in DSP starter kit where user programs & data may be stored.
6) Let the initial content of ARP,AR1,ACC & data memory location 2100h be 2,2100h,1234h & 4563h
respectively, what will be the content of these registers & memory location after executing ADD
*,1,AR2.
7) Write ALP to add two numbers.
8) Draw the table showing content of instruction pipeline when following program is executed.
ZAP
BD PGM 1250h
ADD*
SACL *+
MAC 4500h,25h
PGM 1250h: LACC *+

Prof. Sanjay Balwani Prof. Mayuri Chawla

Prepared by Approved by

(HOD)